1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/leds/common.h> 9#include <dt-bindings/net/ti-dp83867.h> 10 11/ { 12 aliases { 13 rtc0 = &gsc_rtc; 14 rtc1 = &snvs_rtc; 15 }; 16 17 memory@40000000 { 18 device_type = "memory"; 19 reg = <0x0 0x40000000 0 0x80000000>; 20 }; 21 22 gpio-keys { 23 compatible = "gpio-keys"; 24 25 key-user-pb { 26 label = "user_pb"; 27 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 28 linux,code = <BTN_0>; 29 }; 30 31 key-user-pb1x { 32 label = "user_pb1x"; 33 linux,code = <BTN_1>; 34 interrupt-parent = <&gsc>; 35 interrupts = <0>; 36 }; 37 38 key-erased { 39 label = "key_erased"; 40 linux,code = <BTN_2>; 41 interrupt-parent = <&gsc>; 42 interrupts = <1>; 43 }; 44 45 key-eeprom-wp { 46 label = "eeprom_wp"; 47 linux,code = <BTN_3>; 48 interrupt-parent = <&gsc>; 49 interrupts = <2>; 50 }; 51 52 key-tamper { 53 label = "tamper"; 54 linux,code = <BTN_4>; 55 interrupt-parent = <&gsc>; 56 interrupts = <5>; 57 }; 58 59 switch-hold { 60 label = "switch_hold"; 61 linux,code = <BTN_5>; 62 interrupt-parent = <&gsc>; 63 interrupts = <7>; 64 }; 65 }; 66}; 67 68&A53_0 { 69 cpu-supply = <&buck3_reg>; 70}; 71 72&A53_1 { 73 cpu-supply = <&buck3_reg>; 74}; 75 76&A53_2 { 77 cpu-supply = <&buck3_reg>; 78}; 79 80&A53_3 { 81 cpu-supply = <&buck3_reg>; 82}; 83 84&ddrc { 85 operating-points-v2 = <&ddrc_opp_table>; 86 87 ddrc_opp_table: opp-table { 88 compatible = "operating-points-v2"; 89 90 opp-25000000 { 91 opp-hz = /bits/ 64 <25000000>; 92 }; 93 94 opp-100000000 { 95 opp-hz = /bits/ 64 <100000000>; 96 }; 97 98 opp-750000000 { 99 opp-hz = /bits/ 64 <750000000>; 100 }; 101 }; 102}; 103 104&fec1 { 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_fec1>; 107 phy-mode = "rgmii-id"; 108 phy-handle = <ðphy0>; 109 status = "okay"; 110 111 mdio { 112 #address-cells = <1>; 113 #size-cells = <0>; 114 115 ethphy0: ethernet-phy@0 { 116 compatible = "ethernet-phy-ieee802.3-c22"; 117 reg = <0>; 118 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 119 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 120 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 121 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 122 123 leds { 124 #address-cells = <1>; 125 #size-cells = <0>; 126 127 led@1 { 128 reg = <1>; 129 color = <LED_COLOR_ID_AMBER>; 130 function = LED_FUNCTION_LAN; 131 default-state = "keep"; 132 }; 133 134 led@2 { 135 reg = <2>; 136 color = <LED_COLOR_ID_GREEN>; 137 function = LED_FUNCTION_LAN; 138 default-state = "keep"; 139 }; 140 }; 141 }; 142 }; 143}; 144 145&i2c1 { 146 clock-frequency = <100000>; 147 pinctrl-names = "default", "gpio"; 148 pinctrl-0 = <&pinctrl_i2c1>; 149 pinctrl-1 = <&pinctrl_i2c1_gpio>; 150 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 151 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 152 status = "okay"; 153 154 gsc: gsc@20 { 155 compatible = "gw,gsc"; 156 reg = <0x20>; 157 pinctrl-0 = <&pinctrl_gsc>; 158 interrupt-parent = <&gpio2>; 159 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 160 interrupt-controller; 161 #interrupt-cells = <1>; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 165 adc { 166 compatible = "gw,gsc-adc"; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 170 channel@6 { 171 gw,mode = <0>; 172 reg = <0x06>; 173 label = "temp"; 174 }; 175 176 channel@8 { 177 gw,mode = <3>; 178 reg = <0x08>; 179 label = "vdd_bat"; 180 }; 181 182 channel@16 { 183 gw,mode = <4>; 184 reg = <0x16>; 185 label = "fan_tach"; 186 }; 187 188 channel@82 { 189 gw,mode = <2>; 190 reg = <0x82>; 191 label = "vdd_vin"; 192 gw,voltage-divider-ohms = <22100 1000>; 193 }; 194 195 channel@84 { 196 gw,mode = <2>; 197 reg = <0x84>; 198 label = "vdd_adc1"; 199 gw,voltage-divider-ohms = <10000 10000>; 200 }; 201 202 channel@86 { 203 gw,mode = <2>; 204 reg = <0x86>; 205 label = "vdd_adc2"; 206 gw,voltage-divider-ohms = <10000 10000>; 207 }; 208 209 channel@88 { 210 gw,mode = <2>; 211 reg = <0x88>; 212 label = "vdd_dram"; 213 }; 214 215 channel@8c { 216 gw,mode = <2>; 217 reg = <0x8c>; 218 label = "vdd_1p2"; 219 }; 220 221 channel@8e { 222 gw,mode = <2>; 223 reg = <0x8e>; 224 label = "vdd_1p0"; 225 }; 226 227 channel@90 { 228 gw,mode = <2>; 229 reg = <0x90>; 230 label = "vdd_2p5"; 231 gw,voltage-divider-ohms = <10000 10000>; 232 }; 233 234 channel@92 { 235 gw,mode = <2>; 236 reg = <0x92>; 237 label = "vdd_3p3"; 238 gw,voltage-divider-ohms = <10000 10000>; 239 }; 240 241 channel@98 { 242 gw,mode = <2>; 243 reg = <0x98>; 244 label = "vdd_0p95"; 245 }; 246 247 channel@9a { 248 gw,mode = <2>; 249 reg = <0x9a>; 250 label = "vdd_1p8"; 251 }; 252 253 channel@a2 { 254 gw,mode = <2>; 255 reg = <0xa2>; 256 label = "vdd_gsc"; 257 gw,voltage-divider-ohms = <10000 10000>; 258 }; 259 }; 260 261 fan-controller@0 { 262 compatible = "gw,gsc-fan"; 263 reg = <0x0a>; 264 }; 265 }; 266 267 gpio: gpio@23 { 268 compatible = "nxp,pca9555"; 269 reg = <0x23>; 270 gpio-controller; 271 #gpio-cells = <2>; 272 interrupt-parent = <&gsc>; 273 interrupts = <4>; 274 }; 275 276 eeprom@50 { 277 compatible = "atmel,24c02"; 278 reg = <0x50>; 279 pagesize = <16>; 280 }; 281 282 eeprom@51 { 283 compatible = "atmel,24c02"; 284 reg = <0x51>; 285 pagesize = <16>; 286 }; 287 288 eeprom@52 { 289 compatible = "atmel,24c02"; 290 reg = <0x52>; 291 pagesize = <16>; 292 }; 293 294 eeprom@53 { 295 compatible = "atmel,24c02"; 296 reg = <0x53>; 297 pagesize = <16>; 298 }; 299 300 gsc_rtc: rtc@68 { 301 compatible = "dallas,ds1672"; 302 reg = <0x68>; 303 }; 304 305 pmic@69 { 306 compatible = "mps,mp5416"; 307 reg = <0x69>; 308 309 regulators { 310 /* vdd_0p95: DRAM/GPU/VPU */ 311 buck1 { 312 regulator-name = "buck1"; 313 regulator-min-microvolt = <800000>; 314 regulator-max-microvolt = <1000000>; 315 regulator-min-microamp = <3800000>; 316 regulator-max-microamp = <6800000>; 317 regulator-boot-on; 318 regulator-always-on; 319 }; 320 321 /* vdd_soc */ 322 buck2 { 323 regulator-name = "buck2"; 324 regulator-min-microvolt = <800000>; 325 regulator-max-microvolt = <900000>; 326 regulator-min-microamp = <2200000>; 327 regulator-max-microamp = <5200000>; 328 regulator-boot-on; 329 regulator-always-on; 330 }; 331 332 /* vdd_arm */ 333 buck3_reg: buck3 { 334 regulator-name = "buck3"; 335 regulator-min-microvolt = <800000>; 336 regulator-max-microvolt = <1000000>; 337 regulator-min-microamp = <3800000>; 338 regulator-max-microamp = <6800000>; 339 regulator-always-on; 340 }; 341 342 /* vdd_1p8 */ 343 buck4 { 344 regulator-name = "buck4"; 345 regulator-min-microvolt = <1800000>; 346 regulator-max-microvolt = <1800000>; 347 regulator-min-microamp = <2200000>; 348 regulator-max-microamp = <5200000>; 349 regulator-boot-on; 350 regulator-always-on; 351 }; 352 353 /* nvcc_snvs_1p8 */ 354 ldo1 { 355 regulator-name = "ldo1"; 356 regulator-min-microvolt = <1800000>; 357 regulator-max-microvolt = <1800000>; 358 regulator-boot-on; 359 regulator-always-on; 360 }; 361 362 /* vdd_snvs_0p8 */ 363 ldo2 { 364 regulator-name = "ldo2"; 365 regulator-min-microvolt = <800000>; 366 regulator-max-microvolt = <800000>; 367 regulator-boot-on; 368 regulator-always-on; 369 }; 370 371 /* vdd_0p9 */ 372 ldo3 { 373 regulator-name = "ldo3"; 374 regulator-min-microvolt = <900000>; 375 regulator-max-microvolt = <900000>; 376 regulator-boot-on; 377 regulator-always-on; 378 }; 379 380 /* vdd_1p8 */ 381 ldo4 { 382 regulator-name = "ldo4"; 383 regulator-min-microvolt = <1800000>; 384 regulator-max-microvolt = <1800000>; 385 regulator-boot-on; 386 regulator-always-on; 387 }; 388 }; 389 }; 390}; 391 392&i2c2 { 393 clock-frequency = <400000>; 394 pinctrl-names = "default", "gpio"; 395 pinctrl-0 = <&pinctrl_i2c2>; 396 pinctrl-1 = <&pinctrl_i2c2_gpio>; 397 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 398 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 399 status = "okay"; 400 401 eeprom@52 { 402 compatible = "atmel,24c32"; 403 reg = <0x52>; 404 pagesize = <32>; 405 }; 406}; 407 408/* console */ 409&uart2 { 410 pinctrl-names = "default"; 411 pinctrl-0 = <&pinctrl_uart2>; 412 status = "okay"; 413}; 414 415/* eMMC */ 416&usdhc3 { 417 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 418 pinctrl-0 = <&pinctrl_usdhc3>; 419 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 420 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 421 assigned-clocks = <&clk IMX8MM_CLK_USDHC3>; 422 assigned-clock-rates = <400000000>; 423 bus-width = <8>; 424 non-removable; 425 status = "okay"; 426}; 427 428&wdog1 { 429 pinctrl-names = "default"; 430 pinctrl-0 = <&pinctrl_wdog>; 431 fsl,ext-reset-output; 432 status = "okay"; 433}; 434 435&iomuxc { 436 pinctrl_fec1: fec1grp { 437 fsl,pins = < 438 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 439 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 440 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 441 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 442 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 443 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 444 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 445 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 446 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 447 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 448 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 449 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 450 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 451 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 452 MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 453 >; 454 }; 455 456 pinctrl_gsc: gscgrp { 457 fsl,pins = < 458 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x159 459 >; 460 }; 461 462 pinctrl_i2c1: i2c1grp { 463 fsl,pins = < 464 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 465 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 466 >; 467 }; 468 469 pinctrl_i2c1_gpio: i2c1gpiogrp { 470 fsl,pins = < 471 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 472 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 473 >; 474 }; 475 476 pinctrl_i2c2: i2c2grp { 477 fsl,pins = < 478 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 479 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 480 >; 481 }; 482 483 pinctrl_i2c2_gpio: i2c2gpiogrp { 484 fsl,pins = < 485 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 486 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 487 >; 488 }; 489 490 pinctrl_uart2: uart2grp { 491 fsl,pins = < 492 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 493 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 494 >; 495 }; 496 497 pinctrl_usdhc3: usdhc3grp { 498 fsl,pins = < 499 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 500 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 501 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 502 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 503 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 504 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 505 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 506 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 507 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 508 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 509 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 510 >; 511 }; 512 513 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 514 fsl,pins = < 515 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 516 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 517 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 518 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 519 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 520 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 521 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 522 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 523 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 524 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 525 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 526 >; 527 }; 528 529 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 530 fsl,pins = < 531 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 532 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 533 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 534 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 535 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 536 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 537 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 538 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 539 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 540 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 541 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 542 >; 543 }; 544 545 pinctrl_wdog: wdoggrp { 546 fsl,pins = < 547 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 548 >; 549 }; 550}; 551