1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2023 PHYTEC Messtechnik GmbH 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/input/linux-event-codes.h> 9#include <dt-bindings/leds/common.h> 10#include "imx8mm-phycore-som.dtsi" 11 12/ { 13 model = "PHYTEC phyGATE-Tauri-L-iMX8MM"; 14 compatible = "phytec,imx8mm-phygate-tauri-l", 15 "phytec,imx8mm-phycore-som", "fsl,imx8mm"; 16 17 chosen { 18 stdout-path = &uart3; 19 }; 20 21 can_osc_40m: clock-can { 22 compatible = "fixed-clock"; 23 clock-frequency = <40000000>; 24 clock-output-names = "can_osc_40m"; 25 #clock-cells = <0>; 26 }; 27 28 gpio-keys { 29 compatible = "gpio-keys"; 30 pinctrl-names = "default"; 31 pinctrl-0 = <&pinctrl_gpiokeys>; 32 33 key { 34 gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 35 label = "KEY-A"; 36 linux,code = <KEY_A>; 37 }; 38 }; 39 40 leds { 41 compatible = "gpio-leds"; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_leds>; 44 45 led-1 { 46 color = <LED_COLOR_ID_RED>; 47 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 48 linux,default-trigger = "none"; 49 }; 50 51 led-2 { 52 color = <LED_COLOR_ID_YELLOW>; 53 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; 54 linux,default-trigger = "none"; 55 }; 56 }; 57 58 usdhc1_pwrseq: pwr-seq { 59 compatible = "mmc-pwrseq-simple"; 60 post-power-on-delay-ms = <100>; 61 power-off-delay-us = <60>; 62 reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; 63 }; 64 65 reg_usb_hub_vbus: regulator-hub-otg1 { 66 compatible = "regulator-fixed"; 67 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 68 enable-active-high; 69 pinctrl-names = "default"; 70 pinctrl-0 = <&pinctrl_usbhubpwr>; 71 regulator-name = "usb_hub_vbus"; 72 regulator-max-microvolt = <5000000>; 73 regulator-min-microvolt = <5000000>; 74 }; 75 76 reg_usb_otg1_vbus: regulator-usb-otg1 { 77 compatible = "regulator-fixed"; 78 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 79 enable-active-high; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_usbotg1pwr>; 82 regulator-name = "usb_otg1_vbus"; 83 regulator-max-microvolt = <5000000>; 84 regulator-min-microvolt = <5000000>; 85 }; 86 87 reg_usdhc2_vmmc: regulator-usdhc2 { 88 compatible = "regulator-fixed"; 89 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 90 enable-active-high; 91 off-on-delay-us = <20000>; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 94 regulator-max-microvolt = <3300000>; 95 regulator-min-microvolt = <3300000>; 96 regulator-name = "VSD_3V3"; 97 }; 98}; 99 100&ecspi1 { 101 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, 102 <&gpio5 13 GPIO_ACTIVE_LOW>, 103 <&gpio5 2 GPIO_ACTIVE_LOW>; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 status = "okay"; 109 110 /* CAN MCP251XFD */ 111 can0: can@0 { 112 compatible = "microchip,mcp251xfd"; 113 reg = <0>; 114 clocks = <&can_osc_40m>; 115 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 116 interrupt-parent = <&gpio1>; 117 pinctrl-names = "default"; 118 pinctrl-0 = <&pinctrl_can_int>; 119 spi-max-frequency = <10000000>; 120 }; 121 122 tpm: tpm@1 { 123 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 124 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 125 interrupt-parent = <&gpio2>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_tpm>; 128 reg = <1>; 129 spi-max-frequency = <38000000>; 130 }; 131}; 132 133&i2c2 { 134 clock-frequency = <400000>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_i2c2>; 137 pinctrl-1 = <&pinctrl_i2c2_gpio>; 138 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 139 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 140 status = "okay"; 141 142 temp_sense0: temperature-sensor@49 { 143 compatible = "ti,tmp102"; 144 reg = <0x49>; 145 interrupt-parent = <&gpio4>; 146 interrupts = <31 IRQ_TYPE_LEVEL_LOW>; 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_tempsense>; 149 #thermal-sensor-cells = <1>; 150 }; 151}; 152 153&i2c3 { 154 clock-frequency = <400000>; 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_i2c3>; 157 pinctrl-1 = <&pinctrl_i2c3_gpio>; 158 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 159 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 160 status = "okay"; 161}; 162 163&i2c4 { 164 clock-frequency = <400000>; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_i2c4>; 167 pinctrl-1 = <&pinctrl_i2c4_gpio>; 168 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 169 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 170 status = "okay"; 171}; 172 173/* PCIe */ 174&pcie0 { 175 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 176 <&clk IMX8MM_CLK_PCIE1_PHY>, 177 <&clk IMX8MM_CLK_PCIE1_CTRL>; 178 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 179 <&clk IMX8MM_SYS_PLL2_100M>, 180 <&clk IMX8MM_SYS_PLL2_250M>; 181 assigned-clock-rates = <10000000>, <100000000>, <250000000>; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_pcie>; 184 reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; 185 status = "okay"; 186}; 187 188&pwm1 { 189 pinctrl-names = "default"; 190 pinctrl-0 = <&pinctrl_pwm1>; 191 status = "okay"; 192}; 193 194&pwm3 { 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_pwm3>; 197 status = "okay"; 198}; 199 200&pwm4 { 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_pwm4>; 203 status = "okay"; 204}; 205 206/* RTC */ 207&rv3028 { 208 trickle-resistor-ohms = <3000>; 209}; 210 211&uart1 { 212 assigned-clocks = <&clk IMX8MM_CLK_UART1>; 213 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_uart1>; 216 status = "okay"; 217}; 218 219/* UART2 - RS232 */ 220&uart2 { 221 assigned-clocks = <&clk IMX8MM_CLK_UART2>; 222 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_uart2>; 225 status = "okay"; 226}; 227 228/* UART - console */ 229&uart3 { 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_uart3>; 232 status = "okay"; 233}; 234 235/* USB */ 236&usbotg1 { 237 adp-disable; 238 dr_mode = "otg"; 239 over-current-active-low; 240 samsung,picophy-pre-emp-curr-control = <3>; 241 samsung,picophy-dc-vol-level-adjust = <7>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_usbotg1>; 244 srp-disable; 245 vbus-supply = <®_usb_otg1_vbus>; 246 status = "okay"; 247}; 248 249&usbotg2 { 250 disable-over-current; 251 dr_mode = "host"; 252 samsung,picophy-pre-emp-curr-control = <3>; 253 samsung,picophy-dc-vol-level-adjust = <7>; 254 vbus-supply = <®_usb_hub_vbus>; 255 status = "okay"; 256}; 257 258/* SD-Card */ 259&usdhc2 { 260 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 261 assigned-clock-rates = <200000000>; 262 bus-width = <4>; 263 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 264 disable-wp; 265 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 266 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 267 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 268 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 269 vmmc-supply = <®_usdhc2_vmmc>; 270 vqmmc-supply = <®_nvcc_sd2>; 271 status = "okay"; 272}; 273 274&iomuxc { 275 pinctrl_can_int: can-intgrp { 276 fsl,pins = < 277 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 278 >; 279 }; 280 281 pinctrl_ecspi1: ecspi1grp { 282 fsl,pins = < 283 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 284 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 285 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 286 >; 287 }; 288 289 pinctrl_ecspi1_cs: ecspi1csgrp { 290 fsl,pins = < 291 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 292 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00 293 MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00 294 >; 295 }; 296 297 pinctrl_gpiokeys: keygrp { 298 fsl,pins = < 299 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 300 >; 301 }; 302 303 pinctrl_i2c2: i2c2grp { 304 fsl,pins = < 305 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 306 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 307 >; 308 }; 309 310 pinctrl_i2c2_gpio: i2c2gpiogrp { 311 fsl,pins = < 312 MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0 313 MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0 314 >; 315 }; 316 317 318 pinctrl_i2c3: i2c3grp { 319 fsl,pins = < 320 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 321 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 322 >; 323 }; 324 325 pinctrl_i2c3_gpio: i2c3gpiogrp { 326 fsl,pins = < 327 MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0 328 MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0 329 >; 330 }; 331 332 pinctrl_i2c4: i2c4grp { 333 fsl,pins = < 334 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 335 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 336 >; 337 }; 338 339 pinctrl_i2c4_gpio: i2c4gpiogrp { 340 fsl,pins = < 341 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0 342 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0 343 >; 344 }; 345 346 pinctrl_leds: leds1grp { 347 fsl,pins = < 348 MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00 349 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00 350 >; 351 }; 352 353 pinctrl_pcie: pciegrp { 354 fsl,pins = < 355 /* COEX2 */ 356 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00 357 /* COEX1 */ 358 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 359 >; 360 }; 361 362 pinctrl_pwm1: pwm1grp { 363 fsl,pins = < 364 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40 365 >; 366 }; 367 368 pinctrl_pwm3: pwm3grp { 369 fsl,pins = < 370 MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40 371 >; 372 }; 373 374 pinctrl_pwm4: pwm4grp { 375 fsl,pins = < 376 MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40 377 >; 378 }; 379 380 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 381 fsl,pins = < 382 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 383 >; 384 }; 385 386 pinctrl_tempsense: tempsensegrp { 387 fsl,pins = < 388 MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00 389 >; 390 }; 391 392 pinctrl_tpm: tpmgrp { 393 fsl,pins = < 394 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 395 >; 396 }; 397 398 pinctrl_uart1: uart1grp { 399 fsl,pins = < 400 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00 401 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00 402 >; 403 }; 404 405 pinctrl_uart2: uart2grp { 406 fsl,pins = < 407 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 408 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 409 >; 410 }; 411 412 pinctrl_uart3: uart3grp { 413 fsl,pins = < 414 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 415 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 416 >; 417 }; 418 419 pinctrl_usbhubpwr: usbhubpwrgrp { 420 fsl,pins = < 421 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00 422 >; 423 }; 424 425 pinctrl_usbotg1pwr: usbotg1pwrgrp { 426 fsl,pins = < 427 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 428 >; 429 }; 430 431 pinctrl_usbotg1: usbotg1grp { 432 fsl,pins = < 433 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80 434 >; 435 }; 436 437 pinctrl_usdhc1: usdhc1grp { 438 fsl,pins = < 439 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 440 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 441 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 442 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 443 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 444 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 445 >; 446 }; 447 448 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 449 fsl,pins = < 450 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 451 >; 452 }; 453 454 pinctrl_usdhc2: usdhc2grp { 455 fsl,pins = < 456 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 457 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 458 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 459 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 460 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 461 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 462 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 463 >; 464 }; 465 466 pinctrl_usdhc2_100mhz: usdhc2100mhzgrp { 467 fsl,pins = < 468 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 469 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 470 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 471 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 472 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 473 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 474 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 475 >; 476 }; 477 478 pinctrl_usdhc2_200mhz: usdhc2200mhzgrp { 479 fsl,pins = < 480 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 481 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 482 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 483 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 484 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 485 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 486 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 487 >; 488 }; 489}; 490