1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Fabio Estevam <festevam@denx.de> 4 */ 5 6/dts-v1/; 7 8#include "imx8mm-tqma8mqml.dtsi" 9 10/ { 11 model = "Cloos i.MX8MM PHG board"; 12 compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; 13 14 aliases { 15 mmc0 = &usdhc3; 16 mmc1 = &usdhc2; 17 }; 18 19 chosen { 20 stdout-path = &uart2; 21 }; 22 23 beeper { 24 compatible = "gpio-beeper"; 25 pinctrl-0 = <&pinctrl_beeper>; 26 gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; 27 }; 28 29 leds { 30 compatible = "gpio-leds"; 31 pinctrl-names = "default"; 32 pinctrl-0 = <&pinctrl_gpio_led>; 33 34 led-0 { 35 label = "status1"; 36 gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 37 }; 38 39 led-1 { 40 label = "status2"; 41 gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 42 }; 43 44 led-2 { 45 label = "status3"; 46 gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 47 }; 48 49 led-3 { 50 label = "run"; 51 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 52 }; 53 54 led-4 { 55 label = "powerled"; 56 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 57 }; 58 }; 59 60 reg_usb_otg_vbus: regulator-usb-otg-vbus { 61 compatible = "regulator-fixed"; 62 pinctrl-names = "default"; 63 pinctrl-0 = <&pinctrl_otg_vbus_ctrl>; 64 regulator-name = "usb_otg_vbus"; 65 regulator-min-microvolt = <5000000>; 66 regulator-max-microvolt = <5000000>; 67 gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; 68 enable-active-high; 69 }; 70 71 reg_usdhc2_vmmc: regulator-vmmc { 72 compatible = "regulator-fixed"; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 75 regulator-name = "VSD_3V3"; 76 regulator-min-microvolt = <3300000>; 77 regulator-max-microvolt = <3300000>; 78 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 79 enable-active-high; 80 startup-delay-us = <100>; 81 off-on-delay-us = <12000>; 82 }; 83 84 panel { 85 compatible = "panel-lvds"; 86 width-mm = <170>; 87 height-mm = <28>; 88 data-mapping = "jeida-18"; 89 90 panel-timing { 91 clock-frequency = <49500000>; 92 hactive = <800>; 93 hback-porch = <48>; 94 hfront-porch = <312>; 95 hsync-len = <40>; 96 vactive = <600>; 97 vback-porch = <19>; 98 vfront-porch = <61>; 99 vsync-len = <20>; 100 hsync-active = <0>; 101 vsync-active = <0>; 102 de-active = <1>; 103 pixelclk-active = <1>; 104 }; 105 106 port { 107 panel_out_bridge: endpoint { 108 remote-endpoint = <&bridge_out_panel>; 109 }; 110 }; 111 }; 112}; 113 114/* QSPI is not populated on the SoM */ 115&flexspi { 116 status = "disabled"; 117}; 118 119&ecspi1 { 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_ecspi1>; 122 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 123 status = "okay"; 124}; 125 126&fec1 { 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_fec1>; 129 phy-mode = "rgmii-id"; 130 phy-handle = <ðphy0>; 131 fsl,magic-packet; 132 status = "okay"; 133 134 mdio { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 ethphy0: ethernet-phy@0 { 139 reg = <0>; 140 compatible = "ethernet-phy-ieee802.3-c22"; 141 }; 142 }; 143}; 144 145&i2c2 { 146 clock-frequency = <100000>; 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_i2c2>; 149 status = "okay"; 150 151 bridge@2c { 152 compatible = "ti,sn65dsi83"; 153 reg = <0x2c>; 154 enable-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_dsi_bridge>; 157 158 ports { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 162 port@0 { 163 reg = <0>; 164 165 bridge_in_dsi: endpoint { 166 remote-endpoint = <&dsi_out_bridge>; 167 data-lanes = <1 2 3 4>; 168 }; 169 }; 170 171 port@2 { 172 reg = <2>; 173 174 bridge_out_panel: endpoint { 175 remote-endpoint = <&panel_out_bridge>; 176 }; 177 }; 178 }; 179 }; 180}; 181 182&lcdif { 183 status = "okay"; 184}; 185 186&mipi_dsi { 187 samsung,esc-clock-frequency = <10000000>; 188 status = "okay"; 189 190 ports { 191 port@1 { 192 reg = <1>; 193 194 dsi_out_bridge: endpoint { 195 data-lanes = <1 2>; 196 lane-polarities = <1 0 0 0 0>; 197 remote-endpoint = <&bridge_in_dsi>; 198 }; 199 }; 200 }; 201}; 202 203 204&uart2 { 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_uart2>; 207 status = "okay"; 208}; 209 210&usbphynop1 { 211 power-domains = <&pgc_otg1>; 212}; 213 214&usbphynop2 { 215 power-domains = <&pgc_otg2>; 216}; 217 218&usbotg1 { 219 dr_mode = "host"; 220 vbus-supply = <®_usb_otg_vbus>; 221 status = "okay"; 222}; 223 224&usbotg2 { 225 dr_mode = "host"; 226 status = "okay"; 227}; 228 229&usdhc2 { 230 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 231 assigned-clock-rates = <400000000>; 232 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; 233 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 234 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 235 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 236 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 237 bus-width = <4>; 238 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 239 disable-wp; 240 no-mmc; 241 no-sdio; 242 sd-uhs-sdr104; 243 sd-uhs-ddr50; 244 vmmc-supply = <®_usdhc2_vmmc>; 245 status = "okay"; 246}; 247 248&iomuxc { 249 pinctrl_beeper: beepergrp { 250 fsl,pins = < 251 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19 252 >; 253 }; 254 255 pinctrl_dsi_bridge: dsibridgeggrp { 256 fsl,pins = < 257 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x19 258 >; 259 }; 260 261 pinctrl_ecspi1: ecspi1grp { 262 fsl,pins = < 263 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 264 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 265 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 266 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 267 >; 268 }; 269 270 pinctrl_fec1: fec1grp { 271 fsl,pins = < 272 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x40000002 273 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x40000002 274 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x14 275 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x14 276 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x14 277 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x14 278 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 279 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 280 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 281 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 282 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x14 283 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 284 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 285 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14 286 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x10 287 >; 288 }; 289 290 pinctrl_gpio_led: gpioledgrp { 291 fsl,pins = < 292 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 293 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 294 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 295 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 296 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 297 >; 298 }; 299 300 pinctrl_i2c2: i2c2grp { 301 fsl,pins = < 302 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 303 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 304 >; 305 }; 306 307 pinctrl_otg_vbus_ctrl: otgvbusctrlgrp { 308 fsl,pins = < 309 MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x119 310 >; 311 }; 312 313 pinctrl_uart2: uart2grp { 314 fsl,pins = < 315 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 316 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 317 >; 318 }; 319 320 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { 321 fsl,pins = < 322 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 323 >; 324 }; 325 326 pinctrl_usdhc2: usdhc2grp { 327 fsl,pins = < 328 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 329 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 330 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 331 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 332 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 333 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 334 >; 335 }; 336 337 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 338 fsl,pins = < 339 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 340 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 341 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 342 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 343 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 344 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 345 >; 346 }; 347 348 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 349 fsl,pins = < 350 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 351 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 352 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 353 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 354 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 355 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 356 >; 357 }; 358}; 359