1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Copyright (C) 2019 Kontron Electronics GmbH 4 */ 5 6#include "imx8mm.dtsi" 7 8/ { 9 model = "Kontron SL i.MX8MM (N801X SOM)"; 10 compatible = "kontron,imx8mm-sl", "fsl,imx8mm"; 11 12 memory@40000000 { 13 device_type = "memory"; 14 /* 15 * There are multiple SoM flavors with different DDR sizes. 16 * The smallest is 1GB. For larger sizes the bootloader will 17 * update the reg property. 18 */ 19 reg = <0x0 0x40000000 0 0x80000000>; 20 }; 21 22 chosen { 23 stdout-path = &uart3; 24 }; 25}; 26 27&A53_0 { 28 cpu-supply = <®_vdd_arm>; 29}; 30 31&A53_1 { 32 cpu-supply = <®_vdd_arm>; 33}; 34 35&A53_2 { 36 cpu-supply = <®_vdd_arm>; 37}; 38 39&A53_3 { 40 cpu-supply = <®_vdd_arm>; 41}; 42 43&ddrc { 44 operating-points-v2 = <&ddrc_opp_table>; 45 46 ddrc_opp_table: opp-table { 47 compatible = "operating-points-v2"; 48 49 opp-100000000 { 50 opp-hz = /bits/ 64 <100000000>; 51 }; 52 53 opp-750000000 { 54 opp-hz = /bits/ 64 <750000000>; 55 }; 56 }; 57}; 58 59&ecspi1 { 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_ecspi1>; 62 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 63 status = "okay"; 64 65 flash@0 { 66 compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; 67 spi-max-frequency = <80000000>; 68 reg = <0>; 69 70 partitions { 71 compatible = "fixed-partitions"; 72 #address-cells = <1>; 73 #size-cells = <1>; 74 75 partition@0 { 76 label = "u-boot"; 77 reg = <0x0 0x1e0000>; 78 }; 79 80 partition@1e0000 { 81 label = "env"; 82 reg = <0x1e0000 0x10000>; 83 }; 84 85 partition@1f0000 { 86 label = "env_redundant"; 87 reg = <0x1f0000 0x10000>; 88 }; 89 }; 90 }; 91}; 92 93&i2c1 { 94 clock-frequency = <400000>; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_i2c1>; 97 status = "okay"; 98 99 pca9450: pmic@25 { 100 compatible = "nxp,pca9450a"; 101 reg = <0x25>; 102 pinctrl-names = "default"; 103 pinctrl-0 = <&pinctrl_pmic>; 104 interrupt-parent = <&gpio1>; 105 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 106 107 regulators { 108 reg_vdd_soc: BUCK1 { 109 regulator-name = "+0V8_VDD_SOC (BUCK1)"; 110 regulator-min-microvolt = <800000>; 111 regulator-max-microvolt = <850000>; 112 regulator-boot-on; 113 regulator-always-on; 114 regulator-ramp-delay = <3125>; 115 nxp,dvs-run-voltage = <850000>; 116 nxp,dvs-standby-voltage = <800000>; 117 }; 118 119 reg_vdd_arm: BUCK2 { 120 regulator-name = "+0V9_VDD_ARM (BUCK2)"; 121 regulator-min-microvolt = <850000>; 122 regulator-max-microvolt = <950000>; 123 regulator-boot-on; 124 regulator-always-on; 125 regulator-ramp-delay = <3125>; 126 nxp,dvs-run-voltage = <950000>; 127 nxp,dvs-standby-voltage = <850000>; 128 }; 129 130 reg_vdd_dram: BUCK3 { 131 regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)"; 132 regulator-min-microvolt = <850000>; 133 regulator-max-microvolt = <950000>; 134 regulator-boot-on; 135 regulator-always-on; 136 }; 137 138 reg_vdd_3v3: BUCK4 { 139 regulator-name = "+3V3 (BUCK4)"; 140 regulator-min-microvolt = <3300000>; 141 regulator-max-microvolt = <3300000>; 142 regulator-boot-on; 143 regulator-always-on; 144 }; 145 146 reg_vdd_1v8: BUCK5 { 147 regulator-name = "+1V8 (BUCK5)"; 148 regulator-min-microvolt = <1800000>; 149 regulator-max-microvolt = <1800000>; 150 regulator-boot-on; 151 regulator-always-on; 152 }; 153 154 reg_nvcc_dram: BUCK6 { 155 regulator-name = "+1V1_NVCC_DRAM (BUCK6)"; 156 regulator-min-microvolt = <1100000>; 157 regulator-max-microvolt = <1100000>; 158 regulator-boot-on; 159 regulator-always-on; 160 }; 161 162 reg_nvcc_snvs: LDO1 { 163 regulator-name = "+1V8_NVCC_SNVS (LDO1)"; 164 regulator-min-microvolt = <1800000>; 165 regulator-max-microvolt = <1800000>; 166 regulator-boot-on; 167 regulator-always-on; 168 }; 169 170 reg_vdd_snvs: LDO2 { 171 regulator-name = "+0V8_VDD_SNVS (LDO2)"; 172 regulator-min-microvolt = <800000>; 173 regulator-max-microvolt = <900000>; 174 regulator-boot-on; 175 regulator-always-on; 176 }; 177 178 reg_vdda: LDO3 { 179 regulator-name = "+1V8_VDDA (LDO3)"; 180 regulator-min-microvolt = <1800000>; 181 regulator-max-microvolt = <1800000>; 182 regulator-boot-on; 183 regulator-always-on; 184 }; 185 186 reg_vdd_phy: LDO4 { 187 regulator-name = "+0V9_VDD_PHY (LDO4)"; 188 regulator-min-microvolt = <900000>; 189 regulator-max-microvolt = <900000>; 190 regulator-boot-on; 191 regulator-always-on; 192 }; 193 194 reg_nvcc_sd: LDO5 { 195 regulator-name = "NVCC_SD (LDO5)"; 196 regulator-min-microvolt = <1800000>; 197 regulator-max-microvolt = <3300000>; 198 }; 199 }; 200 }; 201}; 202 203&uart3 { /* console */ 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_uart3>; 206 status = "okay"; 207}; 208 209&usdhc1 { 210 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 211 pinctrl-0 = <&pinctrl_usdhc1>; 212 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 213 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 214 vmmc-supply = <®_vdd_3v3>; 215 vqmmc-supply = <®_vdd_1v8>; 216 bus-width = <8>; 217 non-removable; 218 status = "okay"; 219}; 220 221&wdog1 { 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pinctrl_wdog>; 224 fsl,ext-reset-output; 225 status = "okay"; 226}; 227 228&iomuxc { 229 pinctrl_ecspi1: ecspi1grp { 230 fsl,pins = < 231 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 232 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 233 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 234 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 235 >; 236 }; 237 238 pinctrl_i2c1: i2c1grp { 239 fsl,pins = < 240 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 241 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 242 >; 243 }; 244 245 pinctrl_pmic: pmicgrp { 246 fsl,pins = < 247 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 248 >; 249 }; 250 251 pinctrl_uart3: uart3grp { 252 fsl,pins = < 253 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 254 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 255 >; 256 }; 257 258 pinctrl_usdhc1: usdhc1grp { 259 fsl,pins = < 260 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 261 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 262 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 263 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 264 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 265 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 266 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 267 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 268 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 269 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 270 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 271 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 272 >; 273 }; 274 275 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 276 fsl,pins = < 277 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 278 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 279 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 280 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 281 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 282 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 283 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 284 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 285 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 286 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 287 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 288 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 289 >; 290 }; 291 292 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 293 fsl,pins = < 294 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 295 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 296 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 297 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 298 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 299 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 300 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 301 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 302 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 303 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 304 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 305 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 306 >; 307 }; 308 309 pinctrl_wdog: wdoggrp { 310 fsl,pins = < 311 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 312 >; 313 }; 314}; 315