1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Copyright (C) 2019 Kontron Electronics GmbH 4 */ 5 6#include "imx8mm.dtsi" 7 8/ { 9 model = "Kontron i.MX8MM N801X SoM"; 10 compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm"; 11 12 memory@40000000 { 13 device_type = "memory"; 14 /* 15 * There are multiple SoM flavors with different DDR sizes. 16 * The smallest is 1GB. For larger sizes the bootloader will 17 * update the reg property. 18 */ 19 reg = <0x0 0x40000000 0 0x80000000>; 20 }; 21 22 chosen { 23 stdout-path = &uart3; 24 }; 25}; 26 27&A53_0 { 28 cpu-supply = <®_vdd_arm>; 29}; 30 31&A53_1 { 32 cpu-supply = <®_vdd_arm>; 33}; 34 35&A53_2 { 36 cpu-supply = <®_vdd_arm>; 37}; 38 39&A53_3 { 40 cpu-supply = <®_vdd_arm>; 41}; 42 43&ddrc { 44 operating-points-v2 = <&ddrc_opp_table>; 45 46 ddrc_opp_table: opp-table { 47 compatible = "operating-points-v2"; 48 49 opp-25M { 50 opp-hz = /bits/ 64 <25000000>; 51 }; 52 53 opp-100M { 54 opp-hz = /bits/ 64 <100000000>; 55 }; 56 57 opp-750M { 58 opp-hz = /bits/ 64 <750000000>; 59 }; 60 }; 61}; 62 63&ecspi1 { 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_ecspi1>; 66 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 67 status = "okay"; 68 69 flash@0 { 70 compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; 71 spi-max-frequency = <80000000>; 72 reg = <0>; 73 }; 74}; 75 76&i2c1 { 77 clock-frequency = <400000>; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&pinctrl_i2c1>; 80 status = "okay"; 81 82 pca9450: pmic@25 { 83 compatible = "nxp,pca9450a"; 84 reg = <0x25>; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pinctrl_pmic>; 87 interrupt-parent = <&gpio1>; 88 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 89 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 90 91 regulators { 92 reg_vdd_soc: BUCK1 { 93 regulator-name = "buck1"; 94 regulator-min-microvolt = <800000>; 95 regulator-max-microvolt = <850000>; 96 regulator-boot-on; 97 regulator-always-on; 98 regulator-ramp-delay = <3125>; 99 nxp,dvs-run-voltage = <850000>; 100 nxp,dvs-standby-voltage = <800000>; 101 }; 102 103 reg_vdd_arm: BUCK2 { 104 regulator-name = "buck2"; 105 regulator-min-microvolt = <850000>; 106 regulator-max-microvolt = <950000>; 107 regulator-boot-on; 108 regulator-always-on; 109 regulator-ramp-delay = <3125>; 110 nxp,dvs-run-voltage = <950000>; 111 nxp,dvs-standby-voltage = <850000>; 112 }; 113 114 reg_vdd_dram: BUCK3 { 115 regulator-name = "buck3"; 116 regulator-min-microvolt = <850000>; 117 regulator-max-microvolt = <950000>; 118 regulator-boot-on; 119 regulator-always-on; 120 }; 121 122 reg_vdd_3v3: BUCK4 { 123 regulator-name = "buck4"; 124 regulator-min-microvolt = <3300000>; 125 regulator-max-microvolt = <3300000>; 126 regulator-boot-on; 127 regulator-always-on; 128 }; 129 130 reg_vdd_1v8: BUCK5 { 131 regulator-name = "buck5"; 132 regulator-min-microvolt = <1800000>; 133 regulator-max-microvolt = <1800000>; 134 regulator-boot-on; 135 regulator-always-on; 136 }; 137 138 reg_nvcc_dram: BUCK6 { 139 regulator-name = "buck6"; 140 regulator-min-microvolt = <1100000>; 141 regulator-max-microvolt = <1100000>; 142 regulator-boot-on; 143 regulator-always-on; 144 }; 145 146 reg_nvcc_snvs: LDO1 { 147 regulator-name = "ldo1"; 148 regulator-min-microvolt = <1800000>; 149 regulator-max-microvolt = <1800000>; 150 regulator-boot-on; 151 regulator-always-on; 152 }; 153 154 reg_vdd_snvs: LDO2 { 155 regulator-name = "ldo2"; 156 regulator-min-microvolt = <800000>; 157 regulator-max-microvolt = <900000>; 158 regulator-boot-on; 159 regulator-always-on; 160 }; 161 162 reg_vdda: LDO3 { 163 regulator-name = "ldo3"; 164 regulator-min-microvolt = <1800000>; 165 regulator-max-microvolt = <1800000>; 166 regulator-boot-on; 167 regulator-always-on; 168 }; 169 170 reg_vdd_phy: LDO4 { 171 regulator-name = "ldo4"; 172 regulator-min-microvolt = <900000>; 173 regulator-max-microvolt = <900000>; 174 regulator-boot-on; 175 regulator-always-on; 176 }; 177 178 reg_nvcc_sd: LDO5 { 179 regulator-name = "ldo5"; 180 regulator-min-microvolt = <1800000>; 181 regulator-max-microvolt = <3300000>; 182 }; 183 }; 184 }; 185}; 186 187&uart3 { /* console */ 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_uart3>; 190 status = "okay"; 191}; 192 193&usdhc1 { 194 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 195 pinctrl-0 = <&pinctrl_usdhc1>; 196 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 197 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 198 vmmc-supply = <®_vdd_3v3>; 199 vqmmc-supply = <®_vdd_1v8>; 200 bus-width = <8>; 201 non-removable; 202 status = "okay"; 203}; 204 205&wdog1 { 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_wdog>; 208 fsl,ext-reset-output; 209 status = "okay"; 210}; 211 212&iomuxc { 213 pinctrl_ecspi1: ecspi1grp { 214 fsl,pins = < 215 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 216 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 217 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 218 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 219 >; 220 }; 221 222 pinctrl_i2c1: i2c1grp { 223 fsl,pins = < 224 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 225 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 226 >; 227 }; 228 229 pinctrl_pmic: pmicgrp { 230 fsl,pins = < 231 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 232 MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141 233 >; 234 }; 235 236 pinctrl_uart3: uart3grp { 237 fsl,pins = < 238 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 239 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 240 >; 241 }; 242 243 pinctrl_usdhc1: usdhc1grp { 244 fsl,pins = < 245 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 246 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 247 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 248 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 249 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 250 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 251 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 252 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 253 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 254 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 255 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 256 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 257 >; 258 }; 259 260 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 261 fsl,pins = < 262 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 263 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 264 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 265 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 266 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 267 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 268 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 269 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 270 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 271 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 272 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 273 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 274 >; 275 }; 276 277 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 278 fsl,pins = < 279 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 280 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 281 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 282 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 283 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 284 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 285 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 286 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 287 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 288 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 289 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 290 MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 291 >; 292 }; 293 294 pinctrl_wdog: wdoggrp { 295 fsl,pins = < 296 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 297 >; 298 }; 299}; 300