1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx8mm.dtsi" 10 11/ { 12 chosen { 13 stdout-path = &uart2; 14 }; 15 16 memory@40000000 { 17 device_type = "memory"; 18 reg = <0x0 0x40000000 0 0x80000000>; 19 }; 20 21 leds { 22 compatible = "gpio-leds"; 23 pinctrl-names = "default"; 24 pinctrl-0 = <&pinctrl_gpio_led>; 25 26 status { 27 label = "status"; 28 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 29 default-state = "on"; 30 }; 31 }; 32 33 reg_usdhc2_vmmc: regulator-usdhc2 { 34 compatible = "regulator-fixed"; 35 pinctrl-names = "default"; 36 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 37 regulator-name = "VSD_3V3"; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 41 enable-active-high; 42 }; 43 44 ir-receiver { 45 compatible = "gpio-ir-receiver"; 46 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 47 pinctrl-names = "default"; 48 pinctrl-0 = <&pinctrl_ir>; 49 linux,autosuspend-period = <125>; 50 }; 51 52 wm8524: audio-codec { 53 #sound-dai-cells = <0>; 54 compatible = "wlf,wm8524"; 55 pinctrl-names = "default"; 56 pinctrl-0 = <&pinctrl_gpio_wlf>; 57 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; 58 }; 59 60 sound-wm8524 { 61 compatible = "simple-audio-card"; 62 simple-audio-card,name = "wm8524-audio"; 63 simple-audio-card,format = "i2s"; 64 simple-audio-card,frame-master = <&cpudai>; 65 simple-audio-card,bitclock-master = <&cpudai>; 66 simple-audio-card,widgets = 67 "Line", "Left Line Out Jack", 68 "Line", "Right Line Out Jack"; 69 simple-audio-card,routing = 70 "Left Line Out Jack", "LINEVOUTL", 71 "Right Line Out Jack", "LINEVOUTR"; 72 73 cpudai: simple-audio-card,cpu { 74 sound-dai = <&sai3>; 75 dai-tdm-slot-num = <2>; 76 dai-tdm-slot-width = <32>; 77 }; 78 79 simple-audio-card,codec { 80 sound-dai = <&wm8524>; 81 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; 82 }; 83 }; 84}; 85 86&A53_0 { 87 cpu-supply = <&buck2_reg>; 88}; 89 90&A53_1 { 91 cpu-supply = <&buck2_reg>; 92}; 93 94&A53_2 { 95 cpu-supply = <&buck2_reg>; 96}; 97 98&A53_3 { 99 cpu-supply = <&buck2_reg>; 100}; 101 102&fec1 { 103 pinctrl-names = "default"; 104 pinctrl-0 = <&pinctrl_fec1>; 105 phy-mode = "rgmii-id"; 106 phy-handle = <ðphy0>; 107 fsl,magic-packet; 108 status = "okay"; 109 110 mdio { 111 #address-cells = <1>; 112 #size-cells = <0>; 113 114 ethphy0: ethernet-phy@0 { 115 compatible = "ethernet-phy-ieee802.3-c22"; 116 reg = <0>; 117 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 118 reset-assert-us = <10000>; 119 }; 120 }; 121}; 122 123&i2c1 { 124 clock-frequency = <400000>; 125 pinctrl-names = "default"; 126 pinctrl-0 = <&pinctrl_i2c1>; 127 status = "okay"; 128 129 pmic@4b { 130 compatible = "rohm,bd71847"; 131 reg = <0x4b>; 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_pmic>; 134 interrupt-parent = <&gpio1>; 135 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 136 rohm,reset-snvs-powered; 137 138 #clock-cells = <0>; 139 clocks = <&osc_32k 0>; 140 clock-output-names = "clk-32k-out"; 141 142 regulators { 143 buck1_reg: BUCK1 { 144 regulator-name = "buck1"; 145 regulator-min-microvolt = <700000>; 146 regulator-max-microvolt = <1300000>; 147 regulator-boot-on; 148 regulator-always-on; 149 regulator-ramp-delay = <1250>; 150 }; 151 152 buck2_reg: BUCK2 { 153 regulator-name = "buck2"; 154 regulator-min-microvolt = <700000>; 155 regulator-max-microvolt = <1300000>; 156 regulator-boot-on; 157 regulator-always-on; 158 regulator-ramp-delay = <1250>; 159 rohm,dvs-run-voltage = <1000000>; 160 rohm,dvs-idle-voltage = <900000>; 161 }; 162 163 buck3_reg: BUCK3 { 164 // BUCK5 in datasheet 165 regulator-name = "buck3"; 166 regulator-min-microvolt = <700000>; 167 regulator-max-microvolt = <1350000>; 168 regulator-boot-on; 169 regulator-always-on; 170 }; 171 172 buck4_reg: BUCK4 { 173 // BUCK6 in datasheet 174 regulator-name = "buck4"; 175 regulator-min-microvolt = <3000000>; 176 regulator-max-microvolt = <3300000>; 177 regulator-boot-on; 178 regulator-always-on; 179 }; 180 181 buck5_reg: BUCK5 { 182 // BUCK7 in datasheet 183 regulator-name = "buck5"; 184 regulator-min-microvolt = <1605000>; 185 regulator-max-microvolt = <1995000>; 186 regulator-boot-on; 187 regulator-always-on; 188 }; 189 190 buck6_reg: BUCK6 { 191 // BUCK8 in datasheet 192 regulator-name = "buck6"; 193 regulator-min-microvolt = <800000>; 194 regulator-max-microvolt = <1400000>; 195 regulator-boot-on; 196 regulator-always-on; 197 }; 198 199 ldo1_reg: LDO1 { 200 regulator-name = "ldo1"; 201 regulator-min-microvolt = <1600000>; 202 regulator-max-microvolt = <3300000>; 203 regulator-boot-on; 204 regulator-always-on; 205 }; 206 207 ldo2_reg: LDO2 { 208 regulator-name = "ldo2"; 209 regulator-min-microvolt = <800000>; 210 regulator-max-microvolt = <900000>; 211 regulator-boot-on; 212 regulator-always-on; 213 }; 214 215 ldo3_reg: LDO3 { 216 regulator-name = "ldo3"; 217 regulator-min-microvolt = <1800000>; 218 regulator-max-microvolt = <3300000>; 219 regulator-boot-on; 220 regulator-always-on; 221 }; 222 223 ldo4_reg: LDO4 { 224 regulator-name = "ldo4"; 225 regulator-min-microvolt = <900000>; 226 regulator-max-microvolt = <1800000>; 227 regulator-boot-on; 228 regulator-always-on; 229 }; 230 231 ldo6_reg: LDO6 { 232 regulator-name = "ldo6"; 233 regulator-min-microvolt = <900000>; 234 regulator-max-microvolt = <1800000>; 235 regulator-boot-on; 236 regulator-always-on; 237 }; 238 }; 239 }; 240}; 241 242&i2c2 { 243 clock-frequency = <400000>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_i2c2>; 246 status = "okay"; 247 248 ptn5110: tcpc@50 { 249 compatible = "nxp,ptn5110"; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&pinctrl_typec1>; 252 reg = <0x50>; 253 interrupt-parent = <&gpio2>; 254 interrupts = <11 8>; 255 status = "okay"; 256 257 port { 258 typec1_dr_sw: endpoint { 259 remote-endpoint = <&usb1_drd_sw>; 260 }; 261 }; 262 263 typec1_con: connector { 264 compatible = "usb-c-connector"; 265 label = "USB-C"; 266 power-role = "dual"; 267 data-role = "dual"; 268 try-power-role = "sink"; 269 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 270 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 271 PDO_VAR(5000, 20000, 3000)>; 272 op-sink-microwatt = <15000000>; 273 self-powered; 274 }; 275 }; 276}; 277 278&i2c3 { 279 clock-frequency = <400000>; 280 pinctrl-names = "default"; 281 pinctrl-0 = <&pinctrl_i2c3>; 282 status = "okay"; 283 284 pca6416: gpio@20 { 285 compatible = "ti,tca6416"; 286 reg = <0x20>; 287 gpio-controller; 288 #gpio-cells = <2>; 289 }; 290}; 291 292&sai3 { 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_sai3>; 295 assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 296 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 297 assigned-clock-rates = <24576000>; 298 status = "okay"; 299}; 300 301&snvs_pwrkey { 302 status = "okay"; 303}; 304 305&uart2 { /* console */ 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pinctrl_uart2>; 308 status = "okay"; 309}; 310 311&usbotg1 { 312 dr_mode = "otg"; 313 hnp-disable; 314 srp-disable; 315 adp-disable; 316 usb-role-switch; 317 samsung,picophy-pre-emp-curr-control = <3>; 318 samsung,picophy-dc-vol-level-adjust = <7>; 319 status = "okay"; 320 321 port { 322 usb1_drd_sw: endpoint { 323 remote-endpoint = <&typec1_dr_sw>; 324 }; 325 }; 326}; 327 328&usdhc2 { 329 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 330 assigned-clock-rates = <200000000>; 331 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 332 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 333 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 334 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 335 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 336 bus-width = <4>; 337 vmmc-supply = <®_usdhc2_vmmc>; 338 status = "okay"; 339}; 340 341&wdog1 { 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_wdog>; 344 fsl,ext-reset-output; 345 status = "okay"; 346}; 347 348&iomuxc { 349 pinctrl_fec1: fec1grp { 350 fsl,pins = < 351 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 352 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 353 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 354 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 355 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 356 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 357 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 358 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 359 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 360 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 361 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 362 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 363 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 364 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 365 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 366 >; 367 }; 368 369 pinctrl_gpio_led: gpioledgrp { 370 fsl,pins = < 371 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 372 >; 373 }; 374 375 pinctrl_ir: irgrp { 376 fsl,pins = < 377 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f 378 >; 379 }; 380 381 pinctrl_gpio_wlf: gpiowlfgrp { 382 fsl,pins = < 383 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 384 >; 385 }; 386 387 pinctrl_i2c1: i2c1grp { 388 fsl,pins = < 389 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 390 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 391 >; 392 }; 393 394 pinctrl_i2c2: i2c2grp { 395 fsl,pins = < 396 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 397 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 398 >; 399 }; 400 401 pinctrl_i2c3: i2c3grp { 402 fsl,pins = < 403 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 404 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 405 >; 406 }; 407 408 pinctrl_pmic: pmicirqgrp { 409 fsl,pins = < 410 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 411 >; 412 }; 413 414 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 415 fsl,pins = < 416 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 417 >; 418 }; 419 420 pinctrl_sai3: sai3grp { 421 fsl,pins = < 422 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 423 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 424 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 425 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 426 >; 427 }; 428 429 pinctrl_typec1: typec1grp { 430 fsl,pins = < 431 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 432 >; 433 }; 434 435 pinctrl_uart2: uart2grp { 436 fsl,pins = < 437 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 438 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 439 >; 440 }; 441 442 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { 443 fsl,pins = < 444 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 445 >; 446 }; 447 448 pinctrl_usdhc2: usdhc2grp { 449 fsl,pins = < 450 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 451 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 452 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 453 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 454 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 455 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 456 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 457 >; 458 }; 459 460 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 461 fsl,pins = < 462 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 463 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 464 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 465 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 466 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 467 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 468 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 469 >; 470 }; 471 472 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 473 fsl,pins = < 474 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 475 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 476 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 477 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 478 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 479 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 480 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 481 >; 482 }; 483 484 pinctrl_wdog: wdoggrp { 485 fsl,pins = < 486 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 487 >; 488 }; 489}; 490