1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019-2020 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx8mm-evk.dtsi" 10 11/ { 12 model = "FSL i.MX8MM EVK board"; 13 compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; 14 15 aliases { 16 spi0 = &flexspi; 17 }; 18}; 19 20&ddrc { 21 operating-points-v2 = <&ddrc_opp_table>; 22 23 ddrc_opp_table: opp-table { 24 compatible = "operating-points-v2"; 25 26 opp-25000000 { 27 opp-hz = /bits/ 64 <25000000>; 28 }; 29 30 opp-100000000 { 31 opp-hz = /bits/ 64 <100000000>; 32 }; 33 34 opp-750000000 { 35 opp-hz = /bits/ 64 <750000000>; 36 }; 37 }; 38}; 39 40&flexspi { 41 pinctrl-names = "default"; 42 pinctrl-0 = <&pinctrl_flexspi>; 43 status = "okay"; 44 45 flash@0 { 46 reg = <0>; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 compatible = "jedec,spi-nor"; 50 spi-max-frequency = <80000000>; 51 spi-tx-bus-width = <1>; 52 spi-rx-bus-width = <4>; 53 }; 54}; 55 56&usdhc3 { 57 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 58 assigned-clock-rates = <400000000>; 59 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 60 pinctrl-0 = <&pinctrl_usdhc3>; 61 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 62 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 63 bus-width = <8>; 64 non-removable; 65 status = "okay"; 66}; 67 68&iomuxc { 69 pinctrl_flexspi: flexspigrp { 70 fsl,pins = < 71 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 72 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 73 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 74 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 75 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 76 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 77 >; 78 }; 79 80 pinctrl_usdhc3: usdhc3grp { 81 fsl,pins = < 82 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 83 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 84 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 85 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 86 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 87 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 88 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 89 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 90 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 91 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 92 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 93 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 94 >; 95 }; 96 97 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 98 fsl,pins = < 99 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 100 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 101 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 102 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 103 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 104 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 105 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 106 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 107 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 108 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 109 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 110 >; 111 }; 112 113 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 114 fsl,pins = < 115 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 116 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 117 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 118 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 119 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 120 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 121 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 122 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 123 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 124 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 125 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 126 >; 127 }; 128}; 129