1// SPDX-License-Identifier: (GPL-2.0 or MIT) 2// 3// Copyright 2018 NXP 4// Copyright (C) 2021 emtrion GmbH 5// 6 7/dts-v1/; 8 9#include "imx8mm.dtsi" 10 11/ { 12 chosen { 13 stdout-path = &uart1; 14 }; 15 16 som_leds: leds { 17 compatible = "gpio-leds"; 18 pinctrl-names = "default"; 19 pinctrl-0 = <&pinctrl_gpio_led>; 20 21 green { 22 label = "som:green"; 23 gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; 24 default-state = "on"; 25 linux,default-trigger = "heartbeat"; 26 }; 27 28 red { 29 label = "som:red"; 30 gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; 31 default-state = "off"; 32 }; 33 }; 34 35 lvds_backlight: lvds-backlight { 36 compatible = "pwm-backlight"; 37 enable-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; 38 pwms = <&pwm1 0 50000 0>; 39 brightness-levels = < 40 0 4 8 16 32 64 80 96 112 41 128 144 160 176 250 42 >; 43 default-brightness-level = <9>; 44 status = "disabled"; 45 }; 46 47 reg_usdhc1_vmmc: regulator-emmc { 48 compatible = "regulator-fixed"; 49 regulator-name = "eMMC"; 50 regulator-min-microvolt = <3300000>; 51 regulator-max-microvolt = <3300000>; 52 }; 53 54 reg_usdhc2_vmmc: regulator-usdhc2 { 55 compatible = "regulator-fixed"; 56 regulator-name = "sdcard_3V3"; 57 regulator-min-microvolt = <3300000>; 58 regulator-max-microvolt = <3300000>; 59 }; 60}; 61 62&A53_0 { 63 cpu-supply = <&buck2_reg>; 64}; 65 66&ecspi1 { 67 pinctrl-names = "default"; 68 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 69 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, 70 <&gpio5 13 GPIO_ACTIVE_LOW>; 71 status = "okay"; 72}; 73 74&fec1 { 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_fec1>; 77 phy-mode = "rgmii-id"; 78 phy-handle = <ðphy0>; 79 fsl,magic-packet; 80 status = "okay"; 81 82 mdio { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 ethphy0: ethernet-phy@0 { 87 compatible = "ethernet-phy-ieee802.3-c22"; 88 reg = <0>; 89 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 90 reset-assert-us = <10000>; 91 }; 92 }; 93}; 94 95&flexspi { 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_flexspi0>; 98 pinctrl-1 = <&pinctrl_flexspi1>; 99 status = "okay"; 100 101 flash0: spi-flash@0 { 102 reg = <0>; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 compatible = "jedec,spi-nor"; 106 spi-max-frequency = <40000000>; 107 }; 108}; 109 110&iomuxc { 111 pinctrl-names = "default"; 112 113 pinctrl_csi_pwn: csi-pwn-grp { 114 fsl,pins = < 115 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 116 >; 117 }; 118 119 pinctrl_ecspi1: ecspi1-grp { 120 fsl,pins = < 121 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 122 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 123 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 124 >; 125 }; 126 127 pinctrl_ecspi1_cs: ecspi1-cs { 128 fsl,pins = < 129 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000 130 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 131 >; 132 }; 133 134 pinctrl_fec1: fec1-grp { 135 fsl,pins = < 136 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 137 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 138 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 139 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 140 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 141 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 142 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 143 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 144 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 145 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 146 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 147 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 148 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 149 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 150 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 151 >; 152 }; 153 154 pinctrl_flexspi0: flexspi0-grp { 155 fsl,pins = < 156 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 157 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 158 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 159 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 160 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 161 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 162 MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 163 >; 164 }; 165 166 pinctrl_flexspi1: flexspi1-grp { 167 fsl,pins = < 168 MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x1c2 169 MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82 170 MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82 171 MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82 172 MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82 173 MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82 174 >; 175 }; 176 177 pinctrl_gpio_led: gpio-led-grp { 178 fsl,pins = < 179 MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 180 MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 181 >; 182 }; 183 184 pinctrl_i2c1: i2c1-grp { 185 fsl,pins = < 186 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 187 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 188 >; 189 }; 190 191 pinctrl_i2c2: i2c2grp { 192 fsl,pins = < 193 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 194 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 195 >; 196 }; 197 198 pinctrl_i2c3: i2c3-grp { 199 fsl,pins = < 200 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 201 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 202 >; 203 }; 204 205 pinctrl_lvds: lvds-grp { 206 fsl,pins = < 207 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x06 208 >; 209 }; 210 211 pinctrl_pcie0: pcie0-grp { 212 fsl,pins = < 213 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 214 MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x41 215 >; 216 }; 217 218 pinctrl_pmic: pmic-irq { 219 fsl,pins = < 220 MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x41 221 >; 222 }; 223 224 pinctrl_pwm1: pwm1-grp { 225 fsl,pins = < 226 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 227 >; 228 }; 229 230 pinctrl_sai2: sai2-grp { 231 fsl,pins = < 232 MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 233 MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 234 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 235 MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 236 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 237 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 238 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 239 >; 240 }; 241 242 pinctrl_spdif1: spdif1-grp { 243 fsl,pins = < 244 MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 245 MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 246 >; 247 }; 248 249 pinctrl_uart1: uart1-grp { 250 fsl,pins = < 251 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 252 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 253 >; 254 }; 255 256 pinctrl_uart2: uart2-grp { 257 fsl,pins = < 258 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 259 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 260 261 /* rts and cts */ 262 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 263 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 264 >; 265 }; 266 267 pinctrl_uart3: uart3-grp { 268 fsl,pins = < 269 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 270 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 271 >; 272 }; 273 274 pinctrl_uart4: uart4-grp { 275 fsl,pins = < 276 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 277 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 278 >; 279 }; 280 281 pinctrl_usdhc1: usdhc1-grp { 282 fsl,pins = < 283 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 284 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 285 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 286 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 287 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 288 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 289 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 290 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 291 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 292 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 293 >; 294 }; 295 296 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { 297 fsl,pins = < 298 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 299 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 300 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 301 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 302 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 303 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 304 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 305 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 306 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 307 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 308 >; 309 }; 310 311 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { 312 fsl,pins = < 313 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 314 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 315 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 316 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 317 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 318 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 319 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 320 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 321 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 322 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 323 >; 324 }; 325 326 pinctrl_usdhc1_gpio: usdhc1-gpio-grp { 327 fsl,pins = < 328 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x41 329 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c4 330 >; 331 }; 332 333 pinctrl_usdhc2: usdhc2-grp { 334 fsl,pins = < 335 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 336 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 337 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 338 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 339 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 340 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 341 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 342 >; 343 }; 344 345 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { 346 fsl,pins = < 347 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 348 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 349 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 350 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 351 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 352 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 353 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 354 >; 355 }; 356 357 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { 358 fsl,pins = < 359 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 360 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 361 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 362 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 363 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 364 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 365 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 366 >; 367 }; 368 369 /* no reset for sdhc2 interface */ 370 pinctrl_usdhc2_gpio: usdhc2-gpio-grp { 371 fsl,pins = < 372 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 373 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x1c4 374 >; 375 }; 376 377 pinctrl_wdog: wdog-grp { 378 fsl,pins = < 379 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 380 >; 381 }; 382}; 383 384&i2c1 { 385 clock-frequency = <400000>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_i2c1>; 388 status = "okay"; 389}; 390 391&i2c2 { 392 clock-frequency = <400000>; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&pinctrl_i2c2>; 395 status = "okay"; 396}; 397 398&i2c3 { 399 clock-frequency = <400000>; 400 pinctrl-names = "default"; 401 pinctrl-0 = <&pinctrl_i2c3>; 402 status = "okay"; 403 404 bd71847: pmic@4b { 405 compatible = "rohm,bd71847"; 406 reg = <0x4b>; 407 pinctrl-0 = <&pinctrl_pmic>; 408 interrupt-parent = <&gpio3>; 409 interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 410 rohm,reset-snvs-powered; 411 412 regulators { 413 buck1_reg: BUCK1 { 414 regulator-name = "BUCK1"; 415 regulator-min-microvolt = <700000>; 416 regulator-max-microvolt = <1300000>; 417 regulator-boot-on; 418 regulator-always-on; 419 regulator-ramp-delay = <1250>; 420 }; 421 422 buck2_reg: BUCK2 { 423 regulator-name = "BUCK2"; 424 regulator-min-microvolt = <700000>; 425 regulator-max-microvolt = <1300000>; 426 regulator-boot-on; 427 regulator-always-on; 428 regulator-ramp-delay = <1250>; 429 rohm,dvs-run-voltage = <1000000>; 430 rohm,dvs-idle-voltage = <900000>; 431 }; 432 433 buck3_reg: BUCK3 { 434 // BUCK5 in datasheet 435 regulator-name = "BUCK3"; 436 regulator-min-microvolt = <700000>; 437 regulator-max-microvolt = <1350000>; 438 regulator-boot-on; 439 regulator-always-on; 440 }; 441 442 buck4_reg: BUCK4 { 443 // BUCK6 in datasheet 444 regulator-name = "BUCK4"; 445 regulator-min-microvolt = <3000000>; 446 regulator-max-microvolt = <3300000>; 447 regulator-boot-on; 448 regulator-always-on; 449 }; 450 451 buck5_reg: BUCK5 { 452 // BUCK7 in datasheet 453 regulator-name = "BUCK5"; 454 regulator-min-microvolt = <1605000>; 455 regulator-max-microvolt = <1995000>; 456 regulator-boot-on; 457 regulator-always-on; 458 }; 459 460 buck6_reg: BUCK6 { 461 // BUCK8 in datasheet 462 regulator-name = "BUCK6"; 463 regulator-min-microvolt = <800000>; 464 regulator-max-microvolt = <1400000>; 465 regulator-boot-on; 466 regulator-always-on; 467 }; 468 469 ldo1_reg: LDO1 { 470 regulator-name = "LDO1"; 471 regulator-min-microvolt = <1600000>; 472 regulator-max-microvolt = <1900000>; 473 regulator-boot-on; 474 regulator-always-on; 475 }; 476 477 ldo2_reg: LDO2 { 478 regulator-name = "LDO2"; 479 regulator-min-microvolt = <800000>; 480 regulator-max-microvolt = <900000>; 481 regulator-boot-on; 482 regulator-always-on; 483 }; 484 485 ldo3_reg: LDO3 { 486 regulator-name = "LDO3"; 487 regulator-min-microvolt = <1800000>; 488 regulator-max-microvolt = <3300000>; 489 regulator-boot-on; 490 regulator-always-on; 491 }; 492 493 ldo4_reg: LDO4 { 494 regulator-name = "LDO4"; 495 regulator-min-microvolt = <900000>; 496 regulator-max-microvolt = <1800000>; 497 regulator-boot-on; 498 regulator-always-on; 499 }; 500 501 ldo6_reg: LDO6 { 502 regulator-name = "LDO6"; 503 regulator-min-microvolt = <900000>; 504 regulator-max-microvolt = <1800000>; 505 regulator-boot-on; 506 regulator-always-on; 507 }; 508 }; 509 }; 510 511 rv1805: rtc@69 { 512 compatible = "abracon,ab1805"; 513 reg = <0x69>; 514 }; 515}; 516 517&mu { 518 status = "okay"; 519}; 520 521&pwm1 { 522 pinctrl-names = "default"; 523 pinctrl-0 = <&pinctrl_pwm1>; 524}; 525 526&sai2 { 527 #sound-dai-cells = <0>; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&pinctrl_sai2>; 530 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 531 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 532 assigned-clock-rates = <12000000>; 533 status = "disabled"; 534}; 535 536&spdif1 { 537 pinctrl-names = "default"; 538 pinctrl-0 = <&pinctrl_spdif1>; 539 assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; 540 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 541 assigned-clock-rates = <24576000>; 542 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, 543 <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, 544 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, 545 <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, 546 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, 547 <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; 548 clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", 549 "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; 550 status = "disabled"; 551}; 552 553&uart1 { /* console */ 554 pinctrl-names = "default"; 555 pinctrl-0 = <&pinctrl_uart1>; 556 assigned-clocks = <&clk IMX8MM_CLK_UART1>; 557 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 558 status = "okay"; 559}; 560 561&uart2 { 562 pinctrl-names = "default"; 563 pinctrl-0 = <&pinctrl_uart2>; 564 assigned-clocks = <&clk IMX8MM_CLK_UART2>; 565 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 566 status = "okay"; 567}; 568 569&uart3 { 570 pinctrl-names = "default"; 571 pinctrl-0 = <&pinctrl_uart3>; 572 assigned-clocks = <&clk IMX8MM_CLK_UART3>; 573 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 574 status = "okay"; 575}; 576 577&uart4 { 578 pinctrl-names = "default"; 579 pinctrl-0 = <&pinctrl_uart4>; 580 assigned-clocks = <&clk IMX8MM_CLK_UART4>; 581 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 582 status = "okay"; 583}; 584 585&usbotg1 { 586 dr_mode = "otg"; 587 over-current-active-low; 588 status = "okay"; 589}; 590 591&usbotg2 { 592 dr_mode = "host"; 593 disable-over-current; 594 status = "disabled"; 595}; 596 597&usdhc1 { 598 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 599 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; 600 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; 601 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; 602 bus-width = <8>; 603 vmmc-supply = <®_usdhc1_vmmc>; 604 keep-power-in-suspend; 605 non-removable; 606 status = "okay"; 607}; 608 609&usdhc2 { 610 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 611 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 612 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 613 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 614 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 615 wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 616 bus-width = <4>; 617 vmmc-supply = <®_usdhc2_vmmc>; 618 no-1-8-v; 619 status = "okay"; 620}; 621 622&wdog1 { 623 pinctrl-names = "default"; 624 pinctrl-0 = <&pinctrl_wdog>; 625 fsl,ext-reset-output; 626 status = "okay"; 627}; 628