1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2020 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9 10lsio_subsys: bus@5d000000 { 11 compatible = "simple-bus"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>, 15 <0x08000000 0x0 0x08000000 0x10000000>; 16 17 lsio_mem_clk: clock-lsio-mem { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 clock-frequency = <200000000>; 21 clock-output-names = "lsio_mem_clk"; 22 }; 23 24 lsio_bus_clk: clock-lsio-bus { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <100000000>; 28 clock-output-names = "lsio_bus_clk"; 29 }; 30 31 lsio_gpio0: gpio@5d080000 { 32 reg = <0x5d080000 0x10000>; 33 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 34 gpio-controller; 35 #gpio-cells = <2>; 36 interrupt-controller; 37 #interrupt-cells = <2>; 38 power-domains = <&pd IMX_SC_R_GPIO_0>; 39 }; 40 41 lsio_gpio1: gpio@5d090000 { 42 reg = <0x5d090000 0x10000>; 43 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 44 gpio-controller; 45 #gpio-cells = <2>; 46 interrupt-controller; 47 #interrupt-cells = <2>; 48 power-domains = <&pd IMX_SC_R_GPIO_1>; 49 }; 50 51 lsio_gpio2: gpio@5d0a0000 { 52 reg = <0x5d0a0000 0x10000>; 53 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 54 gpio-controller; 55 #gpio-cells = <2>; 56 interrupt-controller; 57 #interrupt-cells = <2>; 58 power-domains = <&pd IMX_SC_R_GPIO_2>; 59 }; 60 61 lsio_gpio3: gpio@5d0b0000 { 62 reg = <0x5d0b0000 0x10000>; 63 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 64 gpio-controller; 65 #gpio-cells = <2>; 66 interrupt-controller; 67 #interrupt-cells = <2>; 68 power-domains = <&pd IMX_SC_R_GPIO_3>; 69 }; 70 71 lsio_gpio4: gpio@5d0c0000 { 72 reg = <0x5d0c0000 0x10000>; 73 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 74 gpio-controller; 75 #gpio-cells = <2>; 76 interrupt-controller; 77 #interrupt-cells = <2>; 78 power-domains = <&pd IMX_SC_R_GPIO_4>; 79 }; 80 81 lsio_gpio5: gpio@5d0d0000 { 82 reg = <0x5d0d0000 0x10000>; 83 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 84 gpio-controller; 85 #gpio-cells = <2>; 86 interrupt-controller; 87 #interrupt-cells = <2>; 88 power-domains = <&pd IMX_SC_R_GPIO_5>; 89 }; 90 91 lsio_gpio6: gpio@5d0e0000 { 92 reg = <0x5d0e0000 0x10000>; 93 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 94 gpio-controller; 95 #gpio-cells = <2>; 96 interrupt-controller; 97 #interrupt-cells = <2>; 98 power-domains = <&pd IMX_SC_R_GPIO_6>; 99 }; 100 101 lsio_gpio7: gpio@5d0f0000 { 102 reg = <0x5d0f0000 0x10000>; 103 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 104 gpio-controller; 105 #gpio-cells = <2>; 106 interrupt-controller; 107 #interrupt-cells = <2>; 108 power-domains = <&pd IMX_SC_R_GPIO_7>; 109 }; 110 111 flexspi0: spi@5d120000 { 112 #address-cells = <1>; 113 #size-cells = <0>; 114 compatible = "nxp,imx8qxp-fspi"; 115 reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>; 116 reg-names = "fspi_base", "fspi_mmap"; 117 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>, 119 <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>; 120 clock-names = "fspi_en", "fspi"; 121 power-domains = <&pd IMX_SC_R_FSPI_0>; 122 status = "disabled"; 123 }; 124 125 lsio_mu0: mailbox@5d1b0000 { 126 reg = <0x5d1b0000 0x10000>; 127 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 128 #mbox-cells = <2>; 129 status = "disabled"; 130 }; 131 132 lsio_mu1: mailbox@5d1c0000 { 133 reg = <0x5d1c0000 0x10000>; 134 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 135 #mbox-cells = <2>; 136 }; 137 138 lsio_mu2: mailbox@5d1d0000 { 139 reg = <0x5d1d0000 0x10000>; 140 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 141 #mbox-cells = <2>; 142 status = "disabled"; 143 }; 144 145 lsio_mu3: mailbox@5d1e0000 { 146 reg = <0x5d1e0000 0x10000>; 147 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 148 #mbox-cells = <2>; 149 status = "disabled"; 150 }; 151 152 lsio_mu4: mailbox@5d1f0000 { 153 reg = <0x5d1f0000 0x10000>; 154 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 155 #mbox-cells = <2>; 156 status = "disabled"; 157 }; 158 159 lsio_mu5: mailbox@5d200000 { 160 reg = <0x5d200000 0x10000>; 161 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 162 #mbox-cells = <2>; 163 power-domains = <&pd IMX_SC_R_MU_5A>; 164 status = "disabled"; 165 }; 166 167 lsio_mu6: mailbox@5d210000 { 168 reg = <0x5d210000 0x10000>; 169 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 170 #mbox-cells = <2>; 171 power-domains = <&pd IMX_SC_R_MU_6A>; 172 status = "disabled"; 173 }; 174 175 lsio_mu13: mailbox@5d280000 { 176 reg = <0x5d280000 0x10000>; 177 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 178 #mbox-cells = <2>; 179 power-domains = <&pd IMX_SC_R_MU_13A>; 180 }; 181 182 /* LPCG clocks */ 183 pwm0_lpcg: clock-controller@5d400000 { 184 compatible = "fsl,imx8qxp-lpcg"; 185 reg = <0x5d400000 0x10000>; 186 #clock-cells = <1>; 187 clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, 188 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, 189 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, 190 <&lsio_bus_clk>, 191 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; 192 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 193 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 194 <IMX_LPCG_CLK_6>; 195 clock-output-names = "pwm0_lpcg_ipg_clk", 196 "pwm0_lpcg_ipg_hf_clk", 197 "pwm0_lpcg_ipg_s_clk", 198 "pwm0_lpcg_ipg_slv_clk", 199 "pwm0_lpcg_ipg_mstr_clk"; 200 power-domains = <&pd IMX_SC_R_PWM_0>; 201 }; 202 203 pwm1_lpcg: clock-controller@5d410000 { 204 compatible = "fsl,imx8qxp-lpcg"; 205 reg = <0x5d410000 0x10000>; 206 #clock-cells = <1>; 207 clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, 208 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, 209 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, 210 <&lsio_bus_clk>, 211 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; 212 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 213 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 214 <IMX_LPCG_CLK_6>; 215 clock-output-names = "pwm1_lpcg_ipg_clk", 216 "pwm1_lpcg_ipg_hf_clk", 217 "pwm1_lpcg_ipg_s_clk", 218 "pwm1_lpcg_ipg_slv_clk", 219 "pwm1_lpcg_ipg_mstr_clk"; 220 power-domains = <&pd IMX_SC_R_PWM_1>; 221 }; 222 223 pwm2_lpcg: clock-controller@5d420000 { 224 compatible = "fsl,imx8qxp-lpcg"; 225 reg = <0x5d420000 0x10000>; 226 #clock-cells = <1>; 227 clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, 228 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, 229 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, 230 <&lsio_bus_clk>, 231 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; 232 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 233 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 234 <IMX_LPCG_CLK_6>; 235 clock-output-names = "pwm2_lpcg_ipg_clk", 236 "pwm2_lpcg_ipg_hf_clk", 237 "pwm2_lpcg_ipg_s_clk", 238 "pwm2_lpcg_ipg_slv_clk", 239 "pwm2_lpcg_ipg_mstr_clk"; 240 power-domains = <&pd IMX_SC_R_PWM_2>; 241 }; 242 243 pwm3_lpcg: clock-controller@5d430000 { 244 compatible = "fsl,imx8qxp-lpcg"; 245 reg = <0x5d430000 0x10000>; 246 #clock-cells = <1>; 247 clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, 248 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, 249 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, 250 <&lsio_bus_clk>, 251 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; 252 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 253 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 254 <IMX_LPCG_CLK_6>; 255 clock-output-names = "pwm3_lpcg_ipg_clk", 256 "pwm3_lpcg_ipg_hf_clk", 257 "pwm3_lpcg_ipg_s_clk", 258 "pwm3_lpcg_ipg_slv_clk", 259 "pwm3_lpcg_ipg_mstr_clk"; 260 power-domains = <&pd IMX_SC_R_PWM_3>; 261 }; 262 263 pwm4_lpcg: clock-controller@5d440000 { 264 compatible = "fsl,imx8qxp-lpcg"; 265 reg = <0x5d440000 0x10000>; 266 #clock-cells = <1>; 267 clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, 268 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, 269 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, 270 <&lsio_bus_clk>, 271 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>; 272 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 273 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 274 <IMX_LPCG_CLK_6>; 275 clock-output-names = "pwm4_lpcg_ipg_clk", 276 "pwm4_lpcg_ipg_hf_clk", 277 "pwm4_lpcg_ipg_s_clk", 278 "pwm4_lpcg_ipg_slv_clk", 279 "pwm4_lpcg_ipg_mstr_clk"; 280 power-domains = <&pd IMX_SC_R_PWM_4>; 281 }; 282 283 pwm5_lpcg: clock-controller@5d450000 { 284 compatible = "fsl,imx8qxp-lpcg"; 285 reg = <0x5d450000 0x10000>; 286 #clock-cells = <1>; 287 clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, 288 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, 289 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, 290 <&lsio_bus_clk>, 291 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>; 292 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 293 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 294 <IMX_LPCG_CLK_6>; 295 clock-output-names = "pwm5_lpcg_ipg_clk", 296 "pwm5_lpcg_ipg_hf_clk", 297 "pwm5_lpcg_ipg_s_clk", 298 "pwm5_lpcg_ipg_slv_clk", 299 "pwm5_lpcg_ipg_mstr_clk"; 300 power-domains = <&pd IMX_SC_R_PWM_5>; 301 }; 302 303 pwm6_lpcg: clock-controller@5d460000 { 304 compatible = "fsl,imx8qxp-lpcg"; 305 reg = <0x5d460000 0x10000>; 306 #clock-cells = <1>; 307 clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, 308 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, 309 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, 310 <&lsio_bus_clk>, 311 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>; 312 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 313 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 314 <IMX_LPCG_CLK_6>; 315 clock-output-names = "pwm6_lpcg_ipg_clk", 316 "pwm6_lpcg_ipg_hf_clk", 317 "pwm6_lpcg_ipg_s_clk", 318 "pwm6_lpcg_ipg_slv_clk", 319 "pwm6_lpcg_ipg_mstr_clk"; 320 power-domains = <&pd IMX_SC_R_PWM_6>; 321 }; 322 323 pwm7_lpcg: clock-controller@5d470000 { 324 compatible = "fsl,imx8qxp-lpcg"; 325 reg = <0x5d470000 0x10000>; 326 #clock-cells = <1>; 327 clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, 328 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, 329 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, 330 <&lsio_bus_clk>, 331 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>; 332 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 333 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 334 <IMX_LPCG_CLK_6>; 335 clock-output-names = "pwm7_lpcg_ipg_clk", 336 "pwm7_lpcg_ipg_hf_clk", 337 "pwm7_lpcg_ipg_s_clk", 338 "pwm7_lpcg_ipg_slv_clk", 339 "pwm7_lpcg_ipg_mstr_clk"; 340 power-domains = <&pd IMX_SC_R_PWM_7>; 341 }; 342}; 343