1*01950c46SEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0+ 2*01950c46SEmmanuel Vadot/* 3*01950c46SEmmanuel Vadot * Copyright 2019 NXP 4*01950c46SEmmanuel Vadot * Dong Aisheng <aisheng.dong@nxp.com> 5*01950c46SEmmanuel Vadot */ 6*01950c46SEmmanuel Vadot 7*01950c46SEmmanuel Vadot#include <dt-bindings/firmware/imx/rsrc.h> 8*01950c46SEmmanuel Vadot 9*01950c46SEmmanuel Vadotgpu0_subsys: bus@53000000 { 10*01950c46SEmmanuel Vadot compatible = "simple-bus"; 11*01950c46SEmmanuel Vadot #address-cells = <1>; 12*01950c46SEmmanuel Vadot #size-cells = <1>; 13*01950c46SEmmanuel Vadot ranges = <0x53000000 0x0 0x53000000 0x1000000>; 14*01950c46SEmmanuel Vadot 15*01950c46SEmmanuel Vadot gpu_3d0: gpu@53100000 { 16*01950c46SEmmanuel Vadot compatible = "vivante,gc"; 17*01950c46SEmmanuel Vadot reg = <0x53100000 0x40000>; 18*01950c46SEmmanuel Vadot interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 19*01950c46SEmmanuel Vadot clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, 20*01950c46SEmmanuel Vadot <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; 21*01950c46SEmmanuel Vadot clock-names = "core", "shader"; 22*01950c46SEmmanuel Vadot assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, 23*01950c46SEmmanuel Vadot <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; 24*01950c46SEmmanuel Vadot assigned-clock-rates = <700000000>, <850000000>; 25*01950c46SEmmanuel Vadot power-domains = <&pd IMX_SC_R_GPU_0_PID0>; 26*01950c46SEmmanuel Vadot }; 27*01950c46SEmmanuel Vadot}; 28