1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9 10audio_ipg_clk: clock-audio-ipg { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <120000000>; 14 clock-output-names = "audio_ipg_clk"; 15}; 16 17audio_subsys: bus@59000000 { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x59000000 0x0 0x59000000 0x1000000>; 22 23 edma0: dma-controller@591f0000 { 24 compatible = "fsl,imx8qm-edma"; 25 reg = <0x591f0000 0x190000>; 26 #dma-cells = <3>; 27 dma-channels = <24>; 28 dma-channel-mask = <0x5c0c00>; 29 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 0 */ 30 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, /* 1 */ 31 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, /* 2 */ 32 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, /* 3 */ 33 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, /* 4 */ 34 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, /* 5 */ 35 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 6 esai0 */ 36 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 7 */ 37 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* 8 spdif0 */ 38 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, /* 9 */ 39 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 10 unused */ 40 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 11 unused */ 41 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 12 sai0 */ 42 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 13 */ 43 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 14 sai1 */ 44 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 15 */ 45 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* 16 sai2 */ 46 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* 17 sai3 */ 47 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 18 unused */ 48 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 19 unused */ 49 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 20 unused */ 50 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, /* 21 */ 51 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 22 unused */ 52 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; /* 23 unused */ 53 power-domains = <&pd IMX_SC_R_DMA_0_CH0>, 54 <&pd IMX_SC_R_DMA_0_CH1>, 55 <&pd IMX_SC_R_DMA_0_CH2>, 56 <&pd IMX_SC_R_DMA_0_CH3>, 57 <&pd IMX_SC_R_DMA_0_CH4>, 58 <&pd IMX_SC_R_DMA_0_CH5>, 59 <&pd IMX_SC_R_DMA_0_CH6>, 60 <&pd IMX_SC_R_DMA_0_CH7>, 61 <&pd IMX_SC_R_DMA_0_CH8>, 62 <&pd IMX_SC_R_DMA_0_CH9>, 63 <&pd IMX_SC_R_DMA_0_CH10>, 64 <&pd IMX_SC_R_DMA_0_CH11>, 65 <&pd IMX_SC_R_DMA_0_CH12>, 66 <&pd IMX_SC_R_DMA_0_CH13>, 67 <&pd IMX_SC_R_DMA_0_CH14>, 68 <&pd IMX_SC_R_DMA_0_CH15>, 69 <&pd IMX_SC_R_DMA_0_CH16>, 70 <&pd IMX_SC_R_DMA_0_CH17>, 71 <&pd IMX_SC_R_DMA_0_CH18>, 72 <&pd IMX_SC_R_DMA_0_CH19>, 73 <&pd IMX_SC_R_DMA_0_CH20>, 74 <&pd IMX_SC_R_DMA_0_CH21>, 75 <&pd IMX_SC_R_DMA_0_CH22>, 76 <&pd IMX_SC_R_DMA_0_CH23>; 77 }; 78 79 dsp_lpcg: clock-controller@59580000 { 80 compatible = "fsl,imx8qxp-lpcg"; 81 reg = <0x59580000 0x10000>; 82 #clock-cells = <1>; 83 clocks = <&audio_ipg_clk>, 84 <&audio_ipg_clk>, 85 <&audio_ipg_clk>; 86 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 87 <IMX_LPCG_CLK_7>; 88 clock-output-names = "dsp_lpcg_adb_clk", 89 "dsp_lpcg_ipg_clk", 90 "dsp_lpcg_core_clk"; 91 power-domains = <&pd IMX_SC_R_DSP>; 92 }; 93 94 dsp_ram_lpcg: clock-controller@59590000 { 95 compatible = "fsl,imx8qxp-lpcg"; 96 reg = <0x59590000 0x10000>; 97 #clock-cells = <1>; 98 clocks = <&audio_ipg_clk>; 99 clock-indices = <IMX_LPCG_CLK_4>; 100 clock-output-names = "dsp_ram_lpcg_ipg_clk"; 101 power-domains = <&pd IMX_SC_R_DSP_RAM>; 102 }; 103 104 dsp: dsp@596e8000 { 105 compatible = "fsl,imx8qxp-dsp"; 106 reg = <0x596e8000 0x88000>; 107 clocks = <&dsp_lpcg IMX_LPCG_CLK_5>, 108 <&dsp_ram_lpcg IMX_LPCG_CLK_4>, 109 <&dsp_lpcg IMX_LPCG_CLK_7>; 110 clock-names = "ipg", "ocram", "core"; 111 power-domains = <&pd IMX_SC_R_MU_13A>, 112 <&pd IMX_SC_R_MU_13B>, 113 <&pd IMX_SC_R_DSP>, 114 <&pd IMX_SC_R_DSP_RAM>; 115 mbox-names = "txdb0", "txdb1", 116 "rxdb0", "rxdb1"; 117 mboxes = <&lsio_mu13 2 0>, 118 <&lsio_mu13 2 1>, 119 <&lsio_mu13 3 0>, 120 <&lsio_mu13 3 1>; 121 memory-region = <&dsp_reserved>; 122 status = "disabled"; 123 }; 124 125 edma1: dma-controller@599f0000 { 126 compatible = "fsl,imx8qm-edma"; 127 reg = <0x599f0000 0xc0000>; 128 #dma-cells = <3>; 129 dma-channels = <11>; 130 dma-channel-mask = <0xc0>; 131 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 1 */ 132 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, /* 1 */ 133 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, /* 2 */ 134 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, /* 3 */ 135 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, /* 4 */ 136 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, /* 5 */ 137 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 6 unused */ 138 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 7 unused */ 139 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ 140 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ 142 power-domains = <&pd IMX_SC_R_DMA_1_CH0>, 143 <&pd IMX_SC_R_DMA_1_CH1>, 144 <&pd IMX_SC_R_DMA_1_CH2>, 145 <&pd IMX_SC_R_DMA_1_CH3>, 146 <&pd IMX_SC_R_DMA_1_CH4>, 147 <&pd IMX_SC_R_DMA_1_CH5>, 148 <&pd IMX_SC_R_DMA_1_CH6>, 149 <&pd IMX_SC_R_DMA_1_CH7>, 150 <&pd IMX_SC_R_DMA_1_CH8>, 151 <&pd IMX_SC_R_DMA_1_CH9>, 152 <&pd IMX_SC_R_DMA_1_CH10>; 153 }; 154}; 155