1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree file for LX2160AQDS 4// 5// Copyright 2018 NXP 6 7/dts-v1/; 8 9#include "fsl-lx2160a.dtsi" 10 11/ { 12 model = "NXP Layerscape LX2160AQDS"; 13 compatible = "fsl,lx2160a-qds", "fsl,lx2160a"; 14 15 aliases { 16 crypto = &crypto; 17 mmc0 = &esdhc0; 18 mmc1 = &esdhc1; 19 serial0 = &uart0; 20 }; 21 22 chosen { 23 stdout-path = "serial0:115200n8"; 24 }; 25 26 sb_3v3: regulator-sb3v3 { 27 compatible = "regulator-fixed"; 28 regulator-name = "MC34717-3.3VSB"; 29 regulator-min-microvolt = <3300000>; 30 regulator-max-microvolt = <3300000>; 31 regulator-boot-on; 32 regulator-always-on; 33 }; 34 35 mdio-mux-1 { 36 compatible = "mdio-mux-multiplexer"; 37 mux-controls = <&mux 0>; 38 mdio-parent-bus = <&emdio1>; 39 #address-cells = <1>; 40 #size-cells = <0>; 41 42 mdio@0 { /* On-board PHY #1 RGMI1*/ 43 reg = <0x00>; 44 #address-cells = <1>; 45 #size-cells = <0>; 46 }; 47 48 mdio@8 { /* On-board PHY #2 RGMI2*/ 49 reg = <0x8>; 50 #address-cells = <1>; 51 #size-cells = <0>; 52 }; 53 54 mdio@18 { /* Slot #1 */ 55 reg = <0x18>; 56 #address-cells = <1>; 57 #size-cells = <0>; 58 }; 59 60 mdio@19 { /* Slot #2 */ 61 reg = <0x19>; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 }; 65 66 mdio@1a { /* Slot #3 */ 67 reg = <0x1a>; 68 #address-cells = <1>; 69 #size-cells = <0>; 70 }; 71 72 mdio@1b { /* Slot #4 */ 73 reg = <0x1b>; 74 #address-cells = <1>; 75 #size-cells = <0>; 76 }; 77 78 mdio@1c { /* Slot #5 */ 79 reg = <0x1c>; 80 #address-cells = <1>; 81 #size-cells = <0>; 82 }; 83 84 mdio@1d { /* Slot #6 */ 85 reg = <0x1d>; 86 #address-cells = <1>; 87 #size-cells = <0>; 88 }; 89 90 mdio@1e { /* Slot #7 */ 91 reg = <0x1e>; 92 #address-cells = <1>; 93 #size-cells = <0>; 94 }; 95 96 mdio@1f { /* Slot #8 */ 97 reg = <0x1f>; 98 #address-cells = <1>; 99 #size-cells = <0>; 100 }; 101 }; 102 103 mdio-mux-2 { 104 compatible = "mdio-mux-multiplexer"; 105 mux-controls = <&mux 1>; 106 mdio-parent-bus = <&emdio2>; 107 #address-cells = <1>; 108 #size-cells = <0>; 109 110 mdio@0 { /* Slot #1 (secondary EMI) */ 111 reg = <0x00>; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 }; 115 116 mdio@1 { /* Slot #2 (secondary EMI) */ 117 reg = <0x01>; 118 #address-cells = <1>; 119 #size-cells = <0>; 120 }; 121 122 mdio@2 { /* Slot #3 (secondary EMI) */ 123 reg = <0x02>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 }; 127 128 mdio@3 { /* Slot #4 (secondary EMI) */ 129 reg = <0x03>; 130 #address-cells = <1>; 131 #size-cells = <0>; 132 }; 133 134 mdio@4 { /* Slot #5 (secondary EMI) */ 135 reg = <0x04>; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 }; 139 140 mdio@5 { /* Slot #6 (secondary EMI) */ 141 reg = <0x05>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 }; 145 146 mdio@6 { /* Slot #7 (secondary EMI) */ 147 reg = <0x06>; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 }; 151 152 mdio@7 { /* Slot #8 (secondary EMI) */ 153 reg = <0x07>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 }; 157 }; 158}; 159 160&can0 { 161 status = "okay"; 162}; 163 164&can1 { 165 status = "okay"; 166}; 167 168&crypto { 169 status = "okay"; 170}; 171 172&dspi0 { 173 status = "okay"; 174 175 dflash0: flash@0 { 176 #address-cells = <1>; 177 #size-cells = <1>; 178 compatible = "jedec,spi-nor"; 179 reg = <0>; 180 spi-max-frequency = <1000000>; 181 }; 182}; 183 184&dspi1 { 185 status = "okay"; 186 187 dflash1: flash@0 { 188 #address-cells = <1>; 189 #size-cells = <1>; 190 compatible = "jedec,spi-nor"; 191 reg = <0>; 192 spi-max-frequency = <1000000>; 193 }; 194}; 195 196&dspi2 { 197 status = "okay"; 198 199 dflash2: flash@0 { 200 #address-cells = <1>; 201 #size-cells = <1>; 202 compatible = "jedec,spi-nor"; 203 reg = <0>; 204 spi-max-frequency = <1000000>; 205 }; 206}; 207 208&emdio1 { 209 status = "okay"; 210}; 211 212&emdio2 { 213 status = "okay"; 214}; 215 216&esdhc0 { 217 status = "okay"; 218}; 219 220&esdhc1 { 221 status = "okay"; 222}; 223 224&fspi { 225 status = "okay"; 226 227 mt35xu512aba0: flash@0 { 228 #address-cells = <1>; 229 #size-cells = <1>; 230 compatible = "jedec,spi-nor"; 231 m25p,fast-read; 232 spi-max-frequency = <50000000>; 233 reg = <0>; 234 spi-rx-bus-width = <8>; 235 spi-tx-bus-width = <8>; 236 }; 237}; 238 239&i2c0 { 240 status = "okay"; 241 242 fpga@66 { 243 compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", 244 "simple-mfd"; 245 reg = <0x66>; 246 247 mux: mux-controller { 248 compatible = "reg-mux"; 249 #mux-control-cells = <1>; 250 mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ 251 <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */ 252 }; 253 }; 254 255 i2c-mux@77 { 256 compatible = "nxp,pca9547"; 257 reg = <0x77>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 261 i2c@2 { 262 #address-cells = <1>; 263 #size-cells = <0>; 264 reg = <0x2>; 265 266 power-monitor@40 { 267 compatible = "ti,ina220"; 268 reg = <0x40>; 269 shunt-resistor = <500>; 270 }; 271 272 power-monitor@41 { 273 compatible = "ti,ina220"; 274 reg = <0x41>; 275 shunt-resistor = <1000>; 276 }; 277 }; 278 279 i2c@3 { 280 #address-cells = <1>; 281 #size-cells = <0>; 282 reg = <0x3>; 283 284 temperature-sensor@4c { 285 compatible = "nxp,sa56004"; 286 reg = <0x4c>; 287 vcc-supply = <&sb_3v3>; 288 }; 289 290 temperature-sensor@4d { 291 compatible = "nxp,sa56004"; 292 reg = <0x4d>; 293 vcc-supply = <&sb_3v3>; 294 }; 295 296 rtc@51 { 297 compatible = "nxp,pcf2129"; 298 reg = <0x51>; 299 }; 300 }; 301 }; 302}; 303 304&optee { 305 status = "okay"; 306}; 307 308&sata0 { 309 status = "okay"; 310}; 311 312&sata1 { 313 status = "okay"; 314}; 315 316&sata2 { 317 status = "okay"; 318}; 319 320&sata3 { 321 status = "okay"; 322}; 323 324&uart0 { 325 status = "okay"; 326}; 327 328&uart1 { 329 status = "okay"; 330}; 331 332&usb0 { 333 status = "okay"; 334}; 335 336&usb1 { 337 status = "okay"; 338}; 339