xref: /freebsd/sys/contrib/device-tree/src/arm64/freescale/fsl-ls208xa.dtsi (revision b077aed33b7b6aefca7b17ddb250cf521f938613) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2017-2020 NXP
7 *
8 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
9 *
10 */
11
12#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13#include <dt-bindings/thermal/thermal.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15
16/ {
17	compatible = "fsl,ls2080a";
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		crypto = &crypto;
24		rtc1 = &ftm_alarm0;
25		serial0 = &serial0;
26		serial1 = &serial1;
27		serial2 = &serial2;
28		serial3 = &serial3;
29	};
30
31	cpu: cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34	};
35
36	memory@80000000 {
37		device_type = "memory";
38		reg = <0x00000000 0x80000000 0 0x80000000>;
39		      /* DRAM space - 1, size : 2 GB DRAM */
40	};
41
42	sysclk: sysclk {
43		compatible = "fixed-clock";
44		#clock-cells = <0>;
45		clock-frequency = <100000000>;
46		clock-output-names = "sysclk";
47	};
48
49	gic: interrupt-controller@6000000 {
50		compatible = "arm,gic-v3";
51		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52			<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53			<0x0 0x0c0c0000 0 0x2000>, /* GICC */
54			<0x0 0x0c0d0000 0 0x1000>, /* GICH */
55			<0x0 0x0c0e0000 0 0x20000>; /* GICV */
56		#interrupt-cells = <3>;
57		#address-cells = <2>;
58		#size-cells = <2>;
59		ranges;
60		interrupt-controller;
61		interrupts = <1 9 0x4>;
62
63		its: gic-its@6020000 {
64			compatible = "arm,gic-v3-its";
65			msi-controller;
66			reg = <0x0 0x6020000 0 0x20000>;
67		};
68	};
69
70	rstcr: syscon@1e60000 {
71		compatible = "fsl,ls2080a-rstcr", "syscon";
72		reg = <0x0 0x1e60000 0x0 0x4>;
73	};
74
75	reboot {
76		compatible = "syscon-reboot";
77		regmap = <&rstcr>;
78		offset = <0x0>;
79		mask = <0x2>;
80	};
81
82	thermal-zones {
83		ddr-controller1 {
84			polling-delay-passive = <1000>;
85			polling-delay = <5000>;
86			thermal-sensors = <&tmu 1>;
87
88			trips {
89				ddr-ctrler1-crit {
90					temperature = <95000>;
91					hysteresis = <2000>;
92					type = "critical";
93				};
94			};
95		};
96
97		ddr-controller2 {
98			polling-delay-passive = <1000>;
99			polling-delay = <5000>;
100			thermal-sensors = <&tmu 2>;
101
102			trips {
103				ddr-ctrler2-crit {
104					temperature = <95000>;
105					hysteresis = <2000>;
106					type = "critical";
107				};
108			};
109		};
110
111		ddr-controller3 {
112			polling-delay-passive = <1000>;
113			polling-delay = <5000>;
114			thermal-sensors = <&tmu 3>;
115
116			trips {
117				ddr-ctrler3-crit {
118					temperature = <95000>;
119					hysteresis = <2000>;
120					type = "critical";
121				};
122			};
123		};
124
125		core-cluster1 {
126			polling-delay-passive = <1000>;
127			polling-delay = <5000>;
128			thermal-sensors = <&tmu 4>;
129
130			trips {
131				core_cluster1_alert: core-cluster1-alert {
132					temperature = <85000>;
133					hysteresis = <2000>;
134					type = "passive";
135				};
136
137				core-cluster1-crit {
138					temperature = <95000>;
139					hysteresis = <2000>;
140					type = "critical";
141				};
142			};
143
144			cooling-maps {
145				map0 {
146					trip = <&core_cluster1_alert>;
147					cooling-device =
148						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
149						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
150				};
151			};
152		};
153
154		core-cluster2 {
155			polling-delay-passive = <1000>;
156			polling-delay = <5000>;
157			thermal-sensors = <&tmu 5>;
158
159			trips {
160				core_cluster2_alert: core-cluster2-alert {
161					temperature = <85000>;
162					hysteresis = <2000>;
163					type = "passive";
164				};
165
166				core-cluster2-crit {
167					temperature = <95000>;
168					hysteresis = <2000>;
169					type = "critical";
170				};
171			};
172
173			cooling-maps {
174				map0 {
175					trip = <&core_cluster2_alert>;
176					cooling-device =
177						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
178						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
179				};
180			};
181		};
182
183		core-cluster3 {
184			polling-delay-passive = <1000>;
185			polling-delay = <5000>;
186			thermal-sensors = <&tmu 6>;
187
188			trips {
189				core_cluster3_alert: core-cluster3-alert {
190					temperature = <85000>;
191					hysteresis = <2000>;
192					type = "passive";
193				};
194
195				core-cluster3-crit {
196					temperature = <95000>;
197					hysteresis = <2000>;
198					type = "critical";
199				};
200			};
201
202			cooling-maps {
203				map0 {
204					trip = <&core_cluster3_alert>;
205					cooling-device =
206						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207						<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
208				};
209			};
210		};
211
212		core-cluster4 {
213			polling-delay-passive = <1000>;
214			polling-delay = <5000>;
215			thermal-sensors = <&tmu 7>;
216
217			trips {
218				core_cluster4_alert: core-cluster4-alert {
219					temperature = <85000>;
220					hysteresis = <2000>;
221					type = "passive";
222				};
223
224				core-cluster4-crit {
225					temperature = <95000>;
226					hysteresis = <2000>;
227					type = "critical";
228				};
229			};
230
231			cooling-maps {
232				map0 {
233					trip = <&core_cluster4_alert>;
234					cooling-device =
235						<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
236						<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
237				};
238			};
239		};
240	};
241
242	timer {
243		compatible = "arm,armv8-timer";
244		interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
245			     <1 14 4>, /* Physical Non-Secure PPI, active-low */
246			     <1 11 4>, /* Virtual PPI, active-low */
247			     <1 10 4>; /* Hypervisor PPI, active-low */
248		fsl,erratum-a008585;
249	};
250
251	pmu {
252		compatible = "arm,armv8-pmuv3";
253		interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
254	};
255
256	psci {
257		compatible = "arm,psci-0.2";
258		method = "smc";
259	};
260
261	soc {
262		compatible = "simple-bus";
263		#address-cells = <2>;
264		#size-cells = <2>;
265		ranges;
266		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
267
268		clockgen: clocking@1300000 {
269			compatible = "fsl,ls2080a-clockgen";
270			reg = <0 0x1300000 0 0xa0000>;
271			#clock-cells = <2>;
272			clocks = <&sysclk>;
273		};
274
275		dcfg: dcfg@1e00000 {
276			compatible = "fsl,ls2080a-dcfg", "syscon";
277			reg = <0x0 0x1e00000 0x0 0x10000>;
278			little-endian;
279		};
280
281		sfp: efuse@1e80000 {
282			compatible = "fsl,ls1028a-sfp";
283			reg = <0x0 0x1e80000 0x0 0x10000>;
284			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
285					    QORIQ_CLK_PLL_DIV(4)>;
286			clock-names = "sfp";
287		};
288
289		isc: syscon@1f70000 {
290			compatible = "fsl,ls2080a-isc", "syscon";
291			reg = <0x0 0x1f70000 0x0 0x10000>;
292			little-endian;
293			#address-cells = <1>;
294			#size-cells = <1>;
295			ranges = <0x0 0x0 0x1f70000 0x10000>;
296
297			extirq: interrupt-controller@14 {
298				compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq";
299				#interrupt-cells = <2>;
300				#address-cells = <0>;
301				interrupt-controller;
302				reg = <0x14 4>;
303				interrupt-map =
304					<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
305					<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
306					<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
307					<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
308					<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
309					<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
310					<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
311					<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
312					<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
313					<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
314					<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
315					<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
316				interrupt-map-mask = <0xf 0x0>;
317			};
318		};
319
320		tmu: tmu@1f80000 {
321			compatible = "fsl,qoriq-tmu";
322			reg = <0x0 0x1f80000 0x0 0x10000>;
323			interrupts = <0 23 0x4>;
324			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
325			fsl,tmu-calibration = <0x00000000 0x00000026
326					       0x00000001 0x0000002d
327					       0x00000002 0x00000032
328					       0x00000003 0x00000039
329					       0x00000004 0x0000003f
330					       0x00000005 0x00000046
331					       0x00000006 0x0000004d
332					       0x00000007 0x00000054
333					       0x00000008 0x0000005a
334					       0x00000009 0x00000061
335					       0x0000000a 0x0000006a
336					       0x0000000b 0x00000071
337
338					       0x00010000 0x00000025
339					       0x00010001 0x0000002c
340					       0x00010002 0x00000035
341					       0x00010003 0x0000003d
342					       0x00010004 0x00000045
343					       0x00010005 0x0000004e
344					       0x00010006 0x00000057
345					       0x00010007 0x00000061
346					       0x00010008 0x0000006b
347					       0x00010009 0x00000076
348
349					       0x00020000 0x00000029
350					       0x00020001 0x00000033
351					       0x00020002 0x0000003d
352					       0x00020003 0x00000049
353					       0x00020004 0x00000056
354					       0x00020005 0x00000061
355					       0x00020006 0x0000006d
356
357					       0x00030000 0x00000021
358					       0x00030001 0x0000002a
359					       0x00030002 0x0000003c
360					       0x00030003 0x0000004e>;
361			little-endian;
362			#thermal-sensor-cells = <1>;
363		};
364
365		serial0: serial@21c0500 {
366			compatible = "fsl,ns16550", "ns16550a";
367			reg = <0x0 0x21c0500 0x0 0x100>;
368			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
369					    QORIQ_CLK_PLL_DIV(4)>;
370			interrupts = <0 32 0x4>; /* Level high type */
371		};
372
373		serial1: serial@21c0600 {
374			compatible = "fsl,ns16550", "ns16550a";
375			reg = <0x0 0x21c0600 0x0 0x100>;
376			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
377					    QORIQ_CLK_PLL_DIV(4)>;
378			interrupts = <0 32 0x4>; /* Level high type */
379		};
380
381		serial2: serial@21d0500 {
382			compatible = "fsl,ns16550", "ns16550a";
383			reg = <0x0 0x21d0500 0x0 0x100>;
384			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
385					    QORIQ_CLK_PLL_DIV(4)>;
386			interrupts = <0 33 0x4>; /* Level high type */
387		};
388
389		serial3: serial@21d0600 {
390			compatible = "fsl,ns16550", "ns16550a";
391			reg = <0x0 0x21d0600 0x0 0x100>;
392			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
393					    QORIQ_CLK_PLL_DIV(4)>;
394			interrupts = <0 33 0x4>; /* Level high type */
395		};
396
397		cluster1_core0_watchdog: wdt@c000000 {
398			compatible = "arm,sp805", "arm,primecell";
399			reg = <0x0 0xc000000 0x0 0x1000>;
400			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
401					    QORIQ_CLK_PLL_DIV(4)>,
402				 <&clockgen QORIQ_CLK_PLATFORM_PLL
403					    QORIQ_CLK_PLL_DIV(4)>;
404			clock-names = "wdog_clk", "apb_pclk";
405		};
406
407		cluster1_core1_watchdog: wdt@c010000 {
408			compatible = "arm,sp805", "arm,primecell";
409			reg = <0x0 0xc010000 0x0 0x1000>;
410			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
411					    QORIQ_CLK_PLL_DIV(4)>,
412				 <&clockgen QORIQ_CLK_PLATFORM_PLL
413					    QORIQ_CLK_PLL_DIV(4)>;
414			clock-names = "wdog_clk", "apb_pclk";
415		};
416
417		cluster2_core0_watchdog: wdt@c100000 {
418			compatible = "arm,sp805", "arm,primecell";
419			reg = <0x0 0xc100000 0x0 0x1000>;
420			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
421					    QORIQ_CLK_PLL_DIV(4)>,
422				 <&clockgen QORIQ_CLK_PLATFORM_PLL
423					    QORIQ_CLK_PLL_DIV(4)>;
424			clock-names = "wdog_clk", "apb_pclk";
425		};
426
427		cluster2_core1_watchdog: wdt@c110000 {
428			compatible = "arm,sp805", "arm,primecell";
429			reg = <0x0 0xc110000 0x0 0x1000>;
430			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
431					    QORIQ_CLK_PLL_DIV(4)>,
432				 <&clockgen QORIQ_CLK_PLATFORM_PLL
433					    QORIQ_CLK_PLL_DIV(4)>;
434			clock-names = "wdog_clk", "apb_pclk";
435		};
436
437		cluster3_core0_watchdog: wdt@c200000 {
438			compatible = "arm,sp805", "arm,primecell";
439			reg = <0x0 0xc200000 0x0 0x1000>;
440			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
441					    QORIQ_CLK_PLL_DIV(4)>,
442				 <&clockgen QORIQ_CLK_PLATFORM_PLL
443					    QORIQ_CLK_PLL_DIV(4)>;
444			clock-names = "wdog_clk", "apb_pclk";
445		};
446
447		cluster3_core1_watchdog: wdt@c210000 {
448			compatible = "arm,sp805", "arm,primecell";
449			reg = <0x0 0xc210000 0x0 0x1000>;
450			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
451					    QORIQ_CLK_PLL_DIV(4)>,
452				 <&clockgen QORIQ_CLK_PLATFORM_PLL
453					    QORIQ_CLK_PLL_DIV(4)>;
454			clock-names = "wdog_clk", "apb_pclk";
455		};
456
457		cluster4_core0_watchdog: wdt@c300000 {
458			compatible = "arm,sp805", "arm,primecell";
459			reg = <0x0 0xc300000 0x0 0x1000>;
460			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
461					    QORIQ_CLK_PLL_DIV(4)>,
462				 <&clockgen QORIQ_CLK_PLATFORM_PLL
463					    QORIQ_CLK_PLL_DIV(4)>;
464			clock-names = "wdog_clk", "apb_pclk";
465		};
466
467		cluster4_core1_watchdog: wdt@c310000 {
468			compatible = "arm,sp805", "arm,primecell";
469			reg = <0x0 0xc310000 0x0 0x1000>;
470			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
471					    QORIQ_CLK_PLL_DIV(4)>,
472				 <&clockgen QORIQ_CLK_PLATFORM_PLL
473					    QORIQ_CLK_PLL_DIV(4)>;
474			clock-names = "wdog_clk", "apb_pclk";
475		};
476
477		crypto: crypto@8000000 {
478			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
479			fsl,sec-era = <8>;
480			#address-cells = <1>;
481			#size-cells = <1>;
482			ranges = <0x0 0x00 0x8000000 0x100000>;
483			reg = <0x00 0x8000000 0x0 0x100000>;
484			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
485			dma-coherent;
486
487			sec_jr0: jr@10000 {
488				compatible = "fsl,sec-v5.0-job-ring",
489					     "fsl,sec-v4.0-job-ring";
490				reg = <0x10000 0x10000>;
491				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
492			};
493
494			sec_jr1: jr@20000 {
495				compatible = "fsl,sec-v5.0-job-ring",
496					     "fsl,sec-v4.0-job-ring";
497				reg = <0x20000 0x10000>;
498				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
499			};
500
501			sec_jr2: jr@30000 {
502				compatible = "fsl,sec-v5.0-job-ring",
503					     "fsl,sec-v4.0-job-ring";
504				reg = <0x30000 0x10000>;
505				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
506			};
507
508			sec_jr3: jr@40000 {
509				compatible = "fsl,sec-v5.0-job-ring",
510					     "fsl,sec-v4.0-job-ring";
511				reg = <0x40000 0x10000>;
512				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
513			};
514		};
515
516		console@8340020 {
517			compatible = "fsl,dpaa2-console";
518			reg = <0x00000000 0x08340020 0 0x2>;
519		};
520
521		ptp-timer@8b95000 {
522			compatible = "fsl,dpaa2-ptp";
523			reg = <0x0 0x8b95000 0x0 0x100>;
524			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
525					    QORIQ_CLK_PLL_DIV(2)>;
526			little-endian;
527			fsl,extts-fifo;
528		};
529
530		emdio1: mdio@8b96000 {
531			compatible = "fsl,fman-memac-mdio";
532			reg = <0x0 0x8b96000 0x0 0x1000>;
533			little-endian;
534			#address-cells = <1>;
535			#size-cells = <0>;
536			status = "disabled";
537		};
538
539		emdio2: mdio@8b97000 {
540			compatible = "fsl,fman-memac-mdio";
541			reg = <0x0 0x8b97000 0x0 0x1000>;
542			little-endian;
543			#address-cells = <1>;
544			#size-cells = <0>;
545			status = "disabled";
546		};
547
548		pcs_mdio1: mdio@8c07000 {
549			compatible = "fsl,fman-memac-mdio";
550			reg = <0x0 0x8c07000 0x0 0x1000>;
551			little-endian;
552			#address-cells = <1>;
553			#size-cells = <0>;
554			status = "disabled";
555
556			pcs1: ethernet-phy@0 {
557				reg = <0>;
558			};
559		};
560
561		pcs_mdio2: mdio@8c0b000 {
562			compatible = "fsl,fman-memac-mdio";
563			reg = <0x0 0x8c0b000 0x0 0x1000>;
564			little-endian;
565			#address-cells = <1>;
566			#size-cells = <0>;
567			status = "disabled";
568
569			pcs2: ethernet-phy@0 {
570				reg = <0>;
571			};
572		};
573
574		pcs_mdio3: mdio@8c0f000 {
575			compatible = "fsl,fman-memac-mdio";
576			reg = <0x0 0x8c0f000 0x0 0x1000>;
577			little-endian;
578			#address-cells = <1>;
579			#size-cells = <0>;
580			status = "disabled";
581
582			pcs3: ethernet-phy@0 {
583				reg = <0>;
584			};
585		};
586
587		pcs_mdio4: mdio@8c13000 {
588			compatible = "fsl,fman-memac-mdio";
589			reg = <0x0 0x8c13000 0x0 0x1000>;
590			little-endian;
591			#address-cells = <1>;
592			#size-cells = <0>;
593			status = "disabled";
594
595			pcs4: ethernet-phy@0 {
596				reg = <0>;
597			};
598		};
599
600		pcs_mdio5: mdio@8c17000 {
601			compatible = "fsl,fman-memac-mdio";
602			reg = <0x0 0x8c17000 0x0 0x1000>;
603			little-endian;
604			#address-cells = <1>;
605			#size-cells = <0>;
606			status = "disabled";
607
608			pcs5: ethernet-phy@0 {
609				reg = <0>;
610			};
611		};
612
613		pcs_mdio6: mdio@8c1b000 {
614			compatible = "fsl,fman-memac-mdio";
615			reg = <0x0 0x8c1b000 0x0 0x1000>;
616			little-endian;
617			#address-cells = <1>;
618			#size-cells = <0>;
619			status = "disabled";
620
621			pcs6: ethernet-phy@0 {
622				reg = <0>;
623			};
624		};
625
626		pcs_mdio7: mdio@8c1f000 {
627			compatible = "fsl,fman-memac-mdio";
628			reg = <0x0 0x8c1f000 0x0 0x1000>;
629			little-endian;
630			#address-cells = <1>;
631			#size-cells = <0>;
632			status = "disabled";
633
634			pcs7: ethernet-phy@0 {
635				reg = <0>;
636			};
637		};
638
639		pcs_mdio8: mdio@8c23000 {
640			compatible = "fsl,fman-memac-mdio";
641			reg = <0x0 0x8c23000 0x0 0x1000>;
642			little-endian;
643			#address-cells = <1>;
644			#size-cells = <0>;
645			status = "disabled";
646
647			pcs8: ethernet-phy@0 {
648				reg = <0>;
649			};
650		};
651
652		pcs_mdio9: mdio@8c27000 {
653			compatible = "fsl,fman-memac-mdio";
654			reg = <0x0 0x8c27000 0x0 0x1000>;
655			little-endian;
656			#address-cells = <1>;
657			#size-cells = <0>;
658			status = "disabled";
659
660			pcs9: ethernet-phy@0 {
661				reg = <0>;
662			};
663		};
664
665		pcs_mdio10: mdio@8c2b000 {
666			compatible = "fsl,fman-memac-mdio";
667			reg = <0x0 0x8c2b000 0x0 0x1000>;
668			little-endian;
669			#address-cells = <1>;
670			#size-cells = <0>;
671			status = "disabled";
672
673			pcs10: ethernet-phy@0 {
674				reg = <0>;
675			};
676		};
677
678		pcs_mdio11: mdio@8c2f000 {
679			compatible = "fsl,fman-memac-mdio";
680			reg = <0x0 0x8c2f000 0x0 0x1000>;
681			little-endian;
682			#address-cells = <1>;
683			#size-cells = <0>;
684			status = "disabled";
685
686			pcs11: ethernet-phy@0 {
687				reg = <0>;
688			};
689		};
690
691		pcs_mdio12: mdio@8c33000 {
692			compatible = "fsl,fman-memac-mdio";
693			reg = <0x0 0x8c33000 0x0 0x1000>;
694			little-endian;
695			#address-cells = <1>;
696			#size-cells = <0>;
697			status = "disabled";
698
699			pcs12: ethernet-phy@0 {
700				reg = <0>;
701			};
702		};
703
704		pcs_mdio13: mdio@8c37000 {
705			compatible = "fsl,fman-memac-mdio";
706			reg = <0x0 0x8c37000 0x0 0x1000>;
707			little-endian;
708			#address-cells = <1>;
709			#size-cells = <0>;
710			status = "disabled";
711
712			pcs13: ethernet-phy@0 {
713				reg = <0>;
714			};
715		};
716
717		pcs_mdio14: mdio@8c3b000 {
718			compatible = "fsl,fman-memac-mdio";
719			reg = <0x0 0x8c3b000 0x0 0x1000>;
720			little-endian;
721			#address-cells = <1>;
722			#size-cells = <0>;
723			status = "disabled";
724
725			pcs14: ethernet-phy@0 {
726				reg = <0>;
727			};
728		};
729
730		pcs_mdio15: mdio@8c3f000 {
731			compatible = "fsl,fman-memac-mdio";
732			reg = <0x0 0x8c3f000 0x0 0x1000>;
733			little-endian;
734			#address-cells = <1>;
735			#size-cells = <0>;
736			status = "disabled";
737
738			pcs15: ethernet-phy@0 {
739				reg = <0>;
740			};
741		};
742
743		pcs_mdio16: mdio@8c43000 {
744			compatible = "fsl,fman-memac-mdio";
745			reg = <0x0 0x8c43000 0x0 0x1000>;
746			little-endian;
747			#address-cells = <1>;
748			#size-cells = <0>;
749			status = "disabled";
750
751			pcs16: ethernet-phy@0 {
752				reg = <0>;
753			};
754		};
755
756		fsl_mc: fsl-mc@80c000000 {
757			compatible = "fsl,qoriq-mc";
758			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
759			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
760			msi-parent = <&its>;
761			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
762			dma-coherent;
763			#address-cells = <3>;
764			#size-cells = <1>;
765
766			/*
767			 * Region type 0x0 - MC portals
768			 * Region type 0x1 - QBMAN portals
769			 */
770			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
771				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
772
773			/*
774			 * Define the maximum number of MACs present on the SoC.
775			 */
776			dpmacs {
777				#address-cells = <1>;
778				#size-cells = <0>;
779
780				dpmac1: ethernet@1 {
781					compatible = "fsl,qoriq-mc-dpmac";
782					reg = <0x1>;
783					pcs-handle = <&pcs1>;
784				};
785
786				dpmac2: ethernet@2 {
787					compatible = "fsl,qoriq-mc-dpmac";
788					reg = <0x2>;
789					pcs-handle = <&pcs2>;
790				};
791
792				dpmac3: ethernet@3 {
793					compatible = "fsl,qoriq-mc-dpmac";
794					reg = <0x3>;
795					pcs-handle = <&pcs3>;
796				};
797
798				dpmac4: ethernet@4 {
799					compatible = "fsl,qoriq-mc-dpmac";
800					reg = <0x4>;
801					pcs-handle = <&pcs4>;
802				};
803
804				dpmac5: ethernet@5 {
805					compatible = "fsl,qoriq-mc-dpmac";
806					reg = <0x5>;
807					pcs-handle = <&pcs5>;
808				};
809
810				dpmac6: ethernet@6 {
811					compatible = "fsl,qoriq-mc-dpmac";
812					reg = <0x6>;
813					pcs-handle = <&pcs6>;
814				};
815
816				dpmac7: ethernet@7 {
817					compatible = "fsl,qoriq-mc-dpmac";
818					reg = <0x7>;
819					pcs-handle = <&pcs7>;
820				};
821
822				dpmac8: ethernet@8 {
823					compatible = "fsl,qoriq-mc-dpmac";
824					reg = <0x8>;
825					pcs-handle = <&pcs8>;
826				};
827
828				dpmac9: ethernet@9 {
829					compatible = "fsl,qoriq-mc-dpmac";
830					reg = <0x9>;
831					pcs-handle = <&pcs9>;
832				};
833
834				dpmac10: ethernet@a {
835					compatible = "fsl,qoriq-mc-dpmac";
836					reg = <0xa>;
837					pcs-handle = <&pcs10>;
838				};
839
840				dpmac11: ethernet@b {
841					compatible = "fsl,qoriq-mc-dpmac";
842					reg = <0xb>;
843					pcs-handle = <&pcs11>;
844				};
845
846				dpmac12: ethernet@c {
847					compatible = "fsl,qoriq-mc-dpmac";
848					reg = <0xc>;
849					pcs-handle = <&pcs12>;
850				};
851
852				dpmac13: ethernet@d {
853					compatible = "fsl,qoriq-mc-dpmac";
854					reg = <0xd>;
855					pcs-handle = <&pcs13>;
856				};
857
858				dpmac14: ethernet@e {
859					compatible = "fsl,qoriq-mc-dpmac";
860					reg = <0xe>;
861					pcs-handle = <&pcs14>;
862				};
863
864				dpmac15: ethernet@f {
865					compatible = "fsl,qoriq-mc-dpmac";
866					reg = <0xf>;
867					pcs-handle = <&pcs15>;
868				};
869
870				dpmac16: ethernet@10 {
871					compatible = "fsl,qoriq-mc-dpmac";
872					reg = <0x10>;
873					pcs-handle = <&pcs16>;
874				};
875			};
876		};
877
878		smmu: iommu@5000000 {
879			compatible = "arm,mmu-500";
880			reg = <0 0x5000000 0 0x800000>;
881			#global-interrupts = <12>;
882			#iommu-cells = <1>;
883			stream-match-mask = <0x7C00>;
884			dma-coherent;
885			interrupts = <0 13 4>, /* global secure fault */
886				     <0 14 4>, /* combined secure interrupt */
887				     <0 15 4>, /* global non-secure fault */
888				     <0 16 4>, /* combined non-secure interrupt */
889				/* performance counter interrupts 0-7 */
890				     <0 211 4>, <0 212 4>,
891				     <0 213 4>, <0 214 4>,
892				     <0 215 4>, <0 216 4>,
893				     <0 217 4>, <0 218 4>,
894				/* per context interrupt, 64 interrupts */
895				     <0 146 4>, <0 147 4>,
896				     <0 148 4>, <0 149 4>,
897				     <0 150 4>, <0 151 4>,
898				     <0 152 4>, <0 153 4>,
899				     <0 154 4>, <0 155 4>,
900				     <0 156 4>, <0 157 4>,
901				     <0 158 4>, <0 159 4>,
902				     <0 160 4>, <0 161 4>,
903				     <0 162 4>, <0 163 4>,
904				     <0 164 4>, <0 165 4>,
905				     <0 166 4>, <0 167 4>,
906				     <0 168 4>, <0 169 4>,
907				     <0 170 4>, <0 171 4>,
908				     <0 172 4>, <0 173 4>,
909				     <0 174 4>, <0 175 4>,
910				     <0 176 4>, <0 177 4>,
911				     <0 178 4>, <0 179 4>,
912				     <0 180 4>, <0 181 4>,
913				     <0 182 4>, <0 183 4>,
914				     <0 184 4>, <0 185 4>,
915				     <0 186 4>, <0 187 4>,
916				     <0 188 4>, <0 189 4>,
917				     <0 190 4>, <0 191 4>,
918				     <0 192 4>, <0 193 4>,
919				     <0 194 4>, <0 195 4>,
920				     <0 196 4>, <0 197 4>,
921				     <0 198 4>, <0 199 4>,
922				     <0 200 4>, <0 201 4>,
923				     <0 202 4>, <0 203 4>,
924				     <0 204 4>, <0 205 4>,
925				     <0 206 4>, <0 207 4>,
926				     <0 208 4>, <0 209 4>;
927		};
928
929		dspi: spi@2100000 {
930			status = "disabled";
931			compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
932			#address-cells = <1>;
933			#size-cells = <0>;
934			reg = <0x0 0x2100000 0x0 0x10000>;
935			interrupts = <0 26 0x4>; /* Level high type */
936			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
937					    QORIQ_CLK_PLL_DIV(4)>;
938			clock-names = "dspi";
939			spi-num-chipselects = <5>;
940		};
941
942		esdhc: esdhc@2140000 {
943			status = "disabled";
944			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
945			reg = <0x0 0x2140000 0x0 0x10000>;
946			interrupts = <0 28 0x4>; /* Level high type */
947			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
948					    QORIQ_CLK_PLL_DIV(2)>;
949			voltage-ranges = <1800 1800 3300 3300>;
950			sdhci,auto-cmd12;
951			little-endian;
952			bus-width = <4>;
953		};
954
955		gpio0: gpio@2300000 {
956			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
957			reg = <0x0 0x2300000 0x0 0x10000>;
958			interrupts = <0 36 0x4>; /* Level high type */
959			gpio-controller;
960			little-endian;
961			#gpio-cells = <2>;
962			interrupt-controller;
963			#interrupt-cells = <2>;
964		};
965
966		gpio1: gpio@2310000 {
967			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
968			reg = <0x0 0x2310000 0x0 0x10000>;
969			interrupts = <0 36 0x4>; /* Level high type */
970			gpio-controller;
971			little-endian;
972			#gpio-cells = <2>;
973			interrupt-controller;
974			#interrupt-cells = <2>;
975		};
976
977		gpio2: gpio@2320000 {
978			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
979			reg = <0x0 0x2320000 0x0 0x10000>;
980			interrupts = <0 37 0x4>; /* Level high type */
981			gpio-controller;
982			little-endian;
983			#gpio-cells = <2>;
984			interrupt-controller;
985			#interrupt-cells = <2>;
986		};
987
988		gpio3: gpio@2330000 {
989			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
990			reg = <0x0 0x2330000 0x0 0x10000>;
991			interrupts = <0 37 0x4>; /* Level high type */
992			gpio-controller;
993			little-endian;
994			#gpio-cells = <2>;
995			interrupt-controller;
996			#interrupt-cells = <2>;
997		};
998
999		i2c0: i2c@2000000 {
1000			status = "disabled";
1001			compatible = "fsl,vf610-i2c";
1002			#address-cells = <1>;
1003			#size-cells = <0>;
1004			reg = <0x0 0x2000000 0x0 0x10000>;
1005			interrupts = <0 34 0x4>; /* Level high type */
1006			clock-names = "i2c";
1007			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1008					    QORIQ_CLK_PLL_DIV(4)>;
1009		};
1010
1011		i2c1: i2c@2010000 {
1012			status = "disabled";
1013			compatible = "fsl,vf610-i2c";
1014			#address-cells = <1>;
1015			#size-cells = <0>;
1016			reg = <0x0 0x2010000 0x0 0x10000>;
1017			interrupts = <0 34 0x4>; /* Level high type */
1018			clock-names = "i2c";
1019			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1020					    QORIQ_CLK_PLL_DIV(4)>;
1021		};
1022
1023		i2c2: i2c@2020000 {
1024			status = "disabled";
1025			compatible = "fsl,vf610-i2c";
1026			#address-cells = <1>;
1027			#size-cells = <0>;
1028			reg = <0x0 0x2020000 0x0 0x10000>;
1029			interrupts = <0 35 0x4>; /* Level high type */
1030			clock-names = "i2c";
1031			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1032					    QORIQ_CLK_PLL_DIV(4)>;
1033		};
1034
1035		i2c3: i2c@2030000 {
1036			status = "disabled";
1037			compatible = "fsl,vf610-i2c";
1038			#address-cells = <1>;
1039			#size-cells = <0>;
1040			reg = <0x0 0x2030000 0x0 0x10000>;
1041			interrupts = <0 35 0x4>; /* Level high type */
1042			clock-names = "i2c";
1043			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1044					    QORIQ_CLK_PLL_DIV(4)>;
1045		};
1046
1047		ifc: memory-controller@2240000 {
1048			compatible = "fsl,ifc";
1049			reg = <0x0 0x2240000 0x0 0x20000>;
1050			interrupts = <0 21 0x4>; /* Level high type */
1051			little-endian;
1052			#address-cells = <2>;
1053			#size-cells = <1>;
1054
1055			ranges = <0 0 0x5 0x80000000 0x08000000
1056				  2 0 0x5 0x30000000 0x00010000
1057				  3 0 0x5 0x20000000 0x00010000>;
1058		};
1059
1060		qspi: spi@20c0000 {
1061			compatible = "fsl,ls2080a-qspi";
1062			#address-cells = <1>;
1063			#size-cells = <0>;
1064			reg = <0x0 0x20c0000 0x0 0x10000>,
1065			      <0x0 0x20000000 0x0 0x10000000>;
1066			reg-names = "QuadSPI", "QuadSPI-memory";
1067			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1068			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1069					    QORIQ_CLK_PLL_DIV(4)>,
1070				 <&clockgen QORIQ_CLK_PLATFORM_PLL
1071					    QORIQ_CLK_PLL_DIV(4)>;
1072			clock-names = "qspi_en", "qspi";
1073			status = "disabled";
1074		};
1075
1076		pcie1: pcie@3400000 {
1077			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1078			reg-names = "regs", "config";
1079			interrupts = <0 108 0x4>; /* Level high type */
1080			interrupt-names = "intr";
1081			#address-cells = <3>;
1082			#size-cells = <2>;
1083			device_type = "pci";
1084			dma-coherent;
1085			num-viewport = <6>;
1086			bus-range = <0x0 0xff>;
1087			msi-parent = <&its>;
1088			#interrupt-cells = <1>;
1089			interrupt-map-mask = <0 0 0 7>;
1090			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1091					<0000 0 0 2 &gic 0 0 0 110 4>,
1092					<0000 0 0 3 &gic 0 0 0 111 4>,
1093					<0000 0 0 4 &gic 0 0 0 112 4>;
1094			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1095			status = "disabled";
1096		};
1097
1098		pcie2: pcie@3500000 {
1099			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1100			reg-names = "regs", "config";
1101			interrupts = <0 113 0x4>; /* Level high type */
1102			interrupt-names = "intr";
1103			#address-cells = <3>;
1104			#size-cells = <2>;
1105			device_type = "pci";
1106			dma-coherent;
1107			num-viewport = <6>;
1108			bus-range = <0x0 0xff>;
1109			msi-parent = <&its>;
1110			#interrupt-cells = <1>;
1111			interrupt-map-mask = <0 0 0 7>;
1112			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1113					<0000 0 0 2 &gic 0 0 0 115 4>,
1114					<0000 0 0 3 &gic 0 0 0 116 4>,
1115					<0000 0 0 4 &gic 0 0 0 117 4>;
1116			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1117			status = "disabled";
1118		};
1119
1120		pcie3: pcie@3600000 {
1121			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1122			reg-names = "regs", "config";
1123			interrupts = <0 118 0x4>; /* Level high type */
1124			interrupt-names = "intr";
1125			#address-cells = <3>;
1126			#size-cells = <2>;
1127			device_type = "pci";
1128			dma-coherent;
1129			num-viewport = <256>;
1130			bus-range = <0x0 0xff>;
1131			msi-parent = <&its>;
1132			#interrupt-cells = <1>;
1133			interrupt-map-mask = <0 0 0 7>;
1134			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1135					<0000 0 0 2 &gic 0 0 0 120 4>,
1136					<0000 0 0 3 &gic 0 0 0 121 4>,
1137					<0000 0 0 4 &gic 0 0 0 122 4>;
1138			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1139			status = "disabled";
1140		};
1141
1142		pcie4: pcie@3700000 {
1143			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1144			reg-names = "regs", "config";
1145			interrupts = <0 123 0x4>; /* Level high type */
1146			interrupt-names = "intr";
1147			#address-cells = <3>;
1148			#size-cells = <2>;
1149			device_type = "pci";
1150			dma-coherent;
1151			num-viewport = <6>;
1152			bus-range = <0x0 0xff>;
1153			msi-parent = <&its>;
1154			#interrupt-cells = <1>;
1155			interrupt-map-mask = <0 0 0 7>;
1156			interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1157					<0000 0 0 2 &gic 0 0 0 125 4>,
1158					<0000 0 0 3 &gic 0 0 0 126 4>,
1159					<0000 0 0 4 &gic 0 0 0 127 4>;
1160			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1161			status = "disabled";
1162		};
1163
1164		sata0: sata@3200000 {
1165			status = "disabled";
1166			compatible = "fsl,ls2080a-ahci";
1167			reg = <0x0 0x3200000 0x0 0x10000>;
1168			interrupts = <0 133 0x4>; /* Level high type */
1169			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1170					    QORIQ_CLK_PLL_DIV(4)>;
1171			dma-coherent;
1172		};
1173
1174		sata1: sata@3210000 {
1175			status = "disabled";
1176			compatible = "fsl,ls2080a-ahci";
1177			reg = <0x0 0x3210000 0x0 0x10000>;
1178			interrupts = <0 136 0x4>; /* Level high type */
1179			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1180					    QORIQ_CLK_PLL_DIV(4)>;
1181			dma-coherent;
1182		};
1183
1184		usb0: usb@3100000 {
1185			status = "disabled";
1186			compatible = "snps,dwc3";
1187			reg = <0x0 0x3100000 0x0 0x10000>;
1188			interrupts = <0 80 0x4>; /* Level high type */
1189			dr_mode = "host";
1190			snps,quirk-frame-length-adjustment = <0x20>;
1191			snps,dis_rxdet_inp3_quirk;
1192			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1193		};
1194
1195		usb1: usb@3110000 {
1196			status = "disabled";
1197			compatible = "snps,dwc3";
1198			reg = <0x0 0x3110000 0x0 0x10000>;
1199			interrupts = <0 81 0x4>; /* Level high type */
1200			dr_mode = "host";
1201			snps,quirk-frame-length-adjustment = <0x20>;
1202			snps,dis_rxdet_inp3_quirk;
1203			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1204		};
1205
1206		ccn@4000000 {
1207			compatible = "arm,ccn-504";
1208			reg = <0x0 0x04000000 0x0 0x01000000>;
1209			interrupts = <0 12 4>;
1210		};
1211
1212		rcpm: power-controller@1e34040 {
1213			compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
1214			reg = <0x0 0x1e34040 0x0 0x18>;
1215			#fsl,rcpm-wakeup-cells = <6>;
1216			little-endian;
1217		};
1218
1219		ftm_alarm0: timer@2800000 {
1220			compatible = "fsl,ls208xa-ftm-alarm";
1221			reg = <0x0 0x2800000 0x0 0x10000>;
1222			fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1223			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1224		};
1225	};
1226
1227	ddr1: memory-controller@1080000 {
1228		compatible = "fsl,qoriq-memory-controller";
1229		reg = <0x0 0x1080000 0x0 0x1000>;
1230		interrupts = <0 17 0x4>;
1231		little-endian;
1232	};
1233
1234	ddr2: memory-controller@1090000 {
1235		compatible = "fsl,qoriq-memory-controller";
1236		reg = <0x0 0x1090000 0x0 0x1000>;
1237		interrupts = <0 18 0x4>;
1238		little-endian;
1239	};
1240
1241	firmware {
1242		optee {
1243			compatible = "linaro,optee-tz";
1244			method = "smc";
1245		};
1246	};
1247};
1248