xref: /freebsd/sys/contrib/device-tree/src/arm64/freescale/fsl-ls208xa.dtsi (revision 7fdf597e96a02165cfe22ff357b857d5fa15ed8a) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2017-2020 NXP
7 *
8 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
9 *
10 */
11
12#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13#include <dt-bindings/thermal/thermal.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15
16/ {
17	compatible = "fsl,ls2080a";
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	aliases {
23		crypto = &crypto;
24		rtc1 = &ftm_alarm0;
25		serial0 = &serial0;
26		serial1 = &serial1;
27		serial2 = &serial2;
28		serial3 = &serial3;
29	};
30
31	cpu: cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34	};
35
36	memory@80000000 {
37		device_type = "memory";
38		reg = <0x00000000 0x80000000 0 0x80000000>;
39		      /* DRAM space - 1, size : 2 GB DRAM */
40	};
41
42	sysclk: sysclk {
43		compatible = "fixed-clock";
44		#clock-cells = <0>;
45		clock-frequency = <100000000>;
46		clock-output-names = "sysclk";
47	};
48
49	gic: interrupt-controller@6000000 {
50		compatible = "arm,gic-v3";
51		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52			<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53			<0x0 0x0c0c0000 0 0x2000>, /* GICC */
54			<0x0 0x0c0d0000 0 0x1000>, /* GICH */
55			<0x0 0x0c0e0000 0 0x20000>; /* GICV */
56		#interrupt-cells = <3>;
57		#address-cells = <2>;
58		#size-cells = <2>;
59		ranges;
60		interrupt-controller;
61		interrupts = <1 9 0x4>;
62
63		its: msi-controller@6020000 {
64			compatible = "arm,gic-v3-its";
65			msi-controller;
66			reg = <0x0 0x6020000 0 0x20000>;
67		};
68	};
69
70	rstcr: syscon@1e60000 {
71		compatible = "fsl,ls2080a-rstcr", "syscon";
72		reg = <0x0 0x1e60000 0x0 0x4>;
73	};
74
75	reboot {
76		compatible = "syscon-reboot";
77		regmap = <&rstcr>;
78		offset = <0x0>;
79		mask = <0x2>;
80	};
81
82	thermal-zones {
83		ddr-controller1 {
84			polling-delay-passive = <1000>;
85			polling-delay = <5000>;
86			thermal-sensors = <&tmu 1>;
87
88			trips {
89				ddr-ctrler1-crit {
90					temperature = <95000>;
91					hysteresis = <2000>;
92					type = "critical";
93				};
94			};
95		};
96
97		ddr-controller2 {
98			polling-delay-passive = <1000>;
99			polling-delay = <5000>;
100			thermal-sensors = <&tmu 2>;
101
102			trips {
103				ddr-ctrler2-crit {
104					temperature = <95000>;
105					hysteresis = <2000>;
106					type = "critical";
107				};
108			};
109		};
110
111		ddr-controller3 {
112			polling-delay-passive = <1000>;
113			polling-delay = <5000>;
114			thermal-sensors = <&tmu 3>;
115
116			trips {
117				ddr-ctrler3-crit {
118					temperature = <95000>;
119					hysteresis = <2000>;
120					type = "critical";
121				};
122			};
123		};
124
125		core-cluster1 {
126			polling-delay-passive = <1000>;
127			polling-delay = <5000>;
128			thermal-sensors = <&tmu 4>;
129
130			trips {
131				core_cluster1_alert: core-cluster1-alert {
132					temperature = <85000>;
133					hysteresis = <2000>;
134					type = "passive";
135				};
136
137				core-cluster1-crit {
138					temperature = <95000>;
139					hysteresis = <2000>;
140					type = "critical";
141				};
142			};
143
144			cooling-maps {
145				map0 {
146					trip = <&core_cluster1_alert>;
147					cooling-device =
148						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
149						<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
150				};
151			};
152		};
153
154		core-cluster2 {
155			polling-delay-passive = <1000>;
156			polling-delay = <5000>;
157			thermal-sensors = <&tmu 5>;
158
159			trips {
160				core_cluster2_alert: core-cluster2-alert {
161					temperature = <85000>;
162					hysteresis = <2000>;
163					type = "passive";
164				};
165
166				core-cluster2-crit {
167					temperature = <95000>;
168					hysteresis = <2000>;
169					type = "critical";
170				};
171			};
172
173			cooling-maps {
174				map0 {
175					trip = <&core_cluster2_alert>;
176					cooling-device =
177						<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
178						<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
179				};
180			};
181		};
182
183		core-cluster3 {
184			polling-delay-passive = <1000>;
185			polling-delay = <5000>;
186			thermal-sensors = <&tmu 6>;
187
188			trips {
189				core_cluster3_alert: core-cluster3-alert {
190					temperature = <85000>;
191					hysteresis = <2000>;
192					type = "passive";
193				};
194
195				core-cluster3-crit {
196					temperature = <95000>;
197					hysteresis = <2000>;
198					type = "critical";
199				};
200			};
201
202			cooling-maps {
203				map0 {
204					trip = <&core_cluster3_alert>;
205					cooling-device =
206						<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
207						<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
208				};
209			};
210		};
211
212		core-cluster4 {
213			polling-delay-passive = <1000>;
214			polling-delay = <5000>;
215			thermal-sensors = <&tmu 7>;
216
217			trips {
218				core_cluster4_alert: core-cluster4-alert {
219					temperature = <85000>;
220					hysteresis = <2000>;
221					type = "passive";
222				};
223
224				core-cluster4-crit {
225					temperature = <95000>;
226					hysteresis = <2000>;
227					type = "critical";
228				};
229			};
230
231			cooling-maps {
232				map0 {
233					trip = <&core_cluster4_alert>;
234					cooling-device =
235						<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
236						<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
237				};
238			};
239		};
240	};
241
242	timer: timer {
243		compatible = "arm,armv8-timer";
244		interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
245			     <1 14 4>, /* Physical Non-Secure PPI, active-low */
246			     <1 11 4>, /* Virtual PPI, active-low */
247			     <1 10 4>; /* Hypervisor PPI, active-low */
248	};
249
250	pmu {
251		compatible = "arm,armv8-pmuv3";
252		interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
253	};
254
255	psci {
256		compatible = "arm,psci-0.2";
257		method = "smc";
258	};
259
260	soc {
261		compatible = "simple-bus";
262		#address-cells = <2>;
263		#size-cells = <2>;
264		ranges;
265		dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
266
267		clockgen: clocking@1300000 {
268			compatible = "fsl,ls2080a-clockgen";
269			reg = <0 0x1300000 0 0xa0000>;
270			#clock-cells = <2>;
271			clocks = <&sysclk>;
272		};
273
274		dcfg: dcfg@1e00000 {
275			compatible = "fsl,ls2080a-dcfg", "syscon";
276			reg = <0x0 0x1e00000 0x0 0x10000>;
277			little-endian;
278		};
279
280		sfp: efuse@1e80000 {
281			compatible = "fsl,ls1028a-sfp";
282			reg = <0x0 0x1e80000 0x0 0x10000>;
283			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
284					    QORIQ_CLK_PLL_DIV(4)>;
285			clock-names = "sfp";
286		};
287
288		isc: syscon@1f70000 {
289			compatible = "fsl,ls2080a-isc", "syscon";
290			reg = <0x0 0x1f70000 0x0 0x10000>;
291			little-endian;
292			#address-cells = <1>;
293			#size-cells = <1>;
294			ranges = <0x0 0x0 0x1f70000 0x10000>;
295
296			extirq: interrupt-controller@14 {
297				compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq";
298				#interrupt-cells = <2>;
299				#address-cells = <0>;
300				interrupt-controller;
301				reg = <0x14 4>;
302				interrupt-map =
303					<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
304					<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
305					<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
306					<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
307					<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
308					<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
309					<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
310					<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
311					<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
312					<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
313					<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
314					<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
315				interrupt-map-mask = <0xf 0x0>;
316			};
317		};
318
319		tmu: tmu@1f80000 {
320			compatible = "fsl,qoriq-tmu";
321			reg = <0x0 0x1f80000 0x0 0x10000>;
322			interrupts = <0 23 0x4>;
323			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
324			fsl,tmu-calibration =
325					<0x00000000 0x00000026>,
326					<0x00000001 0x0000002d>,
327					<0x00000002 0x00000032>,
328					<0x00000003 0x00000039>,
329					<0x00000004 0x0000003f>,
330					<0x00000005 0x00000046>,
331					<0x00000006 0x0000004d>,
332					<0x00000007 0x00000054>,
333					<0x00000008 0x0000005a>,
334					<0x00000009 0x00000061>,
335					<0x0000000a 0x0000006a>,
336					<0x0000000b 0x00000071>,
337
338					<0x00010000 0x00000025>,
339					<0x00010001 0x0000002c>,
340					<0x00010002 0x00000035>,
341					<0x00010003 0x0000003d>,
342					<0x00010004 0x00000045>,
343					<0x00010005 0x0000004e>,
344					<0x00010006 0x00000057>,
345					<0x00010007 0x00000061>,
346					<0x00010008 0x0000006b>,
347					<0x00010009 0x00000076>,
348
349					<0x00020000 0x00000029>,
350					<0x00020001 0x00000033>,
351					<0x00020002 0x0000003d>,
352					<0x00020003 0x00000049>,
353					<0x00020004 0x00000056>,
354					<0x00020005 0x00000061>,
355					<0x00020006 0x0000006d>,
356
357					<0x00030000 0x00000021>,
358					<0x00030001 0x0000002a>,
359					<0x00030002 0x0000003c>,
360					<0x00030003 0x0000004e>;
361			little-endian;
362			#thermal-sensor-cells = <1>;
363		};
364
365		serial0: serial@21c0500 {
366			compatible = "fsl,ns16550", "ns16550a";
367			reg = <0x0 0x21c0500 0x0 0x100>;
368			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
369					    QORIQ_CLK_PLL_DIV(4)>;
370			interrupts = <0 32 0x4>; /* Level high type */
371		};
372
373		serial1: serial@21c0600 {
374			compatible = "fsl,ns16550", "ns16550a";
375			reg = <0x0 0x21c0600 0x0 0x100>;
376			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
377					    QORIQ_CLK_PLL_DIV(4)>;
378			interrupts = <0 32 0x4>; /* Level high type */
379		};
380
381		serial2: serial@21d0500 {
382			compatible = "fsl,ns16550", "ns16550a";
383			reg = <0x0 0x21d0500 0x0 0x100>;
384			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
385					    QORIQ_CLK_PLL_DIV(4)>;
386			interrupts = <0 33 0x4>; /* Level high type */
387		};
388
389		serial3: serial@21d0600 {
390			compatible = "fsl,ns16550", "ns16550a";
391			reg = <0x0 0x21d0600 0x0 0x100>;
392			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
393					    QORIQ_CLK_PLL_DIV(4)>;
394			interrupts = <0 33 0x4>; /* Level high type */
395		};
396
397		cluster1_core0_watchdog: wdt@c000000 {
398			compatible = "arm,sp805", "arm,primecell";
399			reg = <0x0 0xc000000 0x0 0x1000>;
400			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
401					    QORIQ_CLK_PLL_DIV(4)>,
402				 <&clockgen QORIQ_CLK_PLATFORM_PLL
403					    QORIQ_CLK_PLL_DIV(4)>;
404			clock-names = "wdog_clk", "apb_pclk";
405		};
406
407		cluster1_core1_watchdog: wdt@c010000 {
408			compatible = "arm,sp805", "arm,primecell";
409			reg = <0x0 0xc010000 0x0 0x1000>;
410			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
411					    QORIQ_CLK_PLL_DIV(4)>,
412				 <&clockgen QORIQ_CLK_PLATFORM_PLL
413					    QORIQ_CLK_PLL_DIV(4)>;
414			clock-names = "wdog_clk", "apb_pclk";
415		};
416
417		cluster2_core0_watchdog: wdt@c100000 {
418			compatible = "arm,sp805", "arm,primecell";
419			reg = <0x0 0xc100000 0x0 0x1000>;
420			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
421					    QORIQ_CLK_PLL_DIV(4)>,
422				 <&clockgen QORIQ_CLK_PLATFORM_PLL
423					    QORIQ_CLK_PLL_DIV(4)>;
424			clock-names = "wdog_clk", "apb_pclk";
425		};
426
427		cluster2_core1_watchdog: wdt@c110000 {
428			compatible = "arm,sp805", "arm,primecell";
429			reg = <0x0 0xc110000 0x0 0x1000>;
430			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
431					    QORIQ_CLK_PLL_DIV(4)>,
432				 <&clockgen QORIQ_CLK_PLATFORM_PLL
433					    QORIQ_CLK_PLL_DIV(4)>;
434			clock-names = "wdog_clk", "apb_pclk";
435		};
436
437		cluster3_core0_watchdog: wdt@c200000 {
438			compatible = "arm,sp805", "arm,primecell";
439			reg = <0x0 0xc200000 0x0 0x1000>;
440			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
441					    QORIQ_CLK_PLL_DIV(4)>,
442				 <&clockgen QORIQ_CLK_PLATFORM_PLL
443					    QORIQ_CLK_PLL_DIV(4)>;
444			clock-names = "wdog_clk", "apb_pclk";
445		};
446
447		cluster3_core1_watchdog: wdt@c210000 {
448			compatible = "arm,sp805", "arm,primecell";
449			reg = <0x0 0xc210000 0x0 0x1000>;
450			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
451					    QORIQ_CLK_PLL_DIV(4)>,
452				 <&clockgen QORIQ_CLK_PLATFORM_PLL
453					    QORIQ_CLK_PLL_DIV(4)>;
454			clock-names = "wdog_clk", "apb_pclk";
455		};
456
457		cluster4_core0_watchdog: wdt@c300000 {
458			compatible = "arm,sp805", "arm,primecell";
459			reg = <0x0 0xc300000 0x0 0x1000>;
460			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
461					    QORIQ_CLK_PLL_DIV(4)>,
462				 <&clockgen QORIQ_CLK_PLATFORM_PLL
463					    QORIQ_CLK_PLL_DIV(4)>;
464			clock-names = "wdog_clk", "apb_pclk";
465		};
466
467		cluster4_core1_watchdog: wdt@c310000 {
468			compatible = "arm,sp805", "arm,primecell";
469			reg = <0x0 0xc310000 0x0 0x1000>;
470			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
471					    QORIQ_CLK_PLL_DIV(4)>,
472				 <&clockgen QORIQ_CLK_PLATFORM_PLL
473					    QORIQ_CLK_PLL_DIV(4)>;
474			clock-names = "wdog_clk", "apb_pclk";
475		};
476
477		crypto: crypto@8000000 {
478			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
479			fsl,sec-era = <8>;
480			#address-cells = <1>;
481			#size-cells = <1>;
482			ranges = <0x0 0x00 0x8000000 0x100000>;
483			reg = <0x00 0x8000000 0x0 0x100000>;
484			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
485			dma-coherent;
486
487			sec_jr0: jr@10000 {
488				compatible = "fsl,sec-v5.0-job-ring",
489					     "fsl,sec-v4.0-job-ring";
490				reg = <0x10000 0x10000>;
491				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
492			};
493
494			sec_jr1: jr@20000 {
495				compatible = "fsl,sec-v5.0-job-ring",
496					     "fsl,sec-v4.0-job-ring";
497				reg = <0x20000 0x10000>;
498				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
499			};
500
501			sec_jr2: jr@30000 {
502				compatible = "fsl,sec-v5.0-job-ring",
503					     "fsl,sec-v4.0-job-ring";
504				reg = <0x30000 0x10000>;
505				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
506			};
507
508			sec_jr3: jr@40000 {
509				compatible = "fsl,sec-v5.0-job-ring",
510					     "fsl,sec-v4.0-job-ring";
511				reg = <0x40000 0x10000>;
512				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
513			};
514		};
515
516		console@8340020 {
517			compatible = "fsl,dpaa2-console";
518			reg = <0x00000000 0x08340020 0 0x2>;
519		};
520
521		ptp-timer@8b95000 {
522			compatible = "fsl,dpaa2-ptp";
523			reg = <0x0 0x8b95000 0x0 0x100>;
524			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
525					    QORIQ_CLK_PLL_DIV(2)>;
526			little-endian;
527			fsl,extts-fifo;
528		};
529
530		emdio1: mdio@8b96000 {
531			compatible = "fsl,fman-memac-mdio";
532			reg = <0x0 0x8b96000 0x0 0x1000>;
533			little-endian;
534			#address-cells = <1>;
535			#size-cells = <0>;
536			clock-frequency = <2500000>;
537			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
538					    QORIQ_CLK_PLL_DIV(2)>;
539			status = "disabled";
540		};
541
542		emdio2: mdio@8b97000 {
543			compatible = "fsl,fman-memac-mdio";
544			reg = <0x0 0x8b97000 0x0 0x1000>;
545			little-endian;
546			#address-cells = <1>;
547			#size-cells = <0>;
548			clock-frequency = <2500000>;
549			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
550					    QORIQ_CLK_PLL_DIV(2)>;
551			status = "disabled";
552		};
553
554		pcs_mdio1: mdio@8c07000 {
555			compatible = "fsl,fman-memac-mdio";
556			reg = <0x0 0x8c07000 0x0 0x1000>;
557			little-endian;
558			#address-cells = <1>;
559			#size-cells = <0>;
560			status = "disabled";
561
562			pcs1: ethernet-phy@0 {
563				reg = <0>;
564			};
565		};
566
567		pcs_mdio2: mdio@8c0b000 {
568			compatible = "fsl,fman-memac-mdio";
569			reg = <0x0 0x8c0b000 0x0 0x1000>;
570			little-endian;
571			#address-cells = <1>;
572			#size-cells = <0>;
573			status = "disabled";
574
575			pcs2: ethernet-phy@0 {
576				reg = <0>;
577			};
578		};
579
580		pcs_mdio3: mdio@8c0f000 {
581			compatible = "fsl,fman-memac-mdio";
582			reg = <0x0 0x8c0f000 0x0 0x1000>;
583			little-endian;
584			#address-cells = <1>;
585			#size-cells = <0>;
586			status = "disabled";
587
588			pcs3: ethernet-phy@0 {
589				reg = <0>;
590			};
591		};
592
593		pcs_mdio4: mdio@8c13000 {
594			compatible = "fsl,fman-memac-mdio";
595			reg = <0x0 0x8c13000 0x0 0x1000>;
596			little-endian;
597			#address-cells = <1>;
598			#size-cells = <0>;
599			status = "disabled";
600
601			pcs4: ethernet-phy@0 {
602				reg = <0>;
603			};
604		};
605
606		pcs_mdio5: mdio@8c17000 {
607			compatible = "fsl,fman-memac-mdio";
608			reg = <0x0 0x8c17000 0x0 0x1000>;
609			little-endian;
610			#address-cells = <1>;
611			#size-cells = <0>;
612			status = "disabled";
613
614			pcs5: ethernet-phy@0 {
615				reg = <0>;
616			};
617		};
618
619		pcs_mdio6: mdio@8c1b000 {
620			compatible = "fsl,fman-memac-mdio";
621			reg = <0x0 0x8c1b000 0x0 0x1000>;
622			little-endian;
623			#address-cells = <1>;
624			#size-cells = <0>;
625			status = "disabled";
626
627			pcs6: ethernet-phy@0 {
628				reg = <0>;
629			};
630		};
631
632		pcs_mdio7: mdio@8c1f000 {
633			compatible = "fsl,fman-memac-mdio";
634			reg = <0x0 0x8c1f000 0x0 0x1000>;
635			little-endian;
636			#address-cells = <1>;
637			#size-cells = <0>;
638			status = "disabled";
639
640			pcs7: ethernet-phy@0 {
641				reg = <0>;
642			};
643		};
644
645		pcs_mdio8: mdio@8c23000 {
646			compatible = "fsl,fman-memac-mdio";
647			reg = <0x0 0x8c23000 0x0 0x1000>;
648			little-endian;
649			#address-cells = <1>;
650			#size-cells = <0>;
651			status = "disabled";
652
653			pcs8: ethernet-phy@0 {
654				reg = <0>;
655			};
656		};
657
658		pcs_mdio9: mdio@8c27000 {
659			compatible = "fsl,fman-memac-mdio";
660			reg = <0x0 0x8c27000 0x0 0x1000>;
661			little-endian;
662			#address-cells = <1>;
663			#size-cells = <0>;
664			status = "disabled";
665
666			pcs9: ethernet-phy@0 {
667				reg = <0>;
668			};
669		};
670
671		pcs_mdio10: mdio@8c2b000 {
672			compatible = "fsl,fman-memac-mdio";
673			reg = <0x0 0x8c2b000 0x0 0x1000>;
674			little-endian;
675			#address-cells = <1>;
676			#size-cells = <0>;
677			status = "disabled";
678
679			pcs10: ethernet-phy@0 {
680				reg = <0>;
681			};
682		};
683
684		pcs_mdio11: mdio@8c2f000 {
685			compatible = "fsl,fman-memac-mdio";
686			reg = <0x0 0x8c2f000 0x0 0x1000>;
687			little-endian;
688			#address-cells = <1>;
689			#size-cells = <0>;
690			status = "disabled";
691
692			pcs11: ethernet-phy@0 {
693				reg = <0>;
694			};
695		};
696
697		pcs_mdio12: mdio@8c33000 {
698			compatible = "fsl,fman-memac-mdio";
699			reg = <0x0 0x8c33000 0x0 0x1000>;
700			little-endian;
701			#address-cells = <1>;
702			#size-cells = <0>;
703			status = "disabled";
704
705			pcs12: ethernet-phy@0 {
706				reg = <0>;
707			};
708		};
709
710		pcs_mdio13: mdio@8c37000 {
711			compatible = "fsl,fman-memac-mdio";
712			reg = <0x0 0x8c37000 0x0 0x1000>;
713			little-endian;
714			#address-cells = <1>;
715			#size-cells = <0>;
716			status = "disabled";
717
718			pcs13: ethernet-phy@0 {
719				reg = <0>;
720			};
721		};
722
723		pcs_mdio14: mdio@8c3b000 {
724			compatible = "fsl,fman-memac-mdio";
725			reg = <0x0 0x8c3b000 0x0 0x1000>;
726			little-endian;
727			#address-cells = <1>;
728			#size-cells = <0>;
729			status = "disabled";
730
731			pcs14: ethernet-phy@0 {
732				reg = <0>;
733			};
734		};
735
736		pcs_mdio15: mdio@8c3f000 {
737			compatible = "fsl,fman-memac-mdio";
738			reg = <0x0 0x8c3f000 0x0 0x1000>;
739			little-endian;
740			#address-cells = <1>;
741			#size-cells = <0>;
742			status = "disabled";
743
744			pcs15: ethernet-phy@0 {
745				reg = <0>;
746			};
747		};
748
749		pcs_mdio16: mdio@8c43000 {
750			compatible = "fsl,fman-memac-mdio";
751			reg = <0x0 0x8c43000 0x0 0x1000>;
752			little-endian;
753			#address-cells = <1>;
754			#size-cells = <0>;
755			status = "disabled";
756
757			pcs16: ethernet-phy@0 {
758				reg = <0>;
759			};
760		};
761
762		fsl_mc: fsl-mc@80c000000 {
763			compatible = "fsl,qoriq-mc";
764			reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
765			      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
766			msi-parent = <&its>;
767			iommu-map = <0 &smmu 0 0>;	/* This is fixed-up by u-boot */
768			dma-coherent;
769			#address-cells = <3>;
770			#size-cells = <1>;
771
772			/*
773			 * Region type 0x0 - MC portals
774			 * Region type 0x1 - QBMAN portals
775			 */
776			ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
777				  0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
778
779			/*
780			 * Define the maximum number of MACs present on the SoC.
781			 */
782			dpmacs {
783				#address-cells = <1>;
784				#size-cells = <0>;
785
786				dpmac1: ethernet@1 {
787					compatible = "fsl,qoriq-mc-dpmac";
788					reg = <0x1>;
789					pcs-handle = <&pcs1>;
790				};
791
792				dpmac2: ethernet@2 {
793					compatible = "fsl,qoriq-mc-dpmac";
794					reg = <0x2>;
795					pcs-handle = <&pcs2>;
796				};
797
798				dpmac3: ethernet@3 {
799					compatible = "fsl,qoriq-mc-dpmac";
800					reg = <0x3>;
801					pcs-handle = <&pcs3>;
802				};
803
804				dpmac4: ethernet@4 {
805					compatible = "fsl,qoriq-mc-dpmac";
806					reg = <0x4>;
807					pcs-handle = <&pcs4>;
808				};
809
810				dpmac5: ethernet@5 {
811					compatible = "fsl,qoriq-mc-dpmac";
812					reg = <0x5>;
813					pcs-handle = <&pcs5>;
814				};
815
816				dpmac6: ethernet@6 {
817					compatible = "fsl,qoriq-mc-dpmac";
818					reg = <0x6>;
819					pcs-handle = <&pcs6>;
820				};
821
822				dpmac7: ethernet@7 {
823					compatible = "fsl,qoriq-mc-dpmac";
824					reg = <0x7>;
825					pcs-handle = <&pcs7>;
826				};
827
828				dpmac8: ethernet@8 {
829					compatible = "fsl,qoriq-mc-dpmac";
830					reg = <0x8>;
831					pcs-handle = <&pcs8>;
832				};
833
834				dpmac9: ethernet@9 {
835					compatible = "fsl,qoriq-mc-dpmac";
836					reg = <0x9>;
837					pcs-handle = <&pcs9>;
838				};
839
840				dpmac10: ethernet@a {
841					compatible = "fsl,qoriq-mc-dpmac";
842					reg = <0xa>;
843					pcs-handle = <&pcs10>;
844				};
845
846				dpmac11: ethernet@b {
847					compatible = "fsl,qoriq-mc-dpmac";
848					reg = <0xb>;
849					pcs-handle = <&pcs11>;
850				};
851
852				dpmac12: ethernet@c {
853					compatible = "fsl,qoriq-mc-dpmac";
854					reg = <0xc>;
855					pcs-handle = <&pcs12>;
856				};
857
858				dpmac13: ethernet@d {
859					compatible = "fsl,qoriq-mc-dpmac";
860					reg = <0xd>;
861					pcs-handle = <&pcs13>;
862				};
863
864				dpmac14: ethernet@e {
865					compatible = "fsl,qoriq-mc-dpmac";
866					reg = <0xe>;
867					pcs-handle = <&pcs14>;
868				};
869
870				dpmac15: ethernet@f {
871					compatible = "fsl,qoriq-mc-dpmac";
872					reg = <0xf>;
873					pcs-handle = <&pcs15>;
874				};
875
876				dpmac16: ethernet@10 {
877					compatible = "fsl,qoriq-mc-dpmac";
878					reg = <0x10>;
879					pcs-handle = <&pcs16>;
880				};
881			};
882		};
883
884		smmu: iommu@5000000 {
885			compatible = "arm,mmu-500";
886			reg = <0 0x5000000 0 0x800000>;
887			#global-interrupts = <12>;
888			#iommu-cells = <1>;
889			stream-match-mask = <0x7C00>;
890			dma-coherent;
891			interrupts = <0 13 4>, /* global secure fault */
892				     <0 14 4>, /* combined secure interrupt */
893				     <0 15 4>, /* global non-secure fault */
894				     <0 16 4>, /* combined non-secure interrupt */
895				/* performance counter interrupts 0-7 */
896				     <0 211 4>, <0 212 4>,
897				     <0 213 4>, <0 214 4>,
898				     <0 215 4>, <0 216 4>,
899				     <0 217 4>, <0 218 4>,
900				/* per context interrupt, 64 interrupts */
901				     <0 146 4>, <0 147 4>,
902				     <0 148 4>, <0 149 4>,
903				     <0 150 4>, <0 151 4>,
904				     <0 152 4>, <0 153 4>,
905				     <0 154 4>, <0 155 4>,
906				     <0 156 4>, <0 157 4>,
907				     <0 158 4>, <0 159 4>,
908				     <0 160 4>, <0 161 4>,
909				     <0 162 4>, <0 163 4>,
910				     <0 164 4>, <0 165 4>,
911				     <0 166 4>, <0 167 4>,
912				     <0 168 4>, <0 169 4>,
913				     <0 170 4>, <0 171 4>,
914				     <0 172 4>, <0 173 4>,
915				     <0 174 4>, <0 175 4>,
916				     <0 176 4>, <0 177 4>,
917				     <0 178 4>, <0 179 4>,
918				     <0 180 4>, <0 181 4>,
919				     <0 182 4>, <0 183 4>,
920				     <0 184 4>, <0 185 4>,
921				     <0 186 4>, <0 187 4>,
922				     <0 188 4>, <0 189 4>,
923				     <0 190 4>, <0 191 4>,
924				     <0 192 4>, <0 193 4>,
925				     <0 194 4>, <0 195 4>,
926				     <0 196 4>, <0 197 4>,
927				     <0 198 4>, <0 199 4>,
928				     <0 200 4>, <0 201 4>,
929				     <0 202 4>, <0 203 4>,
930				     <0 204 4>, <0 205 4>,
931				     <0 206 4>, <0 207 4>,
932				     <0 208 4>, <0 209 4>;
933		};
934
935		dspi: spi@2100000 {
936			status = "disabled";
937			compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
938			#address-cells = <1>;
939			#size-cells = <0>;
940			reg = <0x0 0x2100000 0x0 0x10000>;
941			interrupts = <0 26 0x4>; /* Level high type */
942			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
943					    QORIQ_CLK_PLL_DIV(4)>;
944			clock-names = "dspi";
945			spi-num-chipselects = <5>;
946		};
947
948		esdhc: esdhc@2140000 {
949			status = "disabled";
950			compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
951			reg = <0x0 0x2140000 0x0 0x10000>;
952			interrupts = <0 28 0x4>; /* Level high type */
953			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
954					    QORIQ_CLK_PLL_DIV(2)>;
955			voltage-ranges = <1800 1800 3300 3300>;
956			sdhci,auto-cmd12;
957			little-endian;
958			bus-width = <4>;
959		};
960
961		gpio0: gpio@2300000 {
962			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
963			reg = <0x0 0x2300000 0x0 0x10000>;
964			interrupts = <0 36 0x4>; /* Level high type */
965			gpio-controller;
966			little-endian;
967			#gpio-cells = <2>;
968			interrupt-controller;
969			#interrupt-cells = <2>;
970		};
971
972		gpio1: gpio@2310000 {
973			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
974			reg = <0x0 0x2310000 0x0 0x10000>;
975			interrupts = <0 36 0x4>; /* Level high type */
976			gpio-controller;
977			little-endian;
978			#gpio-cells = <2>;
979			interrupt-controller;
980			#interrupt-cells = <2>;
981		};
982
983		gpio2: gpio@2320000 {
984			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
985			reg = <0x0 0x2320000 0x0 0x10000>;
986			interrupts = <0 37 0x4>; /* Level high type */
987			gpio-controller;
988			little-endian;
989			#gpio-cells = <2>;
990			interrupt-controller;
991			#interrupt-cells = <2>;
992		};
993
994		gpio3: gpio@2330000 {
995			compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
996			reg = <0x0 0x2330000 0x0 0x10000>;
997			interrupts = <0 37 0x4>; /* Level high type */
998			gpio-controller;
999			little-endian;
1000			#gpio-cells = <2>;
1001			interrupt-controller;
1002			#interrupt-cells = <2>;
1003		};
1004
1005		i2c0: i2c@2000000 {
1006			status = "disabled";
1007			compatible = "fsl,vf610-i2c";
1008			#address-cells = <1>;
1009			#size-cells = <0>;
1010			reg = <0x0 0x2000000 0x0 0x10000>;
1011			interrupts = <0 34 0x4>; /* Level high type */
1012			clock-names = "i2c";
1013			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1014					    QORIQ_CLK_PLL_DIV(4)>;
1015		};
1016
1017		i2c1: i2c@2010000 {
1018			status = "disabled";
1019			compatible = "fsl,vf610-i2c";
1020			#address-cells = <1>;
1021			#size-cells = <0>;
1022			reg = <0x0 0x2010000 0x0 0x10000>;
1023			interrupts = <0 34 0x4>; /* Level high type */
1024			clock-names = "i2c";
1025			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1026					    QORIQ_CLK_PLL_DIV(4)>;
1027		};
1028
1029		i2c2: i2c@2020000 {
1030			status = "disabled";
1031			compatible = "fsl,vf610-i2c";
1032			#address-cells = <1>;
1033			#size-cells = <0>;
1034			reg = <0x0 0x2020000 0x0 0x10000>;
1035			interrupts = <0 35 0x4>; /* Level high type */
1036			clock-names = "i2c";
1037			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1038					    QORIQ_CLK_PLL_DIV(4)>;
1039		};
1040
1041		i2c3: i2c@2030000 {
1042			status = "disabled";
1043			compatible = "fsl,vf610-i2c";
1044			#address-cells = <1>;
1045			#size-cells = <0>;
1046			reg = <0x0 0x2030000 0x0 0x10000>;
1047			interrupts = <0 35 0x4>; /* Level high type */
1048			clock-names = "i2c";
1049			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1050					    QORIQ_CLK_PLL_DIV(4)>;
1051		};
1052
1053		ifc: memory-controller@2240000 {
1054			compatible = "fsl,ifc";
1055			reg = <0x0 0x2240000 0x0 0x20000>;
1056			interrupts = <0 21 0x4>; /* Level high type */
1057			little-endian;
1058			#address-cells = <2>;
1059			#size-cells = <1>;
1060
1061			ranges = <0 0 0x5 0x80000000 0x08000000
1062				  2 0 0x5 0x30000000 0x00010000
1063				  3 0 0x5 0x20000000 0x00010000>;
1064		};
1065
1066		qspi: spi@20c0000 {
1067			compatible = "fsl,ls2080a-qspi";
1068			#address-cells = <1>;
1069			#size-cells = <0>;
1070			reg = <0x0 0x20c0000 0x0 0x10000>,
1071			      <0x0 0x20000000 0x0 0x10000000>;
1072			reg-names = "QuadSPI", "QuadSPI-memory";
1073			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1074			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1075					    QORIQ_CLK_PLL_DIV(4)>,
1076				 <&clockgen QORIQ_CLK_PLATFORM_PLL
1077					    QORIQ_CLK_PLL_DIV(4)>;
1078			clock-names = "qspi_en", "qspi";
1079			status = "disabled";
1080		};
1081
1082		pcie1: pcie@3400000 {
1083			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1084			reg-names = "regs", "config";
1085			interrupts = <0 108 0x4>; /* Level high type */
1086			interrupt-names = "intr";
1087			#address-cells = <3>;
1088			#size-cells = <2>;
1089			device_type = "pci";
1090			dma-coherent;
1091			num-viewport = <6>;
1092			bus-range = <0x0 0xff>;
1093			msi-parent = <&its>;
1094			#interrupt-cells = <1>;
1095			interrupt-map-mask = <0 0 0 7>;
1096			interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1097					<0000 0 0 2 &gic 0 0 0 110 4>,
1098					<0000 0 0 3 &gic 0 0 0 111 4>,
1099					<0000 0 0 4 &gic 0 0 0 112 4>;
1100			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1101			status = "disabled";
1102		};
1103
1104		pcie2: pcie@3500000 {
1105			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1106			reg-names = "regs", "config";
1107			interrupts = <0 113 0x4>; /* Level high type */
1108			interrupt-names = "intr";
1109			#address-cells = <3>;
1110			#size-cells = <2>;
1111			device_type = "pci";
1112			dma-coherent;
1113			num-viewport = <6>;
1114			bus-range = <0x0 0xff>;
1115			msi-parent = <&its>;
1116			#interrupt-cells = <1>;
1117			interrupt-map-mask = <0 0 0 7>;
1118			interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1119					<0000 0 0 2 &gic 0 0 0 115 4>,
1120					<0000 0 0 3 &gic 0 0 0 116 4>,
1121					<0000 0 0 4 &gic 0 0 0 117 4>;
1122			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1123			status = "disabled";
1124		};
1125
1126		pcie3: pcie@3600000 {
1127			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1128			reg-names = "regs", "config";
1129			interrupts = <0 118 0x4>; /* Level high type */
1130			interrupt-names = "intr";
1131			#address-cells = <3>;
1132			#size-cells = <2>;
1133			device_type = "pci";
1134			dma-coherent;
1135			num-viewport = <256>;
1136			bus-range = <0x0 0xff>;
1137			msi-parent = <&its>;
1138			#interrupt-cells = <1>;
1139			interrupt-map-mask = <0 0 0 7>;
1140			interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1141					<0000 0 0 2 &gic 0 0 0 120 4>,
1142					<0000 0 0 3 &gic 0 0 0 121 4>,
1143					<0000 0 0 4 &gic 0 0 0 122 4>;
1144			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1145			status = "disabled";
1146		};
1147
1148		pcie4: pcie@3700000 {
1149			compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
1150			reg-names = "regs", "config";
1151			interrupts = <0 123 0x4>; /* Level high type */
1152			interrupt-names = "intr";
1153			#address-cells = <3>;
1154			#size-cells = <2>;
1155			device_type = "pci";
1156			dma-coherent;
1157			num-viewport = <6>;
1158			bus-range = <0x0 0xff>;
1159			msi-parent = <&its>;
1160			#interrupt-cells = <1>;
1161			interrupt-map-mask = <0 0 0 7>;
1162			interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1163					<0000 0 0 2 &gic 0 0 0 125 4>,
1164					<0000 0 0 3 &gic 0 0 0 126 4>,
1165					<0000 0 0 4 &gic 0 0 0 127 4>;
1166			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1167			status = "disabled";
1168		};
1169
1170		sata0: sata@3200000 {
1171			status = "disabled";
1172			compatible = "fsl,ls2080a-ahci";
1173			reg = <0x0 0x3200000 0x0 0x10000>;
1174			interrupts = <0 133 0x4>; /* Level high type */
1175			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1176					    QORIQ_CLK_PLL_DIV(4)>;
1177			dma-coherent;
1178		};
1179
1180		sata1: sata@3210000 {
1181			status = "disabled";
1182			compatible = "fsl,ls2080a-ahci";
1183			reg = <0x0 0x3210000 0x0 0x10000>;
1184			interrupts = <0 136 0x4>; /* Level high type */
1185			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1186					    QORIQ_CLK_PLL_DIV(4)>;
1187			dma-coherent;
1188		};
1189
1190		bus: bus {
1191			#address-cells = <2>;
1192			#size-cells = <2>;
1193			compatible = "simple-bus";
1194			ranges;
1195			dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
1196
1197			usb0: usb@3100000 {
1198				compatible = "snps,dwc3";
1199				reg = <0x0 0x3100000 0x0 0x10000>;
1200				interrupts = <0 80 0x4>; /* Level high type */
1201				dr_mode = "host";
1202				snps,quirk-frame-length-adjustment = <0x20>;
1203				snps,dis_rxdet_inp3_quirk;
1204				snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1205				status = "disabled";
1206			};
1207
1208			usb1: usb@3110000 {
1209				compatible = "snps,dwc3";
1210				reg = <0x0 0x3110000 0x0 0x10000>;
1211				interrupts = <0 81 0x4>; /* Level high type */
1212				dr_mode = "host";
1213				snps,quirk-frame-length-adjustment = <0x20>;
1214				snps,dis_rxdet_inp3_quirk;
1215				snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1216				status = "disabled";
1217			};
1218		};
1219
1220		ccn@4000000 {
1221			compatible = "arm,ccn-504";
1222			reg = <0x0 0x04000000 0x0 0x01000000>;
1223			interrupts = <0 12 4>;
1224		};
1225
1226		rcpm: power-controller@1e34040 {
1227			compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
1228			reg = <0x0 0x1e34040 0x0 0x18>;
1229			#fsl,rcpm-wakeup-cells = <6>;
1230			little-endian;
1231		};
1232
1233		ftm_alarm0: timer@2800000 {
1234			compatible = "fsl,ls208xa-ftm-alarm";
1235			reg = <0x0 0x2800000 0x0 0x10000>;
1236			fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1237			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1238		};
1239	};
1240
1241	ddr1: memory-controller@1080000 {
1242		compatible = "fsl,qoriq-memory-controller";
1243		reg = <0x0 0x1080000 0x0 0x1000>;
1244		interrupts = <0 17 0x4>;
1245		little-endian;
1246	};
1247
1248	ddr2: memory-controller@1090000 {
1249		compatible = "fsl,qoriq-memory-controller";
1250		reg = <0x0 0x1090000 0x0 0x1000>;
1251		interrupts = <0 18 0x4>;
1252		little-endian;
1253	};
1254
1255	firmware {
1256		optee {
1257			compatible = "linaro,optee-tz";
1258			method = "smc";
1259		};
1260	};
1261};
1262