1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree file for Freescale LS2080A QDS Board. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2017 NXP 7 * 8 * Abhimanyu Saini <abhimanyu.saini@nxp.com> 9 * 10 */ 11 12&esdhc { 13 mmc-hs200-1_8v; 14 status = "okay"; 15}; 16 17&ifc { 18 status = "okay"; 19 #address-cells = <2>; 20 #size-cells = <1>; 21 ranges = <0x0 0x0 0x5 0x80000000 0x08000000 22 0x2 0x0 0x5 0x30000000 0x00010000 23 0x3 0x0 0x5 0x20000000 0x00010000>; 24 25 nor@0,0 { 26 #address-cells = <1>; 27 #size-cells = <1>; 28 compatible = "cfi-flash"; 29 reg = <0x0 0x0 0x8000000>; 30 bank-width = <2>; 31 device-width = <1>; 32 }; 33 34 nand@2,0 { 35 compatible = "fsl,ifc-nand"; 36 reg = <0x2 0x0 0x10000>; 37 }; 38 39 cpld@3,0 { 40 reg = <0x3 0x0 0x10000>; 41 compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis"; 42 }; 43}; 44 45&i2c0 { 46 status = "okay"; 47 pca9547@77 { 48 compatible = "nxp,pca9547"; 49 reg = <0x77>; 50 #address-cells = <1>; 51 #size-cells = <0>; 52 i2c@0 { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 reg = <0x00>; 56 rtc@68 { 57 compatible = "dallas,ds3232"; 58 reg = <0x68>; 59 }; 60 }; 61 62 i2c@2 { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 reg = <0x02>; 66 67 ina220@40 { 68 compatible = "ti,ina220"; 69 reg = <0x40>; 70 shunt-resistor = <500>; 71 }; 72 73 ina220@41 { 74 compatible = "ti,ina220"; 75 reg = <0x41>; 76 shunt-resistor = <1000>; 77 }; 78 }; 79 80 i2c@3 { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 reg = <0x3>; 84 85 adt7481@4c { 86 compatible = "adi,adt7461"; 87 reg = <0x4c>; 88 }; 89 }; 90 }; 91}; 92 93&i2c1 { 94 status = "disabled"; 95}; 96 97&i2c2 { 98 status = "disabled"; 99}; 100 101&i2c3 { 102 status = "disabled"; 103}; 104 105&dspi { 106 status = "okay"; 107 dflash0: n25q128a@0 { 108 #address-cells = <1>; 109 #size-cells = <1>; 110 compatible = "st,m25p80"; 111 spi-max-frequency = <3000000>; 112 reg = <0>; 113 }; 114 dflash1: sst25wf040b@1 { 115 #address-cells = <1>; 116 #size-cells = <1>; 117 compatible = "st,m25p80"; 118 spi-max-frequency = <3000000>; 119 reg = <1>; 120 }; 121 dflash2: en25s64@2 { 122 #address-cells = <1>; 123 #size-cells = <1>; 124 compatible = "st,m25p80"; 125 spi-max-frequency = <3000000>; 126 reg = <2>; 127 }; 128}; 129 130&qspi { 131 status = "okay"; 132 flash0: s25fl256s1@0 { 133 #address-cells = <1>; 134 #size-cells = <1>; 135 compatible = "st,m25p80"; 136 spi-max-frequency = <20000000>; 137 spi-rx-bus-width = <4>; 138 spi-tx-bus-width = <4>; 139 reg = <0>; 140 }; 141 flash2: s25fl256s1@2 { 142 #address-cells = <1>; 143 #size-cells = <1>; 144 compatible = "st,m25p80"; 145 spi-max-frequency = <20000000>; 146 spi-rx-bus-width = <4>; 147 spi-tx-bus-width = <4>; 148 reg = <2>; 149 }; 150}; 151 152&sata0 { 153 status = "okay"; 154}; 155 156&sata1 { 157 status = "okay"; 158}; 159 160&usb0 { 161 status = "okay"; 162}; 163 164&usb1 { 165 status = "okay"; 166}; 167