1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 4 * 5 * Copyright 2014-2016 Freescale Semiconductor, Inc. 6 * 7 * Abhimanyu Saini <abhimanyu.saini@nxp.com> 8 * Bhupesh Sharma <bhupesh.sharma@freescale.com> 9 * 10 */ 11 12#include "fsl-ls208xa.dtsi" 13 14&cpu { 15 cpu0: cpu@0 { 16 device_type = "cpu"; 17 compatible = "arm,cortex-a57"; 18 reg = <0x0>; 19 clocks = <&clockgen 1 0>; 20 cpu-idle-states = <&CPU_PW20>; 21 next-level-cache = <&cluster0_l2>; 22 #cooling-cells = <2>; 23 }; 24 25 cpu1: cpu@1 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a57"; 28 reg = <0x1>; 29 clocks = <&clockgen 1 0>; 30 cpu-idle-states = <&CPU_PW20>; 31 next-level-cache = <&cluster0_l2>; 32 #cooling-cells = <2>; 33 }; 34 35 cpu2: cpu@100 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a57"; 38 reg = <0x100>; 39 clocks = <&clockgen 1 1>; 40 cpu-idle-states = <&CPU_PW20>; 41 next-level-cache = <&cluster1_l2>; 42 #cooling-cells = <2>; 43 }; 44 45 cpu3: cpu@101 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a57"; 48 reg = <0x101>; 49 clocks = <&clockgen 1 1>; 50 cpu-idle-states = <&CPU_PW20>; 51 next-level-cache = <&cluster1_l2>; 52 #cooling-cells = <2>; 53 }; 54 55 cpu4: cpu@200 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a57"; 58 reg = <0x200>; 59 clocks = <&clockgen 1 2>; 60 cpu-idle-states = <&CPU_PW20>; 61 next-level-cache = <&cluster2_l2>; 62 #cooling-cells = <2>; 63 }; 64 65 cpu5: cpu@201 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a57"; 68 reg = <0x201>; 69 clocks = <&clockgen 1 2>; 70 cpu-idle-states = <&CPU_PW20>; 71 next-level-cache = <&cluster2_l2>; 72 #cooling-cells = <2>; 73 }; 74 75 cpu6: cpu@300 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a57"; 78 reg = <0x300>; 79 clocks = <&clockgen 1 3>; 80 next-level-cache = <&cluster3_l2>; 81 cpu-idle-states = <&CPU_PW20>; 82 #cooling-cells = <2>; 83 }; 84 85 cpu7: cpu@301 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a57"; 88 reg = <0x301>; 89 clocks = <&clockgen 1 3>; 90 cpu-idle-states = <&CPU_PW20>; 91 next-level-cache = <&cluster3_l2>; 92 #cooling-cells = <2>; 93 }; 94 95 cluster0_l2: l2-cache0 { 96 compatible = "cache"; 97 }; 98 99 cluster1_l2: l2-cache1 { 100 compatible = "cache"; 101 }; 102 103 cluster2_l2: l2-cache2 { 104 compatible = "cache"; 105 }; 106 107 cluster3_l2: l2-cache3 { 108 compatible = "cache"; 109 }; 110 111 CPU_PW20: cpu-pw20 { 112 compatible = "arm,idle-state"; 113 idle-state-name = "PW20"; 114 arm,psci-suspend-param = <0x00010000>; 115 entry-latency-us = <2000>; 116 exit-latency-us = <2000>; 117 min-residency-us = <6000>; 118 }; 119}; 120 121&pcie1 { 122 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 123 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ 124 125 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ 126 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 127}; 128 129&pcie2 { 130 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 131 0x12 0x00000000 0x0 0x00002000>; /* configuration space */ 132 133 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ 134 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 135}; 136 137&pcie3 { 138 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 139 0x14 0x00000000 0x0 0x00002000>; /* configuration space */ 140 141 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ 142 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 143}; 144 145&pcie4 { 146 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 147 0x16 0x00000000 0x0 0x00002000>; /* configuration space */ 148 149 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ 150 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 151}; 152