1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 4 * 5 * Copyright 2014-2016 Freescale Semiconductor, Inc. 6 * 7 * Abhimanyu Saini <abhimanyu.saini@nxp.com> 8 * Bhupesh Sharma <bhupesh.sharma@freescale.com> 9 * 10 */ 11 12#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 13#include "fsl-ls208xa.dtsi" 14 15&cpu { 16 cpu0: cpu@0 { 17 device_type = "cpu"; 18 compatible = "arm,cortex-a57"; 19 reg = <0x0>; 20 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 21 cpu-idle-states = <&CPU_PW20>; 22 next-level-cache = <&cluster0_l2>; 23 #cooling-cells = <2>; 24 }; 25 26 cpu1: cpu@1 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a57"; 29 reg = <0x1>; 30 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 31 cpu-idle-states = <&CPU_PW20>; 32 next-level-cache = <&cluster0_l2>; 33 #cooling-cells = <2>; 34 }; 35 36 cpu2: cpu@100 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a57"; 39 reg = <0x100>; 40 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 41 cpu-idle-states = <&CPU_PW20>; 42 next-level-cache = <&cluster1_l2>; 43 #cooling-cells = <2>; 44 }; 45 46 cpu3: cpu@101 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a57"; 49 reg = <0x101>; 50 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 51 cpu-idle-states = <&CPU_PW20>; 52 next-level-cache = <&cluster1_l2>; 53 #cooling-cells = <2>; 54 }; 55 56 cpu4: cpu@200 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a57"; 59 reg = <0x200>; 60 clocks = <&clockgen QORIQ_CLK_CMUX 2>; 61 cpu-idle-states = <&CPU_PW20>; 62 next-level-cache = <&cluster2_l2>; 63 #cooling-cells = <2>; 64 }; 65 66 cpu5: cpu@201 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a57"; 69 reg = <0x201>; 70 clocks = <&clockgen QORIQ_CLK_CMUX 2>; 71 cpu-idle-states = <&CPU_PW20>; 72 next-level-cache = <&cluster2_l2>; 73 #cooling-cells = <2>; 74 }; 75 76 cpu6: cpu@300 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a57"; 79 reg = <0x300>; 80 clocks = <&clockgen QORIQ_CLK_CMUX 3>; 81 next-level-cache = <&cluster3_l2>; 82 cpu-idle-states = <&CPU_PW20>; 83 #cooling-cells = <2>; 84 }; 85 86 cpu7: cpu@301 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a57"; 89 reg = <0x301>; 90 clocks = <&clockgen QORIQ_CLK_CMUX 3>; 91 cpu-idle-states = <&CPU_PW20>; 92 next-level-cache = <&cluster3_l2>; 93 #cooling-cells = <2>; 94 }; 95 96 cluster0_l2: l2-cache0 { 97 compatible = "cache"; 98 cache-level = <2>; 99 cache-unified; 100 }; 101 102 cluster1_l2: l2-cache1 { 103 compatible = "cache"; 104 cache-level = <2>; 105 cache-unified; 106 }; 107 108 cluster2_l2: l2-cache2 { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 }; 113 114 cluster3_l2: l2-cache3 { 115 compatible = "cache"; 116 cache-level = <2>; 117 cache-unified; 118 }; 119 120 CPU_PW20: cpu-pw20 { 121 compatible = "arm,idle-state"; 122 idle-state-name = "PW20"; 123 arm,psci-suspend-param = <0x00010000>; 124 entry-latency-us = <2000>; 125 exit-latency-us = <2000>; 126 min-residency-us = <6000>; 127 }; 128}; 129 130&pcie1 { 131 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 132 <0x10 0x00000000 0x0 0x00002000>; /* configuration space */ 133 134 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ 135 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 136}; 137 138&pcie2 { 139 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 140 <0x12 0x00000000 0x0 0x00002000>; /* configuration space */ 141 142 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ 143 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 144}; 145 146&pcie3 { 147 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 148 <0x14 0x00000000 0x0 0x00002000>; /* configuration space */ 149 150 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ 151 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 152}; 153 154&pcie4 { 155 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ 156 <0x16 0x00000000 0x0 0x00002000>; /* configuration space */ 157 158 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ 159 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 160}; 161 162&timer { 163 fsl,erratum-a008585; 164}; 165