1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1088A family SoC. 4 * 5 * Copyright 2017 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 compatible = "fsl,ls1088a"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 crypto = &crypto; 21 rtc1 = &ftm_alarm0; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 /* We have 2 clusters having 4 Cortex-A53 cores each */ 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a53"; 32 reg = <0x0>; 33 clocks = <&clockgen 1 0>; 34 cpu-idle-states = <&CPU_PH20>; 35 #cooling-cells = <2>; 36 }; 37 38 cpu1: cpu@1 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x1>; 42 clocks = <&clockgen 1 0>; 43 cpu-idle-states = <&CPU_PH20>; 44 #cooling-cells = <2>; 45 }; 46 47 cpu2: cpu@2 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a53"; 50 reg = <0x2>; 51 clocks = <&clockgen 1 0>; 52 cpu-idle-states = <&CPU_PH20>; 53 #cooling-cells = <2>; 54 }; 55 56 cpu3: cpu@3 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53"; 59 reg = <0x3>; 60 clocks = <&clockgen 1 0>; 61 cpu-idle-states = <&CPU_PH20>; 62 #cooling-cells = <2>; 63 }; 64 65 cpu4: cpu@100 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53"; 68 reg = <0x100>; 69 clocks = <&clockgen 1 1>; 70 cpu-idle-states = <&CPU_PH20>; 71 #cooling-cells = <2>; 72 }; 73 74 cpu5: cpu@101 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x101>; 78 clocks = <&clockgen 1 1>; 79 cpu-idle-states = <&CPU_PH20>; 80 #cooling-cells = <2>; 81 }; 82 83 cpu6: cpu@102 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a53"; 86 reg = <0x102>; 87 clocks = <&clockgen 1 1>; 88 cpu-idle-states = <&CPU_PH20>; 89 #cooling-cells = <2>; 90 }; 91 92 cpu7: cpu@103 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53"; 95 reg = <0x103>; 96 clocks = <&clockgen 1 1>; 97 cpu-idle-states = <&CPU_PH20>; 98 #cooling-cells = <2>; 99 }; 100 101 CPU_PH20: cpu-ph20 { 102 compatible = "arm,idle-state"; 103 idle-state-name = "PH20"; 104 arm,psci-suspend-param = <0x0>; 105 entry-latency-us = <1000>; 106 exit-latency-us = <1000>; 107 min-residency-us = <3000>; 108 }; 109 }; 110 111 gic: interrupt-controller@6000000 { 112 compatible = "arm,gic-v3"; 113 #interrupt-cells = <3>; 114 interrupt-controller; 115 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 116 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ 117 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 118 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 119 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 120 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; 121 #address-cells = <2>; 122 #size-cells = <2>; 123 ranges; 124 125 its: gic-its@6020000 { 126 compatible = "arm,gic-v3-its"; 127 msi-controller; 128 reg = <0x0 0x6020000 0 0x20000>; 129 }; 130 }; 131 132 thermal-zones { 133 cpu_thermal: cpu-thermal { 134 polling-delay-passive = <1000>; 135 polling-delay = <5000>; 136 thermal-sensors = <&tmu 0>; 137 138 trips { 139 cpu_alert: cpu-alert { 140 temperature = <85000>; 141 hysteresis = <2000>; 142 type = "passive"; 143 }; 144 145 cpu_crit: cpu-crit { 146 temperature = <95000>; 147 hysteresis = <2000>; 148 type = "critical"; 149 }; 150 }; 151 152 cooling-maps { 153 map0 { 154 trip = <&cpu_alert>; 155 cooling-device = 156 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 157 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 158 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 159 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 160 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 161 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 162 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 163 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 164 }; 165 }; 166 }; 167 }; 168 169 timer { 170 compatible = "arm,armv8-timer"; 171 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 172 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 173 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 174 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 175 }; 176 177 psci { 178 compatible = "arm,psci-0.2"; 179 method = "smc"; 180 }; 181 182 sysclk: sysclk { 183 compatible = "fixed-clock"; 184 #clock-cells = <0>; 185 clock-frequency = <100000000>; 186 clock-output-names = "sysclk"; 187 }; 188 189 soc { 190 compatible = "simple-bus"; 191 #address-cells = <2>; 192 #size-cells = <2>; 193 ranges; 194 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 195 196 clockgen: clocking@1300000 { 197 compatible = "fsl,ls1088a-clockgen"; 198 reg = <0 0x1300000 0 0xa0000>; 199 #clock-cells = <2>; 200 clocks = <&sysclk>; 201 }; 202 203 dcfg: dcfg@1e00000 { 204 compatible = "fsl,ls1088a-dcfg", "syscon"; 205 reg = <0x0 0x1e00000 0x0 0x10000>; 206 little-endian; 207 }; 208 209 tmu: tmu@1f80000 { 210 compatible = "fsl,qoriq-tmu"; 211 reg = <0x0 0x1f80000 0x0 0x10000>; 212 interrupts = <0 23 0x4>; 213 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 214 fsl,tmu-calibration = 215 /* Calibration data group 1 */ 216 <0x00000000 0x00000026 217 0x00000001 0x0000002d 218 0x00000002 0x00000032 219 0x00000003 0x00000039 220 0x00000004 0x0000003f 221 0x00000005 0x00000046 222 0x00000006 0x0000004d 223 0x00000007 0x00000054 224 0x00000008 0x0000005a 225 0x00000009 0x00000061 226 0x0000000a 0x0000006a 227 0x0000000b 0x00000071 228 /* Calibration data group 2 */ 229 0x00010000 0x00000025 230 0x00010001 0x0000002c 231 0x00010002 0x00000035 232 0x00010003 0x0000003d 233 0x00010004 0x00000045 234 0x00010005 0x0000004e 235 0x00010006 0x00000057 236 0x00010007 0x00000061 237 0x00010008 0x0000006b 238 0x00010009 0x00000076 239 /* Calibration data group 3 */ 240 0x00020000 0x00000029 241 0x00020001 0x00000033 242 0x00020002 0x0000003d 243 0x00020003 0x00000049 244 0x00020004 0x00000056 245 0x00020005 0x00000061 246 0x00020006 0x0000006d 247 /* Calibration data group 4 */ 248 0x00030000 0x00000021 249 0x00030001 0x0000002a 250 0x00030002 0x0000003c 251 0x00030003 0x0000004e>; 252 little-endian; 253 #thermal-sensor-cells = <1>; 254 }; 255 256 dspi: spi@2100000 { 257 compatible = "fsl,ls1088a-dspi", 258 "fsl,ls1021a-v1.0-dspi"; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 reg = <0x0 0x2100000 0x0 0x10000>; 262 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 263 clock-names = "dspi"; 264 clocks = <&clockgen 4 1>; 265 spi-num-chipselects = <6>; 266 status = "disabled"; 267 }; 268 269 duart0: serial@21c0500 { 270 compatible = "fsl,ns16550", "ns16550a"; 271 reg = <0x0 0x21c0500 0x0 0x100>; 272 clocks = <&clockgen 4 3>; 273 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 274 status = "disabled"; 275 }; 276 277 duart1: serial@21c0600 { 278 compatible = "fsl,ns16550", "ns16550a"; 279 reg = <0x0 0x21c0600 0x0 0x100>; 280 clocks = <&clockgen 4 3>; 281 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 282 status = "disabled"; 283 }; 284 285 gpio0: gpio@2300000 { 286 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 287 reg = <0x0 0x2300000 0x0 0x10000>; 288 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 289 little-endian; 290 gpio-controller; 291 #gpio-cells = <2>; 292 interrupt-controller; 293 #interrupt-cells = <2>; 294 }; 295 296 gpio1: gpio@2310000 { 297 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 298 reg = <0x0 0x2310000 0x0 0x10000>; 299 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 300 little-endian; 301 gpio-controller; 302 #gpio-cells = <2>; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 }; 306 307 gpio2: gpio@2320000 { 308 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 309 reg = <0x0 0x2320000 0x0 0x10000>; 310 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 311 little-endian; 312 gpio-controller; 313 #gpio-cells = <2>; 314 interrupt-controller; 315 #interrupt-cells = <2>; 316 }; 317 318 gpio3: gpio@2330000 { 319 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 320 reg = <0x0 0x2330000 0x0 0x10000>; 321 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 322 little-endian; 323 gpio-controller; 324 #gpio-cells = <2>; 325 interrupt-controller; 326 #interrupt-cells = <2>; 327 }; 328 329 ifc: ifc@2240000 { 330 compatible = "fsl,ifc", "simple-bus"; 331 reg = <0x0 0x2240000 0x0 0x20000>; 332 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 333 little-endian; 334 #address-cells = <2>; 335 #size-cells = <1>; 336 status = "disabled"; 337 }; 338 339 i2c0: i2c@2000000 { 340 compatible = "fsl,vf610-i2c"; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 reg = <0x0 0x2000000 0x0 0x10000>; 344 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clockgen 4 7>; 346 status = "disabled"; 347 }; 348 349 i2c1: i2c@2010000 { 350 compatible = "fsl,vf610-i2c"; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 reg = <0x0 0x2010000 0x0 0x10000>; 354 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&clockgen 4 7>; 356 status = "disabled"; 357 }; 358 359 i2c2: i2c@2020000 { 360 compatible = "fsl,vf610-i2c"; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 reg = <0x0 0x2020000 0x0 0x10000>; 364 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&clockgen 4 7>; 366 status = "disabled"; 367 }; 368 369 i2c3: i2c@2030000 { 370 compatible = "fsl,vf610-i2c"; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 reg = <0x0 0x2030000 0x0 0x10000>; 374 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&clockgen 4 7>; 376 status = "disabled"; 377 }; 378 379 qspi: spi@20c0000 { 380 compatible = "fsl,ls2080a-qspi"; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 reg = <0x0 0x20c0000 0x0 0x10000>, 384 <0x0 0x20000000 0x0 0x10000000>; 385 reg-names = "QuadSPI", "QuadSPI-memory"; 386 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 387 clock-names = "qspi_en", "qspi"; 388 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 389 status = "disabled"; 390 }; 391 392 esdhc: esdhc@2140000 { 393 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; 394 reg = <0x0 0x2140000 0x0 0x10000>; 395 interrupts = <0 28 0x4>; /* Level high type */ 396 clock-frequency = <0>; 397 clocks = <&clockgen 2 1>; 398 voltage-ranges = <1800 1800 3300 3300>; 399 sdhci,auto-cmd12; 400 little-endian; 401 bus-width = <4>; 402 status = "disabled"; 403 }; 404 405 usb0: usb3@3100000 { 406 compatible = "snps,dwc3"; 407 reg = <0x0 0x3100000 0x0 0x10000>; 408 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 409 dr_mode = "host"; 410 snps,quirk-frame-length-adjustment = <0x20>; 411 snps,dis_rxdet_inp3_quirk; 412 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 413 status = "disabled"; 414 }; 415 416 usb1: usb3@3110000 { 417 compatible = "snps,dwc3"; 418 reg = <0x0 0x3110000 0x0 0x10000>; 419 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 420 dr_mode = "host"; 421 snps,quirk-frame-length-adjustment = <0x20>; 422 snps,dis_rxdet_inp3_quirk; 423 status = "disabled"; 424 }; 425 426 sata: sata@3200000 { 427 compatible = "fsl,ls1088a-ahci"; 428 reg = <0x0 0x3200000 0x0 0x10000>, 429 <0x7 0x100520 0x0 0x4>; 430 reg-names = "ahci", "sata-ecc"; 431 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&clockgen 4 3>; 433 dma-coherent; 434 status = "disabled"; 435 }; 436 437 crypto: crypto@8000000 { 438 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 439 fsl,sec-era = <8>; 440 #address-cells = <1>; 441 #size-cells = <1>; 442 ranges = <0x0 0x00 0x8000000 0x100000>; 443 reg = <0x00 0x8000000 0x0 0x100000>; 444 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 445 dma-coherent; 446 447 sec_jr0: jr@10000 { 448 compatible = "fsl,sec-v5.0-job-ring", 449 "fsl,sec-v4.0-job-ring"; 450 reg = <0x10000 0x10000>; 451 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 452 }; 453 454 sec_jr1: jr@20000 { 455 compatible = "fsl,sec-v5.0-job-ring", 456 "fsl,sec-v4.0-job-ring"; 457 reg = <0x20000 0x10000>; 458 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 459 }; 460 461 sec_jr2: jr@30000 { 462 compatible = "fsl,sec-v5.0-job-ring", 463 "fsl,sec-v4.0-job-ring"; 464 reg = <0x30000 0x10000>; 465 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 466 }; 467 468 sec_jr3: jr@40000 { 469 compatible = "fsl,sec-v5.0-job-ring", 470 "fsl,sec-v4.0-job-ring"; 471 reg = <0x40000 0x10000>; 472 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 473 }; 474 }; 475 476 pcie@3400000 { 477 compatible = "fsl,ls1088a-pcie"; 478 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 479 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 480 reg-names = "regs", "config"; 481 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 482 interrupt-names = "aer"; 483 #address-cells = <3>; 484 #size-cells = <2>; 485 device_type = "pci"; 486 dma-coherent; 487 num-viewport = <256>; 488 bus-range = <0x0 0xff>; 489 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 490 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 491 msi-parent = <&its>; 492 #interrupt-cells = <1>; 493 interrupt-map-mask = <0 0 0 7>; 494 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, 495 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, 496 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, 497 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; 498 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 499 status = "disabled"; 500 }; 501 502 pcie@3500000 { 503 compatible = "fsl,ls1088a-pcie"; 504 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 505 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 506 reg-names = "regs", "config"; 507 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 508 interrupt-names = "aer"; 509 #address-cells = <3>; 510 #size-cells = <2>; 511 device_type = "pci"; 512 dma-coherent; 513 num-viewport = <6>; 514 bus-range = <0x0 0xff>; 515 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 516 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 517 msi-parent = <&its>; 518 #interrupt-cells = <1>; 519 interrupt-map-mask = <0 0 0 7>; 520 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, 521 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, 522 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, 523 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; 524 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 525 status = "disabled"; 526 }; 527 528 pcie@3600000 { 529 compatible = "fsl,ls1088a-pcie"; 530 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 531 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 532 reg-names = "regs", "config"; 533 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 534 interrupt-names = "aer"; 535 #address-cells = <3>; 536 #size-cells = <2>; 537 device_type = "pci"; 538 dma-coherent; 539 num-viewport = <6>; 540 bus-range = <0x0 0xff>; 541 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 542 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 543 msi-parent = <&its>; 544 #interrupt-cells = <1>; 545 interrupt-map-mask = <0 0 0 7>; 546 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, 547 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, 548 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, 549 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; 550 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 551 status = "disabled"; 552 }; 553 554 smmu: iommu@5000000 { 555 compatible = "arm,mmu-500"; 556 reg = <0 0x5000000 0 0x800000>; 557 #iommu-cells = <1>; 558 stream-match-mask = <0x7C00>; 559 #global-interrupts = <12>; 560 // global secure fault 561 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 562 // combined secure 563 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 564 // global non-secure fault 565 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 566 // combined non-secure 567 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 568 // performance counter interrupts 0-7 569 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 577 // per context interrupt, 64 interrupts 578 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 642 }; 643 644 console@8340020 { 645 compatible = "fsl,dpaa2-console"; 646 reg = <0x00000000 0x08340020 0 0x2>; 647 }; 648 649 ptp-timer@8b95000 { 650 compatible = "fsl,dpaa2-ptp"; 651 reg = <0x0 0x8b95000 0x0 0x100>; 652 clocks = <&clockgen 4 0>; 653 little-endian; 654 fsl,extts-fifo; 655 }; 656 657 cluster1_core0_watchdog: wdt@c000000 { 658 compatible = "arm,sp805-wdt", "arm,primecell"; 659 reg = <0x0 0xc000000 0x0 0x1000>; 660 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 661 clock-names = "apb_pclk", "wdog_clk"; 662 }; 663 664 cluster1_core1_watchdog: wdt@c010000 { 665 compatible = "arm,sp805-wdt", "arm,primecell"; 666 reg = <0x0 0xc010000 0x0 0x1000>; 667 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 668 clock-names = "apb_pclk", "wdog_clk"; 669 }; 670 671 cluster1_core2_watchdog: wdt@c020000 { 672 compatible = "arm,sp805-wdt", "arm,primecell"; 673 reg = <0x0 0xc020000 0x0 0x1000>; 674 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 675 clock-names = "apb_pclk", "wdog_clk"; 676 }; 677 678 cluster1_core3_watchdog: wdt@c030000 { 679 compatible = "arm,sp805-wdt", "arm,primecell"; 680 reg = <0x0 0xc030000 0x0 0x1000>; 681 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 682 clock-names = "apb_pclk", "wdog_clk"; 683 }; 684 685 cluster2_core0_watchdog: wdt@c100000 { 686 compatible = "arm,sp805-wdt", "arm,primecell"; 687 reg = <0x0 0xc100000 0x0 0x1000>; 688 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 689 clock-names = "apb_pclk", "wdog_clk"; 690 }; 691 692 cluster2_core1_watchdog: wdt@c110000 { 693 compatible = "arm,sp805-wdt", "arm,primecell"; 694 reg = <0x0 0xc110000 0x0 0x1000>; 695 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 696 clock-names = "apb_pclk", "wdog_clk"; 697 }; 698 699 cluster2_core2_watchdog: wdt@c120000 { 700 compatible = "arm,sp805-wdt", "arm,primecell"; 701 reg = <0x0 0xc120000 0x0 0x1000>; 702 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 703 clock-names = "apb_pclk", "wdog_clk"; 704 }; 705 706 cluster2_core3_watchdog: wdt@c130000 { 707 compatible = "arm,sp805-wdt", "arm,primecell"; 708 reg = <0x0 0xc130000 0x0 0x1000>; 709 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 710 clock-names = "apb_pclk", "wdog_clk"; 711 }; 712 713 fsl_mc: fsl-mc@80c000000 { 714 compatible = "fsl,qoriq-mc"; 715 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 716 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 717 msi-parent = <&its>; 718 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ 719 dma-coherent; 720 #address-cells = <3>; 721 #size-cells = <1>; 722 723 /* 724 * Region type 0x0 - MC portals 725 * Region type 0x1 - QBMAN portals 726 */ 727 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 728 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 729 730 dpmacs { 731 #address-cells = <1>; 732 #size-cells = <0>; 733 734 dpmac1: dpmac@1 { 735 compatible = "fsl,qoriq-mc-dpmac"; 736 reg = <1>; 737 }; 738 739 dpmac2: dpmac@2 { 740 compatible = "fsl,qoriq-mc-dpmac"; 741 reg = <2>; 742 }; 743 744 dpmac3: dpmac@3 { 745 compatible = "fsl,qoriq-mc-dpmac"; 746 reg = <3>; 747 }; 748 749 dpmac4: dpmac@4 { 750 compatible = "fsl,qoriq-mc-dpmac"; 751 reg = <4>; 752 }; 753 754 dpmac5: dpmac@5 { 755 compatible = "fsl,qoriq-mc-dpmac"; 756 reg = <5>; 757 }; 758 759 dpmac6: dpmac@6 { 760 compatible = "fsl,qoriq-mc-dpmac"; 761 reg = <6>; 762 }; 763 764 dpmac7: dpmac@7 { 765 compatible = "fsl,qoriq-mc-dpmac"; 766 reg = <7>; 767 }; 768 769 dpmac8: dpmac@8 { 770 compatible = "fsl,qoriq-mc-dpmac"; 771 reg = <8>; 772 }; 773 774 dpmac9: dpmac@9 { 775 compatible = "fsl,qoriq-mc-dpmac"; 776 reg = <9>; 777 }; 778 779 dpmac10: dpmac@a { 780 compatible = "fsl,qoriq-mc-dpmac"; 781 reg = <0xa>; 782 }; 783 }; 784 }; 785 786 rcpm: power-controller@1e34040 { 787 compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; 788 reg = <0x0 0x1e34040 0x0 0x18>; 789 #fsl,rcpm-wakeup-cells = <6>; 790 }; 791 792 ftm_alarm0: timer@2800000 { 793 compatible = "fsl,ls1088a-ftm-alarm"; 794 reg = <0x0 0x2800000 0x0 0x10000>; 795 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; 796 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 797 }; 798 }; 799 800 firmware { 801 optee { 802 compatible = "linaro,optee-tz"; 803 method = "smc"; 804 }; 805 }; 806}; 807