1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1088A family SoC. 4 * 5 * Copyright 2017-2020 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1088a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 crypto = &crypto; 22 rtc1 = &ftm_alarm0; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 /* We have 2 clusters having 4 Cortex-A53 cores each */ 30 cpu0: cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a53"; 33 reg = <0x0>; 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35 cpu-idle-states = <&CPU_PH20>; 36 #cooling-cells = <2>; 37 }; 38 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0x1>; 43 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 44 cpu-idle-states = <&CPU_PH20>; 45 #cooling-cells = <2>; 46 }; 47 48 cpu2: cpu@2 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 reg = <0x2>; 52 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 53 cpu-idle-states = <&CPU_PH20>; 54 #cooling-cells = <2>; 55 }; 56 57 cpu3: cpu@3 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53"; 60 reg = <0x3>; 61 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 62 cpu-idle-states = <&CPU_PH20>; 63 #cooling-cells = <2>; 64 }; 65 66 cpu4: cpu@100 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x100>; 70 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 71 cpu-idle-states = <&CPU_PH20>; 72 #cooling-cells = <2>; 73 }; 74 75 cpu5: cpu@101 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a53"; 78 reg = <0x101>; 79 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 80 cpu-idle-states = <&CPU_PH20>; 81 #cooling-cells = <2>; 82 }; 83 84 cpu6: cpu@102 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x102>; 88 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 89 cpu-idle-states = <&CPU_PH20>; 90 #cooling-cells = <2>; 91 }; 92 93 cpu7: cpu@103 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x103>; 97 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 98 cpu-idle-states = <&CPU_PH20>; 99 #cooling-cells = <2>; 100 }; 101 102 CPU_PH20: cpu-ph20 { 103 compatible = "arm,idle-state"; 104 idle-state-name = "PH20"; 105 arm,psci-suspend-param = <0x0>; 106 entry-latency-us = <1000>; 107 exit-latency-us = <1000>; 108 min-residency-us = <3000>; 109 }; 110 }; 111 112 gic: interrupt-controller@6000000 { 113 compatible = "arm,gic-v3"; 114 #interrupt-cells = <3>; 115 interrupt-controller; 116 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 117 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ 118 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 119 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 120 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 121 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; 122 #address-cells = <2>; 123 #size-cells = <2>; 124 ranges; 125 126 its: gic-its@6020000 { 127 compatible = "arm,gic-v3-its"; 128 msi-controller; 129 reg = <0x0 0x6020000 0 0x20000>; 130 }; 131 }; 132 133 thermal-zones { 134 core-cluster { 135 polling-delay-passive = <1000>; 136 polling-delay = <5000>; 137 thermal-sensors = <&tmu 0>; 138 139 trips { 140 core_cluster_alert: core-cluster-alert { 141 temperature = <85000>; 142 hysteresis = <2000>; 143 type = "passive"; 144 }; 145 146 core-cluster-crit { 147 temperature = <95000>; 148 hysteresis = <2000>; 149 type = "critical"; 150 }; 151 }; 152 153 cooling-maps { 154 map0 { 155 trip = <&core_cluster_alert>; 156 cooling-device = 157 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 158 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 159 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 160 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 161 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 162 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 163 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 164 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 165 }; 166 }; 167 }; 168 169 soc { 170 polling-delay-passive = <1000>; 171 polling-delay = <5000>; 172 thermal-sensors = <&tmu 1>; 173 174 trips { 175 soc-crit { 176 temperature = <95000>; 177 hysteresis = <2000>; 178 type = "critical"; 179 }; 180 }; 181 }; 182 }; 183 184 timer { 185 compatible = "arm,armv8-timer"; 186 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 187 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 188 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 189 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 190 }; 191 192 pmu { 193 compatible = "arm,cortex-a53-pmu"; 194 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 195 }; 196 197 psci { 198 compatible = "arm,psci-0.2"; 199 method = "smc"; 200 }; 201 202 sysclk: sysclk { 203 compatible = "fixed-clock"; 204 #clock-cells = <0>; 205 clock-frequency = <100000000>; 206 clock-output-names = "sysclk"; 207 }; 208 209 soc { 210 compatible = "simple-bus"; 211 #address-cells = <2>; 212 #size-cells = <2>; 213 ranges; 214 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 215 216 clockgen: clocking@1300000 { 217 compatible = "fsl,ls1088a-clockgen"; 218 reg = <0 0x1300000 0 0xa0000>; 219 #clock-cells = <2>; 220 clocks = <&sysclk>; 221 }; 222 223 dcfg: dcfg@1e00000 { 224 compatible = "fsl,ls1088a-dcfg", "syscon"; 225 reg = <0x0 0x1e00000 0x0 0x10000>; 226 little-endian; 227 }; 228 229 isc: syscon@1f70000 { 230 compatible = "fsl,ls1088a-isc", "syscon"; 231 reg = <0x0 0x1f70000 0x0 0x10000>; 232 little-endian; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 ranges = <0x0 0x0 0x1f70000 0x10000>; 236 237 extirq: interrupt-controller@14 { 238 compatible = "fsl,ls1088a-extirq"; 239 #interrupt-cells = <2>; 240 #address-cells = <0>; 241 interrupt-controller; 242 reg = <0x14 4>; 243 interrupt-map = 244 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 245 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 246 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 247 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 248 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 249 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 250 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 251 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 252 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 253 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 254 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 255 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 256 interrupt-map-mask = <0xffffffff 0x0>; 257 }; 258 }; 259 260 tmu: tmu@1f80000 { 261 compatible = "fsl,qoriq-tmu"; 262 reg = <0x0 0x1f80000 0x0 0x10000>; 263 interrupts = <0 23 0x4>; 264 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 265 fsl,tmu-calibration = 266 /* Calibration data group 1 */ 267 <0x00000000 0x00000023 268 0x00000001 0x0000002a 269 0x00000002 0x00000030 270 0x00000003 0x00000037 271 0x00000004 0x0000003d 272 0x00000005 0x00000044 273 0x00000006 0x0000004a 274 0x00000007 0x00000051 275 0x00000008 0x00000057 276 0x00000009 0x0000005e 277 0x0000000a 0x00000064 278 0x0000000b 0x0000006b 279 /* Calibration data group 2 */ 280 0x00010000 0x00000022 281 0x00010001 0x0000002a 282 0x00010002 0x00000032 283 0x00010003 0x0000003a 284 0x00010004 0x00000042 285 0x00010005 0x0000004a 286 0x00010006 0x00000052 287 0x00010007 0x0000005a 288 0x00010008 0x00000062 289 0x00010009 0x0000006a 290 /* Calibration data group 3 */ 291 0x00020000 0x00000021 292 0x00020001 0x0000002b 293 0x00020002 0x00000035 294 0x00020003 0x00000040 295 0x00020004 0x0000004a 296 0x00020005 0x00000054 297 0x00020006 0x0000005e 298 /* Calibration data group 4 */ 299 0x00030000 0x00000010 300 0x00030001 0x0000001c 301 0x00030002 0x00000027 302 0x00030003 0x00000032 303 0x00030004 0x0000003e 304 0x00030005 0x00000049 305 0x00030006 0x00000054 306 0x00030007 0x00000060>; 307 little-endian; 308 #thermal-sensor-cells = <1>; 309 }; 310 311 dspi: spi@2100000 { 312 compatible = "fsl,ls1088a-dspi", 313 "fsl,ls1021a-v1.0-dspi"; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 reg = <0x0 0x2100000 0x0 0x10000>; 317 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 318 clock-names = "dspi"; 319 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 320 QORIQ_CLK_PLL_DIV(2)>; 321 spi-num-chipselects = <6>; 322 status = "disabled"; 323 }; 324 325 duart0: serial@21c0500 { 326 compatible = "fsl,ns16550", "ns16550a"; 327 reg = <0x0 0x21c0500 0x0 0x100>; 328 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 329 QORIQ_CLK_PLL_DIV(4)>; 330 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 331 status = "disabled"; 332 }; 333 334 duart1: serial@21c0600 { 335 compatible = "fsl,ns16550", "ns16550a"; 336 reg = <0x0 0x21c0600 0x0 0x100>; 337 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 338 QORIQ_CLK_PLL_DIV(4)>; 339 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 340 status = "disabled"; 341 }; 342 343 gpio0: gpio@2300000 { 344 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 345 reg = <0x0 0x2300000 0x0 0x10000>; 346 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 347 little-endian; 348 gpio-controller; 349 #gpio-cells = <2>; 350 interrupt-controller; 351 #interrupt-cells = <2>; 352 }; 353 354 gpio1: gpio@2310000 { 355 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 356 reg = <0x0 0x2310000 0x0 0x10000>; 357 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 358 little-endian; 359 gpio-controller; 360 #gpio-cells = <2>; 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 }; 364 365 gpio2: gpio@2320000 { 366 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 367 reg = <0x0 0x2320000 0x0 0x10000>; 368 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 369 little-endian; 370 gpio-controller; 371 #gpio-cells = <2>; 372 interrupt-controller; 373 #interrupt-cells = <2>; 374 }; 375 376 gpio3: gpio@2330000 { 377 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 378 reg = <0x0 0x2330000 0x0 0x10000>; 379 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 380 little-endian; 381 gpio-controller; 382 #gpio-cells = <2>; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 387 ifc: ifc@2240000 { 388 compatible = "fsl,ifc", "simple-bus"; 389 reg = <0x0 0x2240000 0x0 0x20000>; 390 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 391 little-endian; 392 #address-cells = <2>; 393 #size-cells = <1>; 394 status = "disabled"; 395 }; 396 397 i2c0: i2c@2000000 { 398 compatible = "fsl,vf610-i2c"; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 reg = <0x0 0x2000000 0x0 0x10000>; 402 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 404 QORIQ_CLK_PLL_DIV(8)>; 405 status = "disabled"; 406 }; 407 408 i2c1: i2c@2010000 { 409 compatible = "fsl,vf610-i2c"; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 reg = <0x0 0x2010000 0x0 0x10000>; 413 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 415 QORIQ_CLK_PLL_DIV(8)>; 416 status = "disabled"; 417 }; 418 419 i2c2: i2c@2020000 { 420 compatible = "fsl,vf610-i2c"; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 reg = <0x0 0x2020000 0x0 0x10000>; 424 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 426 QORIQ_CLK_PLL_DIV(8)>; 427 status = "disabled"; 428 }; 429 430 i2c3: i2c@2030000 { 431 compatible = "fsl,vf610-i2c"; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 reg = <0x0 0x2030000 0x0 0x10000>; 435 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 437 QORIQ_CLK_PLL_DIV(8)>; 438 status = "disabled"; 439 }; 440 441 qspi: spi@20c0000 { 442 compatible = "fsl,ls2080a-qspi"; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 reg = <0x0 0x20c0000 0x0 0x10000>, 446 <0x0 0x20000000 0x0 0x10000000>; 447 reg-names = "QuadSPI", "QuadSPI-memory"; 448 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 449 clock-names = "qspi_en", "qspi"; 450 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 451 QORIQ_CLK_PLL_DIV(4)>, 452 <&clockgen QORIQ_CLK_PLATFORM_PLL 453 QORIQ_CLK_PLL_DIV(4)>; 454 status = "disabled"; 455 }; 456 457 esdhc: esdhc@2140000 { 458 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; 459 reg = <0x0 0x2140000 0x0 0x10000>; 460 interrupts = <0 28 0x4>; /* Level high type */ 461 clock-frequency = <0>; 462 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 463 voltage-ranges = <1800 1800 3300 3300>; 464 sdhci,auto-cmd12; 465 little-endian; 466 bus-width = <4>; 467 status = "disabled"; 468 }; 469 470 usb0: usb@3100000 { 471 compatible = "snps,dwc3"; 472 reg = <0x0 0x3100000 0x0 0x10000>; 473 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 474 dr_mode = "host"; 475 snps,quirk-frame-length-adjustment = <0x20>; 476 snps,dis_rxdet_inp3_quirk; 477 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 478 status = "disabled"; 479 }; 480 481 usb1: usb@3110000 { 482 compatible = "snps,dwc3"; 483 reg = <0x0 0x3110000 0x0 0x10000>; 484 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 485 dr_mode = "host"; 486 snps,quirk-frame-length-adjustment = <0x20>; 487 snps,dis_rxdet_inp3_quirk; 488 status = "disabled"; 489 }; 490 491 sata: sata@3200000 { 492 compatible = "fsl,ls1088a-ahci"; 493 reg = <0x0 0x3200000 0x0 0x10000>, 494 <0x7 0x100520 0x0 0x4>; 495 reg-names = "ahci", "sata-ecc"; 496 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 498 QORIQ_CLK_PLL_DIV(4)>; 499 dma-coherent; 500 status = "disabled"; 501 }; 502 503 crypto: crypto@8000000 { 504 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 505 fsl,sec-era = <8>; 506 #address-cells = <1>; 507 #size-cells = <1>; 508 ranges = <0x0 0x00 0x8000000 0x100000>; 509 reg = <0x00 0x8000000 0x0 0x100000>; 510 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 511 dma-coherent; 512 513 sec_jr0: jr@10000 { 514 compatible = "fsl,sec-v5.0-job-ring", 515 "fsl,sec-v4.0-job-ring"; 516 reg = <0x10000 0x10000>; 517 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 518 }; 519 520 sec_jr1: jr@20000 { 521 compatible = "fsl,sec-v5.0-job-ring", 522 "fsl,sec-v4.0-job-ring"; 523 reg = <0x20000 0x10000>; 524 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 525 }; 526 527 sec_jr2: jr@30000 { 528 compatible = "fsl,sec-v5.0-job-ring", 529 "fsl,sec-v4.0-job-ring"; 530 reg = <0x30000 0x10000>; 531 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 532 }; 533 534 sec_jr3: jr@40000 { 535 compatible = "fsl,sec-v5.0-job-ring", 536 "fsl,sec-v4.0-job-ring"; 537 reg = <0x40000 0x10000>; 538 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 539 }; 540 }; 541 542 pcie1: pcie@3400000 { 543 compatible = "fsl,ls1088a-pcie"; 544 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 545 <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 546 reg-names = "regs", "config"; 547 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 548 interrupt-names = "aer"; 549 #address-cells = <3>; 550 #size-cells = <2>; 551 device_type = "pci"; 552 dma-coherent; 553 num-viewport = <256>; 554 bus-range = <0x0 0xff>; 555 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 556 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 557 msi-parent = <&its>; 558 #interrupt-cells = <1>; 559 interrupt-map-mask = <0 0 0 7>; 560 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, 561 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, 562 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, 563 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; 564 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 565 status = "disabled"; 566 }; 567 568 pcie_ep1: pcie-ep@3400000 { 569 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; 570 reg = <0x00 0x03400000 0x0 0x00100000>, 571 <0x20 0x00000000 0x8 0x00000000>; 572 reg-names = "regs", "addr_space"; 573 num-ib-windows = <24>; 574 num-ob-windows = <256>; 575 max-functions = /bits/ 8 <2>; 576 status = "disabled"; 577 }; 578 579 pcie2: pcie@3500000 { 580 compatible = "fsl,ls1088a-pcie"; 581 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 582 <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 583 reg-names = "regs", "config"; 584 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 585 interrupt-names = "aer"; 586 #address-cells = <3>; 587 #size-cells = <2>; 588 device_type = "pci"; 589 dma-coherent; 590 num-viewport = <6>; 591 bus-range = <0x0 0xff>; 592 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 593 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 594 msi-parent = <&its>; 595 #interrupt-cells = <1>; 596 interrupt-map-mask = <0 0 0 7>; 597 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, 598 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, 599 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, 600 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; 601 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 602 status = "disabled"; 603 }; 604 605 pcie_ep2: pcie-ep@3500000 { 606 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; 607 reg = <0x00 0x03500000 0x0 0x00100000>, 608 <0x28 0x00000000 0x8 0x00000000>; 609 reg-names = "regs", "addr_space"; 610 num-ib-windows = <6>; 611 num-ob-windows = <6>; 612 status = "disabled"; 613 }; 614 615 pcie3: pcie@3600000 { 616 compatible = "fsl,ls1088a-pcie"; 617 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 618 <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 619 reg-names = "regs", "config"; 620 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 621 interrupt-names = "aer"; 622 #address-cells = <3>; 623 #size-cells = <2>; 624 device_type = "pci"; 625 dma-coherent; 626 num-viewport = <6>; 627 bus-range = <0x0 0xff>; 628 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 629 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 630 msi-parent = <&its>; 631 #interrupt-cells = <1>; 632 interrupt-map-mask = <0 0 0 7>; 633 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, 634 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, 635 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, 636 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; 637 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 638 status = "disabled"; 639 }; 640 641 pcie_ep3: pcie-ep@3600000 { 642 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; 643 reg = <0x00 0x03600000 0x0 0x00100000>, 644 <0x30 0x00000000 0x8 0x00000000>; 645 reg-names = "regs", "addr_space"; 646 num-ib-windows = <6>; 647 num-ob-windows = <6>; 648 status = "disabled"; 649 }; 650 651 smmu: iommu@5000000 { 652 compatible = "arm,mmu-500"; 653 reg = <0 0x5000000 0 0x800000>; 654 #iommu-cells = <1>; 655 stream-match-mask = <0x7C00>; 656 #global-interrupts = <12>; 657 // global secure fault 658 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 659 // combined secure 660 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 661 // global non-secure fault 662 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 663 // combined non-secure 664 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 665 // performance counter interrupts 0-7 666 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 674 // per context interrupt, 64 interrupts 675 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 739 }; 740 741 console@8340020 { 742 compatible = "fsl,dpaa2-console"; 743 reg = <0x00000000 0x08340020 0 0x2>; 744 }; 745 746 ptp-timer@8b95000 { 747 compatible = "fsl,dpaa2-ptp"; 748 reg = <0x0 0x8b95000 0x0 0x100>; 749 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 750 QORIQ_CLK_PLL_DIV(1)>; 751 little-endian; 752 fsl,extts-fifo; 753 }; 754 755 emdio1: mdio@8b96000 { 756 compatible = "fsl,fman-memac-mdio"; 757 reg = <0x0 0x8b96000 0x0 0x1000>; 758 little-endian; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 status = "disabled"; 762 }; 763 764 emdio2: mdio@8b97000 { 765 compatible = "fsl,fman-memac-mdio"; 766 reg = <0x0 0x8b97000 0x0 0x1000>; 767 little-endian; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 status = "disabled"; 771 }; 772 773 pcs_mdio1: mdio@8c07000 { 774 compatible = "fsl,fman-memac-mdio"; 775 reg = <0x0 0x8c07000 0x0 0x1000>; 776 little-endian; 777 #address-cells = <1>; 778 #size-cells = <0>; 779 status = "disabled"; 780 781 pcs1: ethernet-phy@0 { 782 reg = <0>; 783 }; 784 }; 785 786 pcs_mdio2: mdio@8c0b000 { 787 compatible = "fsl,fman-memac-mdio"; 788 reg = <0x0 0x8c0b000 0x0 0x1000>; 789 little-endian; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 status = "disabled"; 793 794 pcs2: ethernet-phy@0 { 795 reg = <0>; 796 }; 797 }; 798 799 pcs_mdio3: mdio@8c0f000 { 800 compatible = "fsl,fman-memac-mdio"; 801 reg = <0x0 0x8c0f000 0x0 0x1000>; 802 little-endian; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 status = "disabled"; 806 807 pcs3_0: ethernet-phy@0 { 808 reg = <0>; 809 }; 810 811 pcs3_1: ethernet-phy@1 { 812 reg = <1>; 813 }; 814 815 pcs3_2: ethernet-phy@2 { 816 reg = <2>; 817 }; 818 819 pcs3_3: ethernet-phy@3 { 820 reg = <3>; 821 }; 822 }; 823 824 pcs_mdio7: mdio@8c1f000 { 825 compatible = "fsl,fman-memac-mdio"; 826 reg = <0x0 0x8c1f000 0x0 0x1000>; 827 little-endian; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 status = "disabled"; 831 832 pcs7_0: ethernet-phy@0 { 833 reg = <0>; 834 }; 835 836 pcs7_1: ethernet-phy@1 { 837 reg = <1>; 838 }; 839 840 pcs7_2: ethernet-phy@2 { 841 reg = <2>; 842 }; 843 844 pcs7_3: ethernet-phy@3 { 845 reg = <3>; 846 }; 847 }; 848 849 cluster1_core0_watchdog: wdt@c000000 { 850 compatible = "arm,sp805-wdt", "arm,primecell"; 851 reg = <0x0 0xc000000 0x0 0x1000>; 852 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 853 QORIQ_CLK_PLL_DIV(16)>, 854 <&clockgen QORIQ_CLK_PLATFORM_PLL 855 QORIQ_CLK_PLL_DIV(16)>; 856 clock-names = "wdog_clk", "apb_pclk"; 857 }; 858 859 cluster1_core1_watchdog: wdt@c010000 { 860 compatible = "arm,sp805-wdt", "arm,primecell"; 861 reg = <0x0 0xc010000 0x0 0x1000>; 862 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 863 QORIQ_CLK_PLL_DIV(16)>, 864 <&clockgen QORIQ_CLK_PLATFORM_PLL 865 QORIQ_CLK_PLL_DIV(16)>; 866 clock-names = "wdog_clk", "apb_pclk"; 867 }; 868 869 cluster1_core2_watchdog: wdt@c020000 { 870 compatible = "arm,sp805-wdt", "arm,primecell"; 871 reg = <0x0 0xc020000 0x0 0x1000>; 872 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 873 QORIQ_CLK_PLL_DIV(16)>, 874 <&clockgen QORIQ_CLK_PLATFORM_PLL 875 QORIQ_CLK_PLL_DIV(16)>; 876 clock-names = "wdog_clk", "apb_pclk"; 877 }; 878 879 cluster1_core3_watchdog: wdt@c030000 { 880 compatible = "arm,sp805-wdt", "arm,primecell"; 881 reg = <0x0 0xc030000 0x0 0x1000>; 882 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 883 QORIQ_CLK_PLL_DIV(16)>, 884 <&clockgen QORIQ_CLK_PLATFORM_PLL 885 QORIQ_CLK_PLL_DIV(16)>; 886 clock-names = "wdog_clk", "apb_pclk"; 887 }; 888 889 cluster2_core0_watchdog: wdt@c100000 { 890 compatible = "arm,sp805-wdt", "arm,primecell"; 891 reg = <0x0 0xc100000 0x0 0x1000>; 892 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 893 QORIQ_CLK_PLL_DIV(16)>, 894 <&clockgen QORIQ_CLK_PLATFORM_PLL 895 QORIQ_CLK_PLL_DIV(16)>; 896 clock-names = "wdog_clk", "apb_pclk"; 897 }; 898 899 cluster2_core1_watchdog: wdt@c110000 { 900 compatible = "arm,sp805-wdt", "arm,primecell"; 901 reg = <0x0 0xc110000 0x0 0x1000>; 902 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 903 QORIQ_CLK_PLL_DIV(16)>, 904 <&clockgen QORIQ_CLK_PLATFORM_PLL 905 QORIQ_CLK_PLL_DIV(16)>; 906 clock-names = "wdog_clk", "apb_pclk"; 907 }; 908 909 cluster2_core2_watchdog: wdt@c120000 { 910 compatible = "arm,sp805-wdt", "arm,primecell"; 911 reg = <0x0 0xc120000 0x0 0x1000>; 912 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 913 QORIQ_CLK_PLL_DIV(16)>, 914 <&clockgen QORIQ_CLK_PLATFORM_PLL 915 QORIQ_CLK_PLL_DIV(16)>; 916 clock-names = "wdog_clk", "apb_pclk"; 917 }; 918 919 cluster2_core3_watchdog: wdt@c130000 { 920 compatible = "arm,sp805-wdt", "arm,primecell"; 921 reg = <0x0 0xc130000 0x0 0x1000>; 922 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 923 QORIQ_CLK_PLL_DIV(16)>, 924 <&clockgen QORIQ_CLK_PLATFORM_PLL 925 QORIQ_CLK_PLL_DIV(16)>; 926 clock-names = "wdog_clk", "apb_pclk"; 927 }; 928 929 fsl_mc: fsl-mc@80c000000 { 930 compatible = "fsl,qoriq-mc"; 931 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 932 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 933 msi-parent = <&its>; 934 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ 935 dma-coherent; 936 #address-cells = <3>; 937 #size-cells = <1>; 938 939 /* 940 * Region type 0x0 - MC portals 941 * Region type 0x1 - QBMAN portals 942 */ 943 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 944 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 945 946 dpmacs { 947 #address-cells = <1>; 948 #size-cells = <0>; 949 950 dpmac1: ethernet@1 { 951 compatible = "fsl,qoriq-mc-dpmac"; 952 reg = <1>; 953 }; 954 955 dpmac2: ethernet@2 { 956 compatible = "fsl,qoriq-mc-dpmac"; 957 reg = <2>; 958 }; 959 960 dpmac3: ethernet@3 { 961 compatible = "fsl,qoriq-mc-dpmac"; 962 reg = <3>; 963 }; 964 965 dpmac4: ethernet@4 { 966 compatible = "fsl,qoriq-mc-dpmac"; 967 reg = <4>; 968 }; 969 970 dpmac5: ethernet@5 { 971 compatible = "fsl,qoriq-mc-dpmac"; 972 reg = <5>; 973 }; 974 975 dpmac6: ethernet@6 { 976 compatible = "fsl,qoriq-mc-dpmac"; 977 reg = <6>; 978 }; 979 980 dpmac7: ethernet@7 { 981 compatible = "fsl,qoriq-mc-dpmac"; 982 reg = <7>; 983 }; 984 985 dpmac8: ethernet@8 { 986 compatible = "fsl,qoriq-mc-dpmac"; 987 reg = <8>; 988 }; 989 990 dpmac9: ethernet@9 { 991 compatible = "fsl,qoriq-mc-dpmac"; 992 reg = <9>; 993 }; 994 995 dpmac10: ethernet@a { 996 compatible = "fsl,qoriq-mc-dpmac"; 997 reg = <0xa>; 998 }; 999 }; 1000 }; 1001 1002 rcpm: power-controller@1e34040 { 1003 compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1004 reg = <0x0 0x1e34040 0x0 0x18>; 1005 #fsl,rcpm-wakeup-cells = <6>; 1006 little-endian; 1007 }; 1008 1009 ftm_alarm0: timer@2800000 { 1010 compatible = "fsl,ls1088a-ftm-alarm"; 1011 reg = <0x0 0x2800000 0x0 0x10000>; 1012 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; 1013 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1014 }; 1015 }; 1016 1017 firmware { 1018 optee { 1019 compatible = "linaro,optee-tz"; 1020 method = "smc"; 1021 }; 1022 }; 1023}; 1024