1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1046A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2020 NXP 7 * 8 * Mingkai Hu <mingkai.hu@nxp.com> 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "fsl,ls1046a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 crypto = &crypto; 23 fman0 = &fman0; 24 ethernet0 = &enet0; 25 ethernet1 = &enet1; 26 ethernet2 = &enet2; 27 ethernet3 = &enet3; 28 ethernet4 = &enet4; 29 ethernet5 = &enet5; 30 ethernet6 = &enet6; 31 ethernet7 = &enet7; 32 rtc1 = &ftm_alarm0; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a72"; 42 reg = <0x0>; 43 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 44 next-level-cache = <&l2>; 45 cpu-idle-states = <&CPU_PH20>; 46 #cooling-cells = <2>; 47 }; 48 49 cpu1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a72"; 52 reg = <0x1>; 53 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 54 next-level-cache = <&l2>; 55 cpu-idle-states = <&CPU_PH20>; 56 #cooling-cells = <2>; 57 }; 58 59 cpu2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a72"; 62 reg = <0x2>; 63 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 64 next-level-cache = <&l2>; 65 cpu-idle-states = <&CPU_PH20>; 66 #cooling-cells = <2>; 67 }; 68 69 cpu3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a72"; 72 reg = <0x3>; 73 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 74 next-level-cache = <&l2>; 75 cpu-idle-states = <&CPU_PH20>; 76 #cooling-cells = <2>; 77 }; 78 79 l2: l2-cache { 80 compatible = "cache"; 81 }; 82 }; 83 84 idle-states { 85 /* 86 * PSCI node is not added default, U-boot will add missing 87 * parts if it determines to use PSCI. 88 */ 89 entry-method = "psci"; 90 91 CPU_PH20: cpu-ph20 { 92 compatible = "arm,idle-state"; 93 idle-state-name = "PH20"; 94 arm,psci-suspend-param = <0x0>; 95 entry-latency-us = <1000>; 96 exit-latency-us = <1000>; 97 min-residency-us = <3000>; 98 }; 99 }; 100 101 memory@80000000 { 102 device_type = "memory"; 103 /* Real size will be filled by bootloader */ 104 reg = <0x0 0x80000000 0x0 0x0>; 105 }; 106 107 sysclk: sysclk { 108 compatible = "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <100000000>; 111 clock-output-names = "sysclk"; 112 }; 113 114 reboot { 115 compatible ="syscon-reboot"; 116 regmap = <&dcfg>; 117 offset = <0xb0>; 118 mask = <0x02>; 119 }; 120 121 thermal-zones { 122 ddr-controller { 123 polling-delay-passive = <1000>; 124 polling-delay = <5000>; 125 thermal-sensors = <&tmu 0>; 126 127 trips { 128 ddr-ctrler-alert { 129 temperature = <85000>; 130 hysteresis = <2000>; 131 type = "passive"; 132 }; 133 134 ddr-ctrler-crit { 135 temperature = <95000>; 136 hysteresis = <2000>; 137 type = "critical"; 138 }; 139 }; 140 }; 141 142 serdes { 143 polling-delay-passive = <1000>; 144 polling-delay = <5000>; 145 thermal-sensors = <&tmu 1>; 146 147 trips { 148 serdes-alert { 149 temperature = <85000>; 150 hysteresis = <2000>; 151 type = "passive"; 152 }; 153 154 serdes-crit { 155 temperature = <95000>; 156 hysteresis = <2000>; 157 type = "critical"; 158 }; 159 }; 160 }; 161 162 fman { 163 polling-delay-passive = <1000>; 164 polling-delay = <5000>; 165 thermal-sensors = <&tmu 2>; 166 167 trips { 168 fman-alert { 169 temperature = <85000>; 170 hysteresis = <2000>; 171 type = "passive"; 172 }; 173 174 fman-crit { 175 temperature = <95000>; 176 hysteresis = <2000>; 177 type = "critical"; 178 }; 179 }; 180 }; 181 182 core-cluster { 183 polling-delay-passive = <1000>; 184 polling-delay = <5000>; 185 thermal-sensors = <&tmu 3>; 186 187 trips { 188 core_cluster_alert: core-cluster-alert { 189 temperature = <85000>; 190 hysteresis = <2000>; 191 type = "passive"; 192 }; 193 194 core_cluster_crit: core-cluster-crit { 195 temperature = <95000>; 196 hysteresis = <2000>; 197 type = "critical"; 198 }; 199 }; 200 201 cooling-maps { 202 map0 { 203 trip = <&core_cluster_alert>; 204 cooling-device = 205 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 206 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 207 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 208 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 209 }; 210 }; 211 }; 212 213 sec { 214 polling-delay-passive = <1000>; 215 polling-delay = <5000>; 216 thermal-sensors = <&tmu 4>; 217 218 trips { 219 sec-alert { 220 temperature = <85000>; 221 hysteresis = <2000>; 222 type = "passive"; 223 }; 224 225 sec-crit { 226 temperature = <95000>; 227 hysteresis = <2000>; 228 type = "critical"; 229 }; 230 }; 231 }; 232 }; 233 234 timer { 235 compatible = "arm,armv8-timer"; 236 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) | 237 IRQ_TYPE_LEVEL_LOW)>, 238 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) | 239 IRQ_TYPE_LEVEL_LOW)>, 240 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) | 241 IRQ_TYPE_LEVEL_LOW)>, 242 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) | 243 IRQ_TYPE_LEVEL_LOW)>; 244 }; 245 246 pmu { 247 compatible = "arm,cortex-a72-pmu"; 248 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 252 interrupt-affinity = <&cpu0>, 253 <&cpu1>, 254 <&cpu2>, 255 <&cpu3>; 256 }; 257 258 gic: interrupt-controller@1400000 { 259 compatible = "arm,gic-400"; 260 #interrupt-cells = <3>; 261 interrupt-controller; 262 reg = <0x0 0x1410000 0 0x10000>, /* GICD */ 263 <0x0 0x1420000 0 0x20000>, /* GICC */ 264 <0x0 0x1440000 0 0x20000>, /* GICH */ 265 <0x0 0x1460000 0 0x20000>; /* GICV */ 266 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 267 IRQ_TYPE_LEVEL_LOW)>; 268 }; 269 270 soc: soc { 271 compatible = "simple-bus"; 272 #address-cells = <2>; 273 #size-cells = <2>; 274 ranges; 275 276 ddr: memory-controller@1080000 { 277 compatible = "fsl,qoriq-memory-controller"; 278 reg = <0x0 0x1080000 0x0 0x1000>; 279 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 280 big-endian; 281 }; 282 283 ifc: ifc@1530000 { 284 compatible = "fsl,ifc", "simple-bus"; 285 reg = <0x0 0x1530000 0x0 0x10000>; 286 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 287 status = "disabled"; 288 }; 289 290 qspi: spi@1550000 { 291 compatible = "fsl,ls1021a-qspi"; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 reg = <0x0 0x1550000 0x0 0x10000>, 295 <0x0 0x40000000 0x0 0x10000000>; 296 reg-names = "QuadSPI", "QuadSPI-memory"; 297 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 298 clock-names = "qspi_en", "qspi"; 299 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 300 QORIQ_CLK_PLL_DIV(2)>, 301 <&clockgen QORIQ_CLK_PLATFORM_PLL 302 QORIQ_CLK_PLL_DIV(2)>; 303 status = "disabled"; 304 }; 305 306 esdhc: esdhc@1560000 { 307 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; 308 reg = <0x0 0x1560000 0x0 0x10000>; 309 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 311 voltage-ranges = <1800 1800 3300 3300>; 312 sdhci,auto-cmd12; 313 big-endian; 314 bus-width = <4>; 315 }; 316 317 scfg: scfg@1570000 { 318 compatible = "fsl,ls1046a-scfg", "syscon"; 319 reg = <0x0 0x1570000 0x0 0x10000>; 320 big-endian; 321 #address-cells = <1>; 322 #size-cells = <1>; 323 ranges = <0x0 0x0 0x1570000 0x10000>; 324 325 extirq: interrupt-controller@1ac { 326 compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq"; 327 #interrupt-cells = <2>; 328 #address-cells = <0>; 329 interrupt-controller; 330 reg = <0x1ac 4>; 331 interrupt-map = 332 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 333 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 334 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 335 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 336 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 337 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 338 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 339 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 340 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 341 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 342 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 343 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 344 interrupt-map-mask = <0xffffffff 0x0>; 345 }; 346 }; 347 348 crypto: crypto@1700000 { 349 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 350 "fsl,sec-v4.0"; 351 fsl,sec-era = <8>; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges = <0x0 0x00 0x1700000 0x100000>; 355 reg = <0x00 0x1700000 0x0 0x100000>; 356 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 357 358 sec_jr0: jr@10000 { 359 compatible = "fsl,sec-v5.4-job-ring", 360 "fsl,sec-v5.0-job-ring", 361 "fsl,sec-v4.0-job-ring"; 362 reg = <0x10000 0x10000>; 363 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 364 }; 365 366 sec_jr1: jr@20000 { 367 compatible = "fsl,sec-v5.4-job-ring", 368 "fsl,sec-v5.0-job-ring", 369 "fsl,sec-v4.0-job-ring"; 370 reg = <0x20000 0x10000>; 371 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 372 }; 373 374 sec_jr2: jr@30000 { 375 compatible = "fsl,sec-v5.4-job-ring", 376 "fsl,sec-v5.0-job-ring", 377 "fsl,sec-v4.0-job-ring"; 378 reg = <0x30000 0x10000>; 379 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 380 }; 381 382 sec_jr3: jr@40000 { 383 compatible = "fsl,sec-v5.4-job-ring", 384 "fsl,sec-v5.0-job-ring", 385 "fsl,sec-v4.0-job-ring"; 386 reg = <0x40000 0x10000>; 387 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 388 }; 389 }; 390 391 qman: qman@1880000 { 392 compatible = "fsl,qman"; 393 reg = <0x0 0x1880000 0x0 0x10000>; 394 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 395 memory-region = <&qman_fqd &qman_pfdr>; 396 397 }; 398 399 bman: bman@1890000 { 400 compatible = "fsl,bman"; 401 reg = <0x0 0x1890000 0x0 0x10000>; 402 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 403 memory-region = <&bman_fbpr>; 404 405 }; 406 407 qportals: qman-portals@500000000 { 408 ranges = <0x0 0x5 0x00000000 0x8000000>; 409 }; 410 411 bportals: bman-portals@508000000 { 412 ranges = <0x0 0x5 0x08000000 0x8000000>; 413 }; 414 415 dcfg: dcfg@1ee0000 { 416 compatible = "fsl,ls1046a-dcfg", "syscon"; 417 reg = <0x0 0x1ee0000 0x0 0x1000>; 418 big-endian; 419 }; 420 421 clockgen: clocking@1ee1000 { 422 compatible = "fsl,ls1046a-clockgen"; 423 reg = <0x0 0x1ee1000 0x0 0x1000>; 424 #clock-cells = <2>; 425 clocks = <&sysclk>; 426 }; 427 428 tmu: tmu@1f00000 { 429 compatible = "fsl,qoriq-tmu"; 430 reg = <0x0 0x1f00000 0x0 0x10000>; 431 interrupts = <0 33 0x4>; 432 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 433 fsl,tmu-calibration = 434 /* Calibration data group 1 */ 435 <0x00000000 0x00000023 436 0x00000001 0x00000029 437 0x00000002 0x0000002f 438 0x00000003 0x00000036 439 0x00000004 0x0000003c 440 0x00000005 0x00000042 441 0x00000006 0x00000049 442 0x00000007 0x0000004f 443 0x00000008 0x00000055 444 0x00000009 0x0000005c 445 0x0000000a 0x00000062 446 0x0000000b 0x00000068 447 /* Calibration data group 2 */ 448 0x00010000 0x00000022 449 0x00010001 0x0000002a 450 0x00010002 0x00000032 451 0x00010003 0x0000003a 452 0x00010004 0x00000042 453 0x00010005 0x0000004a 454 0x00010006 0x00000052 455 0x00010007 0x0000005a 456 0x00010008 0x00000062 457 0x00010009 0x0000006a 458 /* Calibration data group 3 */ 459 0x00020000 0x00000021 460 0x00020001 0x0000002b 461 0x00020002 0x00000035 462 0x00020003 0x0000003e 463 0x00020004 0x00000048 464 0x00020005 0x00000052 465 0x00020006 0x0000005c 466 /* Calibration data group 4 */ 467 0x00030000 0x00000011 468 0x00030001 0x0000001a 469 0x00030002 0x00000024 470 0x00030003 0x0000002e 471 0x00030004 0x00000038 472 0x00030005 0x00000042 473 0x00030006 0x0000004c 474 0x00030007 0x00000056>; 475 big-endian; 476 #thermal-sensor-cells = <1>; 477 }; 478 479 dspi: spi@2100000 { 480 compatible = "fsl,ls1021a-v1.0-dspi"; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 reg = <0x0 0x2100000 0x0 0x10000>; 484 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 485 clock-names = "dspi"; 486 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 487 QORIQ_CLK_PLL_DIV(2)>; 488 spi-num-chipselects = <5>; 489 big-endian; 490 status = "disabled"; 491 }; 492 493 i2c0: i2c@2180000 { 494 compatible = "fsl,vf610-i2c"; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 reg = <0x0 0x2180000 0x0 0x10000>; 498 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 500 QORIQ_CLK_PLL_DIV(2)>; 501 dmas = <&edma0 1 39>, 502 <&edma0 1 38>; 503 dma-names = "tx", "rx"; 504 status = "disabled"; 505 }; 506 507 i2c1: i2c@2190000 { 508 compatible = "fsl,vf610-i2c"; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 reg = <0x0 0x2190000 0x0 0x10000>; 512 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 514 QORIQ_CLK_PLL_DIV(2)>; 515 status = "disabled"; 516 }; 517 518 i2c2: i2c@21a0000 { 519 compatible = "fsl,vf610-i2c"; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 reg = <0x0 0x21a0000 0x0 0x10000>; 523 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 525 QORIQ_CLK_PLL_DIV(2)>; 526 status = "disabled"; 527 }; 528 529 i2c3: i2c@21b0000 { 530 compatible = "fsl,vf610-i2c"; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 reg = <0x0 0x21b0000 0x0 0x10000>; 534 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 536 QORIQ_CLK_PLL_DIV(2)>; 537 status = "disabled"; 538 }; 539 540 duart0: serial@21c0500 { 541 compatible = "fsl,ns16550", "ns16550a"; 542 reg = <0x00 0x21c0500 0x0 0x100>; 543 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 545 QORIQ_CLK_PLL_DIV(2)>; 546 status = "disabled"; 547 }; 548 549 duart1: serial@21c0600 { 550 compatible = "fsl,ns16550", "ns16550a"; 551 reg = <0x00 0x21c0600 0x0 0x100>; 552 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 554 QORIQ_CLK_PLL_DIV(2)>; 555 status = "disabled"; 556 }; 557 558 duart2: serial@21d0500 { 559 compatible = "fsl,ns16550", "ns16550a"; 560 reg = <0x0 0x21d0500 0x0 0x100>; 561 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 563 QORIQ_CLK_PLL_DIV(2)>; 564 status = "disabled"; 565 }; 566 567 duart3: serial@21d0600 { 568 compatible = "fsl,ns16550", "ns16550a"; 569 reg = <0x0 0x21d0600 0x0 0x100>; 570 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 572 QORIQ_CLK_PLL_DIV(2)>; 573 status = "disabled"; 574 }; 575 576 gpio0: gpio@2300000 { 577 compatible = "fsl,qoriq-gpio"; 578 reg = <0x0 0x2300000 0x0 0x10000>; 579 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 580 gpio-controller; 581 #gpio-cells = <2>; 582 interrupt-controller; 583 #interrupt-cells = <2>; 584 }; 585 586 gpio1: gpio@2310000 { 587 compatible = "fsl,qoriq-gpio"; 588 reg = <0x0 0x2310000 0x0 0x10000>; 589 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 590 gpio-controller; 591 #gpio-cells = <2>; 592 interrupt-controller; 593 #interrupt-cells = <2>; 594 }; 595 596 gpio2: gpio@2320000 { 597 compatible = "fsl,qoriq-gpio"; 598 reg = <0x0 0x2320000 0x0 0x10000>; 599 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 600 gpio-controller; 601 #gpio-cells = <2>; 602 interrupt-controller; 603 #interrupt-cells = <2>; 604 }; 605 606 gpio3: gpio@2330000 { 607 compatible = "fsl,qoriq-gpio"; 608 reg = <0x0 0x2330000 0x0 0x10000>; 609 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 610 gpio-controller; 611 #gpio-cells = <2>; 612 interrupt-controller; 613 #interrupt-cells = <2>; 614 }; 615 616 lpuart0: serial@2950000 { 617 compatible = "fsl,ls1021a-lpuart"; 618 reg = <0x0 0x2950000 0x0 0x1000>; 619 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 621 QORIQ_CLK_PLL_DIV(1)>; 622 clock-names = "ipg"; 623 status = "disabled"; 624 }; 625 626 lpuart1: serial@2960000 { 627 compatible = "fsl,ls1021a-lpuart"; 628 reg = <0x0 0x2960000 0x0 0x1000>; 629 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 631 QORIQ_CLK_PLL_DIV(2)>; 632 clock-names = "ipg"; 633 status = "disabled"; 634 }; 635 636 lpuart2: serial@2970000 { 637 compatible = "fsl,ls1021a-lpuart"; 638 reg = <0x0 0x2970000 0x0 0x1000>; 639 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 641 QORIQ_CLK_PLL_DIV(2)>; 642 clock-names = "ipg"; 643 status = "disabled"; 644 }; 645 646 lpuart3: serial@2980000 { 647 compatible = "fsl,ls1021a-lpuart"; 648 reg = <0x0 0x2980000 0x0 0x1000>; 649 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 651 QORIQ_CLK_PLL_DIV(2)>; 652 clock-names = "ipg"; 653 status = "disabled"; 654 }; 655 656 lpuart4: serial@2990000 { 657 compatible = "fsl,ls1021a-lpuart"; 658 reg = <0x0 0x2990000 0x0 0x1000>; 659 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 661 QORIQ_CLK_PLL_DIV(2)>; 662 clock-names = "ipg"; 663 status = "disabled"; 664 }; 665 666 lpuart5: serial@29a0000 { 667 compatible = "fsl,ls1021a-lpuart"; 668 reg = <0x0 0x29a0000 0x0 0x1000>; 669 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 671 QORIQ_CLK_PLL_DIV(2)>; 672 clock-names = "ipg"; 673 status = "disabled"; 674 }; 675 676 wdog0: watchdog@2ad0000 { 677 compatible = "fsl,imx21-wdt"; 678 reg = <0x0 0x2ad0000 0x0 0x10000>; 679 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 681 QORIQ_CLK_PLL_DIV(2)>; 682 big-endian; 683 }; 684 685 edma0: edma@2c00000 { 686 #dma-cells = <2>; 687 compatible = "fsl,vf610-edma"; 688 reg = <0x0 0x2c00000 0x0 0x10000>, 689 <0x0 0x2c10000 0x0 0x10000>, 690 <0x0 0x2c20000 0x0 0x10000>; 691 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 693 interrupt-names = "edma-tx", "edma-err"; 694 dma-channels = <32>; 695 big-endian; 696 clock-names = "dmamux0", "dmamux1"; 697 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 698 QORIQ_CLK_PLL_DIV(2)>, 699 <&clockgen QORIQ_CLK_PLATFORM_PLL 700 QORIQ_CLK_PLL_DIV(2)>; 701 }; 702 703 usb0: usb@2f00000 { 704 compatible = "snps,dwc3"; 705 reg = <0x0 0x2f00000 0x0 0x10000>; 706 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 707 dr_mode = "host"; 708 snps,quirk-frame-length-adjustment = <0x20>; 709 snps,dis_rxdet_inp3_quirk; 710 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 711 }; 712 713 usb1: usb@3000000 { 714 compatible = "snps,dwc3"; 715 reg = <0x0 0x3000000 0x0 0x10000>; 716 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 717 dr_mode = "host"; 718 snps,quirk-frame-length-adjustment = <0x20>; 719 snps,dis_rxdet_inp3_quirk; 720 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 721 }; 722 723 usb2: usb@3100000 { 724 compatible = "snps,dwc3"; 725 reg = <0x0 0x3100000 0x0 0x10000>; 726 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 727 dr_mode = "host"; 728 snps,quirk-frame-length-adjustment = <0x20>; 729 snps,dis_rxdet_inp3_quirk; 730 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 731 }; 732 733 sata: sata@3200000 { 734 compatible = "fsl,ls1046a-ahci"; 735 reg = <0x0 0x3200000 0x0 0x10000>, 736 <0x0 0x20140520 0x0 0x4>; 737 reg-names = "ahci", "sata-ecc"; 738 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 740 QORIQ_CLK_PLL_DIV(2)>; 741 }; 742 743 msi1: msi-controller@1580000 { 744 compatible = "fsl,ls1046a-msi"; 745 msi-controller; 746 reg = <0x0 0x1580000 0x0 0x10000>; 747 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 751 }; 752 753 msi2: msi-controller@1590000 { 754 compatible = "fsl,ls1046a-msi"; 755 msi-controller; 756 reg = <0x0 0x1590000 0x0 0x10000>; 757 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 761 }; 762 763 msi3: msi-controller@15a0000 { 764 compatible = "fsl,ls1046a-msi"; 765 msi-controller; 766 reg = <0x0 0x15a0000 0x0 0x10000>; 767 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 771 }; 772 773 pcie1: pcie@3400000 { 774 compatible = "fsl,ls1046a-pcie"; 775 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 776 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 777 reg-names = "regs", "config"; 778 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 779 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 780 interrupt-names = "aer", "pme"; 781 #address-cells = <3>; 782 #size-cells = <2>; 783 device_type = "pci"; 784 dma-coherent; 785 num-viewport = <8>; 786 bus-range = <0x0 0xff>; 787 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 788 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 789 msi-parent = <&msi1>, <&msi2>, <&msi3>; 790 #interrupt-cells = <1>; 791 interrupt-map-mask = <0 0 0 7>; 792 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 793 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 794 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 795 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 796 status = "disabled"; 797 }; 798 799 pcie_ep1: pcie_ep@3400000 { 800 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 801 reg = <0x00 0x03400000 0x0 0x00100000 802 0x40 0x00000000 0x8 0x00000000>; 803 reg-names = "regs", "addr_space"; 804 num-ib-windows = <6>; 805 num-ob-windows = <8>; 806 status = "disabled"; 807 }; 808 809 pcie2: pcie@3500000 { 810 compatible = "fsl,ls1046a-pcie"; 811 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 812 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 813 reg-names = "regs", "config"; 814 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 815 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 816 interrupt-names = "aer", "pme"; 817 #address-cells = <3>; 818 #size-cells = <2>; 819 device_type = "pci"; 820 dma-coherent; 821 num-viewport = <8>; 822 bus-range = <0x0 0xff>; 823 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 824 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 825 msi-parent = <&msi2>, <&msi3>, <&msi1>; 826 #interrupt-cells = <1>; 827 interrupt-map-mask = <0 0 0 7>; 828 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 829 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 830 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 831 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 832 status = "disabled"; 833 }; 834 835 pcie_ep2: pcie_ep@3500000 { 836 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 837 reg = <0x00 0x03500000 0x0 0x00100000 838 0x48 0x00000000 0x8 0x00000000>; 839 reg-names = "regs", "addr_space"; 840 num-ib-windows = <6>; 841 num-ob-windows = <8>; 842 status = "disabled"; 843 }; 844 845 pcie3: pcie@3600000 { 846 compatible = "fsl,ls1046a-pcie"; 847 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 848 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 849 reg-names = "regs", "config"; 850 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 851 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 852 interrupt-names = "aer", "pme"; 853 #address-cells = <3>; 854 #size-cells = <2>; 855 device_type = "pci"; 856 dma-coherent; 857 num-viewport = <8>; 858 bus-range = <0x0 0xff>; 859 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 860 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 861 msi-parent = <&msi3>, <&msi1>, <&msi2>; 862 #interrupt-cells = <1>; 863 interrupt-map-mask = <0 0 0 7>; 864 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 865 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 866 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 867 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 868 status = "disabled"; 869 }; 870 871 pcie_ep3: pcie_ep@3600000 { 872 compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; 873 reg = <0x00 0x03600000 0x0 0x00100000 874 0x50 0x00000000 0x8 0x00000000>; 875 reg-names = "regs", "addr_space"; 876 num-ib-windows = <6>; 877 num-ob-windows = <8>; 878 status = "disabled"; 879 }; 880 881 qdma: dma-controller@8380000 { 882 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; 883 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 884 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 885 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 886 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 891 interrupt-names = "qdma-error", "qdma-queue0", 892 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 893 dma-channels = <8>; 894 block-number = <1>; 895 block-offset = <0x10000>; 896 fsl,dma-queues = <2>; 897 status-sizes = <64>; 898 queue-sizes = <64 64>; 899 big-endian; 900 }; 901 902 rcpm: power-controller@1ee2140 { 903 compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+"; 904 reg = <0x0 0x1ee2140 0x0 0x4>; 905 #fsl,rcpm-wakeup-cells = <1>; 906 }; 907 908 ftm_alarm0: timer@29d0000 { 909 compatible = "fsl,ls1046a-ftm-alarm"; 910 reg = <0x0 0x29d0000 0x0 0x10000>; 911 fsl,rcpm-wakeup = <&rcpm 0x20000>; 912 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 913 big-endian; 914 }; 915 }; 916 917 reserved-memory { 918 #address-cells = <2>; 919 #size-cells = <2>; 920 ranges; 921 922 bman_fbpr: bman-fbpr { 923 compatible = "shared-dma-pool"; 924 size = <0 0x1000000>; 925 alignment = <0 0x1000000>; 926 no-map; 927 }; 928 929 qman_fqd: qman-fqd { 930 compatible = "shared-dma-pool"; 931 size = <0 0x800000>; 932 alignment = <0 0x800000>; 933 no-map; 934 }; 935 936 qman_pfdr: qman-pfdr { 937 compatible = "shared-dma-pool"; 938 size = <0 0x2000000>; 939 alignment = <0 0x2000000>; 940 no-map; 941 }; 942 }; 943 944 firmware { 945 optee { 946 compatible = "linaro,optee-tz"; 947 method = "smc"; 948 }; 949 }; 950}; 951 952#include "qoriq-qman-portals.dtsi" 953#include "qoriq-bman-portals.dtsi" 954