1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1046A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2020 NXP 7 * 8 * Mingkai Hu <mingkai.hu@nxp.com> 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "fsl,ls1046a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 crypto = &crypto; 23 fman0 = &fman0; 24 ethernet0 = &enet0; 25 ethernet1 = &enet1; 26 ethernet2 = &enet2; 27 ethernet3 = &enet3; 28 ethernet4 = &enet4; 29 ethernet5 = &enet5; 30 ethernet6 = &enet6; 31 ethernet7 = &enet7; 32 rtc1 = &ftm_alarm0; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a72"; 42 reg = <0x0>; 43 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 44 next-level-cache = <&l2>; 45 cpu-idle-states = <&CPU_PH20>; 46 #cooling-cells = <2>; 47 }; 48 49 cpu1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a72"; 52 reg = <0x1>; 53 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 54 next-level-cache = <&l2>; 55 cpu-idle-states = <&CPU_PH20>; 56 #cooling-cells = <2>; 57 }; 58 59 cpu2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a72"; 62 reg = <0x2>; 63 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 64 next-level-cache = <&l2>; 65 cpu-idle-states = <&CPU_PH20>; 66 #cooling-cells = <2>; 67 }; 68 69 cpu3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a72"; 72 reg = <0x3>; 73 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 74 next-level-cache = <&l2>; 75 cpu-idle-states = <&CPU_PH20>; 76 #cooling-cells = <2>; 77 }; 78 79 l2: l2-cache { 80 compatible = "cache"; 81 }; 82 }; 83 84 idle-states { 85 /* 86 * PSCI node is not added default, U-boot will add missing 87 * parts if it determines to use PSCI. 88 */ 89 entry-method = "psci"; 90 91 CPU_PH20: cpu-ph20 { 92 compatible = "arm,idle-state"; 93 idle-state-name = "PH20"; 94 arm,psci-suspend-param = <0x0>; 95 entry-latency-us = <1000>; 96 exit-latency-us = <1000>; 97 min-residency-us = <3000>; 98 }; 99 }; 100 101 memory@80000000 { 102 device_type = "memory"; 103 /* Real size will be filled by bootloader */ 104 reg = <0x0 0x80000000 0x0 0x0>; 105 }; 106 107 sysclk: sysclk { 108 compatible = "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <100000000>; 111 clock-output-names = "sysclk"; 112 }; 113 114 reboot { 115 compatible ="syscon-reboot"; 116 regmap = <&dcfg>; 117 offset = <0xb0>; 118 mask = <0x02>; 119 }; 120 121 thermal-zones { 122 ddr-controller { 123 polling-delay-passive = <1000>; 124 polling-delay = <5000>; 125 thermal-sensors = <&tmu 0>; 126 127 trips { 128 ddr-ctrler-alert { 129 temperature = <85000>; 130 hysteresis = <2000>; 131 type = "passive"; 132 }; 133 134 ddr-ctrler-crit { 135 temperature = <95000>; 136 hysteresis = <2000>; 137 type = "critical"; 138 }; 139 }; 140 }; 141 142 serdes { 143 polling-delay-passive = <1000>; 144 polling-delay = <5000>; 145 thermal-sensors = <&tmu 1>; 146 147 trips { 148 serdes-alert { 149 temperature = <85000>; 150 hysteresis = <2000>; 151 type = "passive"; 152 }; 153 154 serdes-crit { 155 temperature = <95000>; 156 hysteresis = <2000>; 157 type = "critical"; 158 }; 159 }; 160 }; 161 162 fman { 163 polling-delay-passive = <1000>; 164 polling-delay = <5000>; 165 thermal-sensors = <&tmu 2>; 166 167 trips { 168 fman-alert { 169 temperature = <85000>; 170 hysteresis = <2000>; 171 type = "passive"; 172 }; 173 174 fman-crit { 175 temperature = <95000>; 176 hysteresis = <2000>; 177 type = "critical"; 178 }; 179 }; 180 }; 181 182 core-cluster { 183 polling-delay-passive = <1000>; 184 polling-delay = <5000>; 185 thermal-sensors = <&tmu 3>; 186 187 trips { 188 core_cluster_alert: core-cluster-alert { 189 temperature = <85000>; 190 hysteresis = <2000>; 191 type = "passive"; 192 }; 193 194 core_cluster_crit: core-cluster-crit { 195 temperature = <95000>; 196 hysteresis = <2000>; 197 type = "critical"; 198 }; 199 }; 200 201 cooling-maps { 202 map0 { 203 trip = <&core_cluster_alert>; 204 cooling-device = 205 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 206 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 207 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 208 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 209 }; 210 }; 211 }; 212 213 sec { 214 polling-delay-passive = <1000>; 215 polling-delay = <5000>; 216 thermal-sensors = <&tmu 4>; 217 218 trips { 219 sec-alert { 220 temperature = <85000>; 221 hysteresis = <2000>; 222 type = "passive"; 223 }; 224 225 sec-crit { 226 temperature = <95000>; 227 hysteresis = <2000>; 228 type = "critical"; 229 }; 230 }; 231 }; 232 }; 233 234 timer { 235 compatible = "arm,armv8-timer"; 236 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) | 237 IRQ_TYPE_LEVEL_LOW)>, 238 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) | 239 IRQ_TYPE_LEVEL_LOW)>, 240 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) | 241 IRQ_TYPE_LEVEL_LOW)>, 242 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) | 243 IRQ_TYPE_LEVEL_LOW)>; 244 }; 245 246 pmu { 247 compatible = "arm,cortex-a72-pmu"; 248 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 252 interrupt-affinity = <&cpu0>, 253 <&cpu1>, 254 <&cpu2>, 255 <&cpu3>; 256 }; 257 258 gic: interrupt-controller@1400000 { 259 compatible = "arm,gic-400"; 260 #interrupt-cells = <3>; 261 interrupt-controller; 262 reg = <0x0 0x1410000 0 0x10000>, /* GICD */ 263 <0x0 0x1420000 0 0x20000>, /* GICC */ 264 <0x0 0x1440000 0 0x20000>, /* GICH */ 265 <0x0 0x1460000 0 0x20000>; /* GICV */ 266 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 267 IRQ_TYPE_LEVEL_LOW)>; 268 }; 269 270 soc: soc { 271 compatible = "simple-bus"; 272 #address-cells = <2>; 273 #size-cells = <2>; 274 ranges; 275 276 ddr: memory-controller@1080000 { 277 compatible = "fsl,qoriq-memory-controller"; 278 reg = <0x0 0x1080000 0x0 0x1000>; 279 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 280 big-endian; 281 }; 282 283 ifc: ifc@1530000 { 284 compatible = "fsl,ifc", "simple-bus"; 285 reg = <0x0 0x1530000 0x0 0x10000>; 286 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 287 status = "disabled"; 288 }; 289 290 qspi: spi@1550000 { 291 compatible = "fsl,ls1021a-qspi"; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 reg = <0x0 0x1550000 0x0 0x10000>, 295 <0x0 0x40000000 0x0 0x10000000>; 296 reg-names = "QuadSPI", "QuadSPI-memory"; 297 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 298 clock-names = "qspi_en", "qspi"; 299 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 300 QORIQ_CLK_PLL_DIV(2)>, 301 <&clockgen QORIQ_CLK_PLATFORM_PLL 302 QORIQ_CLK_PLL_DIV(2)>; 303 status = "disabled"; 304 }; 305 306 esdhc: esdhc@1560000 { 307 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; 308 reg = <0x0 0x1560000 0x0 0x10000>; 309 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 311 voltage-ranges = <1800 1800 3300 3300>; 312 sdhci,auto-cmd12; 313 big-endian; 314 bus-width = <4>; 315 }; 316 317 scfg: scfg@1570000 { 318 compatible = "fsl,ls1046a-scfg", "syscon"; 319 reg = <0x0 0x1570000 0x0 0x10000>; 320 big-endian; 321 #address-cells = <1>; 322 #size-cells = <1>; 323 ranges = <0x0 0x0 0x1570000 0x10000>; 324 325 extirq: interrupt-controller@1ac { 326 compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq"; 327 #interrupt-cells = <2>; 328 #address-cells = <0>; 329 interrupt-controller; 330 reg = <0x1ac 4>; 331 interrupt-map = 332 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 333 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 334 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 335 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 336 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 337 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 338 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 339 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 340 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 341 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 342 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 343 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 344 interrupt-map-mask = <0xffffffff 0x0>; 345 }; 346 }; 347 348 crypto: crypto@1700000 { 349 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 350 "fsl,sec-v4.0"; 351 fsl,sec-era = <8>; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges = <0x0 0x00 0x1700000 0x100000>; 355 reg = <0x00 0x1700000 0x0 0x100000>; 356 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 357 dma-coherent; 358 359 sec_jr0: jr@10000 { 360 compatible = "fsl,sec-v5.4-job-ring", 361 "fsl,sec-v5.0-job-ring", 362 "fsl,sec-v4.0-job-ring"; 363 reg = <0x10000 0x10000>; 364 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 365 }; 366 367 sec_jr1: jr@20000 { 368 compatible = "fsl,sec-v5.4-job-ring", 369 "fsl,sec-v5.0-job-ring", 370 "fsl,sec-v4.0-job-ring"; 371 reg = <0x20000 0x10000>; 372 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 373 }; 374 375 sec_jr2: jr@30000 { 376 compatible = "fsl,sec-v5.4-job-ring", 377 "fsl,sec-v5.0-job-ring", 378 "fsl,sec-v4.0-job-ring"; 379 reg = <0x30000 0x10000>; 380 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 381 }; 382 383 sec_jr3: jr@40000 { 384 compatible = "fsl,sec-v5.4-job-ring", 385 "fsl,sec-v5.0-job-ring", 386 "fsl,sec-v4.0-job-ring"; 387 reg = <0x40000 0x10000>; 388 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 389 }; 390 }; 391 392 qman: qman@1880000 { 393 compatible = "fsl,qman"; 394 reg = <0x0 0x1880000 0x0 0x10000>; 395 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 396 memory-region = <&qman_fqd &qman_pfdr>; 397 398 }; 399 400 bman: bman@1890000 { 401 compatible = "fsl,bman"; 402 reg = <0x0 0x1890000 0x0 0x10000>; 403 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 404 memory-region = <&bman_fbpr>; 405 406 }; 407 408 qportals: qman-portals@500000000 { 409 ranges = <0x0 0x5 0x00000000 0x8000000>; 410 }; 411 412 bportals: bman-portals@508000000 { 413 ranges = <0x0 0x5 0x08000000 0x8000000>; 414 }; 415 416 dcfg: dcfg@1ee0000 { 417 compatible = "fsl,ls1046a-dcfg", "syscon"; 418 reg = <0x0 0x1ee0000 0x0 0x1000>; 419 big-endian; 420 }; 421 422 clockgen: clocking@1ee1000 { 423 compatible = "fsl,ls1046a-clockgen"; 424 reg = <0x0 0x1ee1000 0x0 0x1000>; 425 #clock-cells = <2>; 426 clocks = <&sysclk>; 427 }; 428 429 tmu: tmu@1f00000 { 430 compatible = "fsl,qoriq-tmu"; 431 reg = <0x0 0x1f00000 0x0 0x10000>; 432 interrupts = <0 33 0x4>; 433 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 434 fsl,tmu-calibration = 435 /* Calibration data group 1 */ 436 <0x00000000 0x00000023 437 0x00000001 0x00000029 438 0x00000002 0x0000002f 439 0x00000003 0x00000036 440 0x00000004 0x0000003c 441 0x00000005 0x00000042 442 0x00000006 0x00000049 443 0x00000007 0x0000004f 444 0x00000008 0x00000055 445 0x00000009 0x0000005c 446 0x0000000a 0x00000062 447 0x0000000b 0x00000068 448 /* Calibration data group 2 */ 449 0x00010000 0x00000022 450 0x00010001 0x0000002a 451 0x00010002 0x00000032 452 0x00010003 0x0000003a 453 0x00010004 0x00000042 454 0x00010005 0x0000004a 455 0x00010006 0x00000052 456 0x00010007 0x0000005a 457 0x00010008 0x00000062 458 0x00010009 0x0000006a 459 /* Calibration data group 3 */ 460 0x00020000 0x00000021 461 0x00020001 0x0000002b 462 0x00020002 0x00000035 463 0x00020003 0x0000003e 464 0x00020004 0x00000048 465 0x00020005 0x00000052 466 0x00020006 0x0000005c 467 /* Calibration data group 4 */ 468 0x00030000 0x00000011 469 0x00030001 0x0000001a 470 0x00030002 0x00000024 471 0x00030003 0x0000002e 472 0x00030004 0x00000038 473 0x00030005 0x00000042 474 0x00030006 0x0000004c 475 0x00030007 0x00000056>; 476 big-endian; 477 #thermal-sensor-cells = <1>; 478 }; 479 480 dspi: spi@2100000 { 481 compatible = "fsl,ls1021a-v1.0-dspi"; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 reg = <0x0 0x2100000 0x0 0x10000>; 485 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 486 clock-names = "dspi"; 487 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 488 QORIQ_CLK_PLL_DIV(2)>; 489 spi-num-chipselects = <5>; 490 big-endian; 491 status = "disabled"; 492 }; 493 494 i2c0: i2c@2180000 { 495 compatible = "fsl,vf610-i2c"; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 reg = <0x0 0x2180000 0x0 0x10000>; 499 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 501 QORIQ_CLK_PLL_DIV(2)>; 502 dmas = <&edma0 1 38>, 503 <&edma0 1 39>; 504 dma-names = "rx", "tx"; 505 status = "disabled"; 506 }; 507 508 i2c1: i2c@2190000 { 509 compatible = "fsl,vf610-i2c"; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 reg = <0x0 0x2190000 0x0 0x10000>; 513 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 515 QORIQ_CLK_PLL_DIV(2)>; 516 status = "disabled"; 517 }; 518 519 i2c2: i2c@21a0000 { 520 compatible = "fsl,vf610-i2c"; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 reg = <0x0 0x21a0000 0x0 0x10000>; 524 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 526 QORIQ_CLK_PLL_DIV(2)>; 527 status = "disabled"; 528 }; 529 530 i2c3: i2c@21b0000 { 531 compatible = "fsl,vf610-i2c"; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 reg = <0x0 0x21b0000 0x0 0x10000>; 535 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 537 QORIQ_CLK_PLL_DIV(2)>; 538 status = "disabled"; 539 }; 540 541 duart0: serial@21c0500 { 542 compatible = "fsl,ns16550", "ns16550a"; 543 reg = <0x00 0x21c0500 0x0 0x100>; 544 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 545 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 546 QORIQ_CLK_PLL_DIV(2)>; 547 status = "disabled"; 548 }; 549 550 duart1: serial@21c0600 { 551 compatible = "fsl,ns16550", "ns16550a"; 552 reg = <0x00 0x21c0600 0x0 0x100>; 553 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 555 QORIQ_CLK_PLL_DIV(2)>; 556 status = "disabled"; 557 }; 558 559 duart2: serial@21d0500 { 560 compatible = "fsl,ns16550", "ns16550a"; 561 reg = <0x0 0x21d0500 0x0 0x100>; 562 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 564 QORIQ_CLK_PLL_DIV(2)>; 565 status = "disabled"; 566 }; 567 568 duart3: serial@21d0600 { 569 compatible = "fsl,ns16550", "ns16550a"; 570 reg = <0x0 0x21d0600 0x0 0x100>; 571 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 573 QORIQ_CLK_PLL_DIV(2)>; 574 status = "disabled"; 575 }; 576 577 gpio0: gpio@2300000 { 578 compatible = "fsl,qoriq-gpio"; 579 reg = <0x0 0x2300000 0x0 0x10000>; 580 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 581 gpio-controller; 582 #gpio-cells = <2>; 583 interrupt-controller; 584 #interrupt-cells = <2>; 585 }; 586 587 gpio1: gpio@2310000 { 588 compatible = "fsl,qoriq-gpio"; 589 reg = <0x0 0x2310000 0x0 0x10000>; 590 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 591 gpio-controller; 592 #gpio-cells = <2>; 593 interrupt-controller; 594 #interrupt-cells = <2>; 595 }; 596 597 gpio2: gpio@2320000 { 598 compatible = "fsl,qoriq-gpio"; 599 reg = <0x0 0x2320000 0x0 0x10000>; 600 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 601 gpio-controller; 602 #gpio-cells = <2>; 603 interrupt-controller; 604 #interrupt-cells = <2>; 605 }; 606 607 gpio3: gpio@2330000 { 608 compatible = "fsl,qoriq-gpio"; 609 reg = <0x0 0x2330000 0x0 0x10000>; 610 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 611 gpio-controller; 612 #gpio-cells = <2>; 613 interrupt-controller; 614 #interrupt-cells = <2>; 615 }; 616 617 lpuart0: serial@2950000 { 618 compatible = "fsl,ls1021a-lpuart"; 619 reg = <0x0 0x2950000 0x0 0x1000>; 620 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 622 QORIQ_CLK_PLL_DIV(1)>; 623 clock-names = "ipg"; 624 status = "disabled"; 625 }; 626 627 lpuart1: serial@2960000 { 628 compatible = "fsl,ls1021a-lpuart"; 629 reg = <0x0 0x2960000 0x0 0x1000>; 630 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 632 QORIQ_CLK_PLL_DIV(2)>; 633 clock-names = "ipg"; 634 status = "disabled"; 635 }; 636 637 lpuart2: serial@2970000 { 638 compatible = "fsl,ls1021a-lpuart"; 639 reg = <0x0 0x2970000 0x0 0x1000>; 640 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 642 QORIQ_CLK_PLL_DIV(2)>; 643 clock-names = "ipg"; 644 status = "disabled"; 645 }; 646 647 lpuart3: serial@2980000 { 648 compatible = "fsl,ls1021a-lpuart"; 649 reg = <0x0 0x2980000 0x0 0x1000>; 650 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 652 QORIQ_CLK_PLL_DIV(2)>; 653 clock-names = "ipg"; 654 status = "disabled"; 655 }; 656 657 lpuart4: serial@2990000 { 658 compatible = "fsl,ls1021a-lpuart"; 659 reg = <0x0 0x2990000 0x0 0x1000>; 660 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 662 QORIQ_CLK_PLL_DIV(2)>; 663 clock-names = "ipg"; 664 status = "disabled"; 665 }; 666 667 lpuart5: serial@29a0000 { 668 compatible = "fsl,ls1021a-lpuart"; 669 reg = <0x0 0x29a0000 0x0 0x1000>; 670 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 672 QORIQ_CLK_PLL_DIV(2)>; 673 clock-names = "ipg"; 674 status = "disabled"; 675 }; 676 677 wdog0: watchdog@2ad0000 { 678 compatible = "fsl,imx21-wdt"; 679 reg = <0x0 0x2ad0000 0x0 0x10000>; 680 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 682 QORIQ_CLK_PLL_DIV(2)>; 683 big-endian; 684 }; 685 686 edma0: edma@2c00000 { 687 #dma-cells = <2>; 688 compatible = "fsl,vf610-edma"; 689 reg = <0x0 0x2c00000 0x0 0x10000>, 690 <0x0 0x2c10000 0x0 0x10000>, 691 <0x0 0x2c20000 0x0 0x10000>; 692 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 694 interrupt-names = "edma-tx", "edma-err"; 695 dma-channels = <32>; 696 big-endian; 697 clock-names = "dmamux0", "dmamux1"; 698 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 699 QORIQ_CLK_PLL_DIV(2)>, 700 <&clockgen QORIQ_CLK_PLATFORM_PLL 701 QORIQ_CLK_PLL_DIV(2)>; 702 }; 703 704 usb0: usb@2f00000 { 705 compatible = "snps,dwc3"; 706 reg = <0x0 0x2f00000 0x0 0x10000>; 707 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 708 dr_mode = "host"; 709 snps,quirk-frame-length-adjustment = <0x20>; 710 snps,dis_rxdet_inp3_quirk; 711 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 712 }; 713 714 usb1: usb@3000000 { 715 compatible = "snps,dwc3"; 716 reg = <0x0 0x3000000 0x0 0x10000>; 717 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 718 dr_mode = "host"; 719 snps,quirk-frame-length-adjustment = <0x20>; 720 snps,dis_rxdet_inp3_quirk; 721 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 722 }; 723 724 usb2: usb@3100000 { 725 compatible = "snps,dwc3"; 726 reg = <0x0 0x3100000 0x0 0x10000>; 727 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 728 dr_mode = "host"; 729 snps,quirk-frame-length-adjustment = <0x20>; 730 snps,dis_rxdet_inp3_quirk; 731 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 732 }; 733 734 sata: sata@3200000 { 735 compatible = "fsl,ls1046a-ahci"; 736 reg = <0x0 0x3200000 0x0 0x10000>, 737 <0x0 0x20140520 0x0 0x4>; 738 reg-names = "ahci", "sata-ecc"; 739 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 741 QORIQ_CLK_PLL_DIV(2)>; 742 }; 743 744 msi1: msi-controller@1580000 { 745 compatible = "fsl,ls1046a-msi"; 746 msi-controller; 747 reg = <0x0 0x1580000 0x0 0x10000>; 748 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 752 }; 753 754 msi2: msi-controller@1590000 { 755 compatible = "fsl,ls1046a-msi"; 756 msi-controller; 757 reg = <0x0 0x1590000 0x0 0x10000>; 758 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 762 }; 763 764 msi3: msi-controller@15a0000 { 765 compatible = "fsl,ls1046a-msi"; 766 msi-controller; 767 reg = <0x0 0x15a0000 0x0 0x10000>; 768 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 772 }; 773 774 pcie1: pcie@3400000 { 775 compatible = "fsl,ls1046a-pcie"; 776 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 777 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 778 reg-names = "regs", "config"; 779 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 780 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 781 interrupt-names = "aer", "pme"; 782 #address-cells = <3>; 783 #size-cells = <2>; 784 device_type = "pci"; 785 dma-coherent; 786 num-viewport = <8>; 787 bus-range = <0x0 0xff>; 788 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 789 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 790 msi-parent = <&msi1>, <&msi2>, <&msi3>; 791 #interrupt-cells = <1>; 792 interrupt-map-mask = <0 0 0 7>; 793 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 794 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 795 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 796 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 797 status = "disabled"; 798 }; 799 800 pcie_ep1: pcie_ep@3400000 { 801 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 802 reg = <0x00 0x03400000 0x0 0x00100000>, 803 <0x40 0x00000000 0x8 0x00000000>; 804 reg-names = "regs", "addr_space"; 805 num-ib-windows = <6>; 806 num-ob-windows = <8>; 807 status = "disabled"; 808 }; 809 810 pcie2: pcie@3500000 { 811 compatible = "fsl,ls1046a-pcie"; 812 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 813 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 814 reg-names = "regs", "config"; 815 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 816 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 817 interrupt-names = "aer", "pme"; 818 #address-cells = <3>; 819 #size-cells = <2>; 820 device_type = "pci"; 821 dma-coherent; 822 num-viewport = <8>; 823 bus-range = <0x0 0xff>; 824 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 825 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 826 msi-parent = <&msi2>, <&msi3>, <&msi1>; 827 #interrupt-cells = <1>; 828 interrupt-map-mask = <0 0 0 7>; 829 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 830 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 831 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 832 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 833 status = "disabled"; 834 }; 835 836 pcie_ep2: pcie_ep@3500000 { 837 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 838 reg = <0x00 0x03500000 0x0 0x00100000>, 839 <0x48 0x00000000 0x8 0x00000000>; 840 reg-names = "regs", "addr_space"; 841 num-ib-windows = <6>; 842 num-ob-windows = <8>; 843 status = "disabled"; 844 }; 845 846 pcie3: pcie@3600000 { 847 compatible = "fsl,ls1046a-pcie"; 848 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 849 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 850 reg-names = "regs", "config"; 851 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 852 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 853 interrupt-names = "aer", "pme"; 854 #address-cells = <3>; 855 #size-cells = <2>; 856 device_type = "pci"; 857 dma-coherent; 858 num-viewport = <8>; 859 bus-range = <0x0 0xff>; 860 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 861 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 862 msi-parent = <&msi3>, <&msi1>, <&msi2>; 863 #interrupt-cells = <1>; 864 interrupt-map-mask = <0 0 0 7>; 865 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 866 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 867 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 868 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 869 status = "disabled"; 870 }; 871 872 pcie_ep3: pcie_ep@3600000 { 873 compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; 874 reg = <0x00 0x03600000 0x0 0x00100000>, 875 <0x50 0x00000000 0x8 0x00000000>; 876 reg-names = "regs", "addr_space"; 877 num-ib-windows = <6>; 878 num-ob-windows = <8>; 879 status = "disabled"; 880 }; 881 882 qdma: dma-controller@8380000 { 883 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; 884 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 885 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 886 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 887 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 892 interrupt-names = "qdma-error", "qdma-queue0", 893 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 894 dma-channels = <8>; 895 block-number = <1>; 896 block-offset = <0x10000>; 897 fsl,dma-queues = <2>; 898 status-sizes = <64>; 899 queue-sizes = <64 64>; 900 big-endian; 901 }; 902 903 rcpm: power-controller@1ee2140 { 904 compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+"; 905 reg = <0x0 0x1ee2140 0x0 0x4>; 906 #fsl,rcpm-wakeup-cells = <1>; 907 }; 908 909 ftm_alarm0: timer@29d0000 { 910 compatible = "fsl,ls1046a-ftm-alarm"; 911 reg = <0x0 0x29d0000 0x0 0x10000>; 912 fsl,rcpm-wakeup = <&rcpm 0x20000>; 913 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 914 big-endian; 915 }; 916 }; 917 918 reserved-memory { 919 #address-cells = <2>; 920 #size-cells = <2>; 921 ranges; 922 923 bman_fbpr: bman-fbpr { 924 compatible = "shared-dma-pool"; 925 size = <0 0x1000000>; 926 alignment = <0 0x1000000>; 927 no-map; 928 }; 929 930 qman_fqd: qman-fqd { 931 compatible = "shared-dma-pool"; 932 size = <0 0x800000>; 933 alignment = <0 0x800000>; 934 no-map; 935 }; 936 937 qman_pfdr: qman-pfdr { 938 compatible = "shared-dma-pool"; 939 size = <0 0x2000000>; 940 alignment = <0 0x2000000>; 941 no-map; 942 }; 943 }; 944 945 firmware { 946 optee { 947 compatible = "linaro,optee-tz"; 948 method = "smc"; 949 }; 950 }; 951}; 952 953#include "qoriq-qman-portals.dtsi" 954#include "qoriq-bman-portals.dtsi" 955