1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1046A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2020 NXP 7 * 8 * Mingkai Hu <mingkai.hu@nxp.com> 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "fsl,ls1046a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 crypto = &crypto; 23 fman0 = &fman0; 24 ethernet0 = &enet0; 25 ethernet1 = &enet1; 26 ethernet2 = &enet2; 27 ethernet3 = &enet3; 28 ethernet4 = &enet4; 29 ethernet5 = &enet5; 30 ethernet6 = &enet6; 31 ethernet7 = &enet7; 32 rtc1 = &ftm_alarm0; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a72"; 42 reg = <0x0>; 43 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 44 next-level-cache = <&l2>; 45 cpu-idle-states = <&CPU_PH20>; 46 #cooling-cells = <2>; 47 }; 48 49 cpu1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a72"; 52 reg = <0x1>; 53 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 54 next-level-cache = <&l2>; 55 cpu-idle-states = <&CPU_PH20>; 56 #cooling-cells = <2>; 57 }; 58 59 cpu2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a72"; 62 reg = <0x2>; 63 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 64 next-level-cache = <&l2>; 65 cpu-idle-states = <&CPU_PH20>; 66 #cooling-cells = <2>; 67 }; 68 69 cpu3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a72"; 72 reg = <0x3>; 73 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 74 next-level-cache = <&l2>; 75 cpu-idle-states = <&CPU_PH20>; 76 #cooling-cells = <2>; 77 }; 78 79 l2: l2-cache { 80 compatible = "cache"; 81 }; 82 }; 83 84 idle-states { 85 /* 86 * PSCI node is not added default, U-boot will add missing 87 * parts if it determines to use PSCI. 88 */ 89 entry-method = "psci"; 90 91 CPU_PH20: cpu-ph20 { 92 compatible = "arm,idle-state"; 93 idle-state-name = "PH20"; 94 arm,psci-suspend-param = <0x0>; 95 entry-latency-us = <1000>; 96 exit-latency-us = <1000>; 97 min-residency-us = <3000>; 98 }; 99 }; 100 101 memory@80000000 { 102 device_type = "memory"; 103 /* Real size will be filled by bootloader */ 104 reg = <0x0 0x80000000 0x0 0x0>; 105 }; 106 107 sysclk: sysclk { 108 compatible = "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <100000000>; 111 clock-output-names = "sysclk"; 112 }; 113 114 reboot { 115 compatible = "syscon-reboot"; 116 regmap = <&dcfg>; 117 offset = <0xb0>; 118 mask = <0x02>; 119 }; 120 121 thermal-zones { 122 ddr-controller { 123 polling-delay-passive = <1000>; 124 polling-delay = <5000>; 125 thermal-sensors = <&tmu 0>; 126 127 trips { 128 ddr-ctrler-alert { 129 temperature = <85000>; 130 hysteresis = <2000>; 131 type = "passive"; 132 }; 133 134 ddr-ctrler-crit { 135 temperature = <95000>; 136 hysteresis = <2000>; 137 type = "critical"; 138 }; 139 }; 140 }; 141 142 serdes { 143 polling-delay-passive = <1000>; 144 polling-delay = <5000>; 145 thermal-sensors = <&tmu 1>; 146 147 trips { 148 serdes-alert { 149 temperature = <85000>; 150 hysteresis = <2000>; 151 type = "passive"; 152 }; 153 154 serdes-crit { 155 temperature = <95000>; 156 hysteresis = <2000>; 157 type = "critical"; 158 }; 159 }; 160 }; 161 162 fman { 163 polling-delay-passive = <1000>; 164 polling-delay = <5000>; 165 thermal-sensors = <&tmu 2>; 166 167 trips { 168 fman-alert { 169 temperature = <85000>; 170 hysteresis = <2000>; 171 type = "passive"; 172 }; 173 174 fman-crit { 175 temperature = <95000>; 176 hysteresis = <2000>; 177 type = "critical"; 178 }; 179 }; 180 }; 181 182 core-cluster { 183 polling-delay-passive = <1000>; 184 polling-delay = <5000>; 185 thermal-sensors = <&tmu 3>; 186 187 trips { 188 core_cluster_alert: core-cluster-alert { 189 temperature = <85000>; 190 hysteresis = <2000>; 191 type = "passive"; 192 }; 193 194 core_cluster_crit: core-cluster-crit { 195 temperature = <95000>; 196 hysteresis = <2000>; 197 type = "critical"; 198 }; 199 }; 200 201 cooling-maps { 202 map0 { 203 trip = <&core_cluster_alert>; 204 cooling-device = 205 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 206 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 207 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 208 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 209 }; 210 }; 211 }; 212 213 sec { 214 polling-delay-passive = <1000>; 215 polling-delay = <5000>; 216 thermal-sensors = <&tmu 4>; 217 218 trips { 219 sec-alert { 220 temperature = <85000>; 221 hysteresis = <2000>; 222 type = "passive"; 223 }; 224 225 sec-crit { 226 temperature = <95000>; 227 hysteresis = <2000>; 228 type = "critical"; 229 }; 230 }; 231 }; 232 }; 233 234 timer { 235 compatible = "arm,armv8-timer"; 236 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) | 237 IRQ_TYPE_LEVEL_LOW)>, 238 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) | 239 IRQ_TYPE_LEVEL_LOW)>, 240 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) | 241 IRQ_TYPE_LEVEL_LOW)>, 242 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) | 243 IRQ_TYPE_LEVEL_LOW)>; 244 }; 245 246 pmu { 247 compatible = "arm,cortex-a72-pmu"; 248 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 252 interrupt-affinity = <&cpu0>, 253 <&cpu1>, 254 <&cpu2>, 255 <&cpu3>; 256 }; 257 258 gic: interrupt-controller@1400000 { 259 compatible = "arm,gic-400"; 260 #interrupt-cells = <3>; 261 interrupt-controller; 262 reg = <0x0 0x1410000 0 0x10000>, /* GICD */ 263 <0x0 0x1420000 0 0x20000>, /* GICC */ 264 <0x0 0x1440000 0 0x20000>, /* GICH */ 265 <0x0 0x1460000 0 0x20000>; /* GICV */ 266 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 267 IRQ_TYPE_LEVEL_LOW)>; 268 }; 269 270 soc: soc { 271 compatible = "simple-bus"; 272 #address-cells = <2>; 273 #size-cells = <2>; 274 ranges; 275 276 ddr: memory-controller@1080000 { 277 compatible = "fsl,qoriq-memory-controller"; 278 reg = <0x0 0x1080000 0x0 0x1000>; 279 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 280 big-endian; 281 }; 282 283 ifc: memory-controller@1530000 { 284 compatible = "fsl,ifc"; 285 reg = <0x0 0x1530000 0x0 0x10000>; 286 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 287 status = "disabled"; 288 }; 289 290 qspi: spi@1550000 { 291 compatible = "fsl,ls1021a-qspi"; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 reg = <0x0 0x1550000 0x0 0x10000>, 295 <0x0 0x40000000 0x0 0x10000000>; 296 reg-names = "QuadSPI", "QuadSPI-memory"; 297 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 298 clock-names = "qspi_en", "qspi"; 299 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 300 QORIQ_CLK_PLL_DIV(2)>, 301 <&clockgen QORIQ_CLK_PLATFORM_PLL 302 QORIQ_CLK_PLL_DIV(2)>; 303 status = "disabled"; 304 }; 305 306 esdhc: esdhc@1560000 { 307 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; 308 reg = <0x0 0x1560000 0x0 0x10000>; 309 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 311 voltage-ranges = <1800 1800 3300 3300>; 312 sdhci,auto-cmd12; 313 big-endian; 314 bus-width = <4>; 315 }; 316 317 scfg: scfg@1570000 { 318 compatible = "fsl,ls1046a-scfg", "syscon"; 319 reg = <0x0 0x1570000 0x0 0x10000>; 320 big-endian; 321 #address-cells = <1>; 322 #size-cells = <1>; 323 ranges = <0x0 0x0 0x1570000 0x10000>; 324 325 extirq: interrupt-controller@1ac { 326 compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq"; 327 #interrupt-cells = <2>; 328 #address-cells = <0>; 329 interrupt-controller; 330 reg = <0x1ac 4>; 331 interrupt-map = 332 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 333 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 334 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 335 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 336 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 337 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 338 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 339 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 340 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 341 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 342 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 343 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 344 interrupt-map-mask = <0xf 0x0>; 345 }; 346 }; 347 348 crypto: crypto@1700000 { 349 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 350 "fsl,sec-v4.0"; 351 fsl,sec-era = <8>; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges = <0x0 0x00 0x1700000 0x100000>; 355 reg = <0x00 0x1700000 0x0 0x100000>; 356 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 357 dma-coherent; 358 359 sec_jr0: jr@10000 { 360 compatible = "fsl,sec-v5.4-job-ring", 361 "fsl,sec-v5.0-job-ring", 362 "fsl,sec-v4.0-job-ring"; 363 reg = <0x10000 0x10000>; 364 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 365 }; 366 367 sec_jr1: jr@20000 { 368 compatible = "fsl,sec-v5.4-job-ring", 369 "fsl,sec-v5.0-job-ring", 370 "fsl,sec-v4.0-job-ring"; 371 reg = <0x20000 0x10000>; 372 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 373 }; 374 375 sec_jr2: jr@30000 { 376 compatible = "fsl,sec-v5.4-job-ring", 377 "fsl,sec-v5.0-job-ring", 378 "fsl,sec-v4.0-job-ring"; 379 reg = <0x30000 0x10000>; 380 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 381 }; 382 383 sec_jr3: jr@40000 { 384 compatible = "fsl,sec-v5.4-job-ring", 385 "fsl,sec-v5.0-job-ring", 386 "fsl,sec-v4.0-job-ring"; 387 reg = <0x40000 0x10000>; 388 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 389 }; 390 }; 391 392 qman: qman@1880000 { 393 compatible = "fsl,qman"; 394 reg = <0x0 0x1880000 0x0 0x10000>; 395 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 396 memory-region = <&qman_fqd &qman_pfdr>; 397 398 }; 399 400 bman: bman@1890000 { 401 compatible = "fsl,bman"; 402 reg = <0x0 0x1890000 0x0 0x10000>; 403 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 404 memory-region = <&bman_fbpr>; 405 406 }; 407 408 qportals: qman-portals@500000000 { 409 ranges = <0x0 0x5 0x00000000 0x8000000>; 410 }; 411 412 bportals: bman-portals@508000000 { 413 ranges = <0x0 0x5 0x08000000 0x8000000>; 414 }; 415 416 sfp: efuse@1e80000 { 417 compatible = "fsl,ls1021a-sfp"; 418 reg = <0x0 0x1e80000 0x0 0x10000>; 419 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 420 QORIQ_CLK_PLL_DIV(4)>; 421 clock-names = "sfp"; 422 }; 423 424 dcfg: dcfg@1ee0000 { 425 compatible = "fsl,ls1046a-dcfg", "syscon"; 426 reg = <0x0 0x1ee0000 0x0 0x1000>; 427 big-endian; 428 }; 429 430 clockgen: clocking@1ee1000 { 431 compatible = "fsl,ls1046a-clockgen"; 432 reg = <0x0 0x1ee1000 0x0 0x1000>; 433 #clock-cells = <2>; 434 clocks = <&sysclk>; 435 }; 436 437 tmu: tmu@1f00000 { 438 compatible = "fsl,qoriq-tmu"; 439 reg = <0x0 0x1f00000 0x0 0x10000>; 440 interrupts = <0 33 0x4>; 441 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 442 fsl,tmu-calibration = 443 /* Calibration data group 1 */ 444 <0x00000000 0x00000023 445 0x00000001 0x00000029 446 0x00000002 0x0000002f 447 0x00000003 0x00000036 448 0x00000004 0x0000003c 449 0x00000005 0x00000042 450 0x00000006 0x00000049 451 0x00000007 0x0000004f 452 0x00000008 0x00000055 453 0x00000009 0x0000005c 454 0x0000000a 0x00000062 455 0x0000000b 0x00000068 456 /* Calibration data group 2 */ 457 0x00010000 0x00000022 458 0x00010001 0x0000002a 459 0x00010002 0x00000032 460 0x00010003 0x0000003a 461 0x00010004 0x00000042 462 0x00010005 0x0000004a 463 0x00010006 0x00000052 464 0x00010007 0x0000005a 465 0x00010008 0x00000062 466 0x00010009 0x0000006a 467 /* Calibration data group 3 */ 468 0x00020000 0x00000021 469 0x00020001 0x0000002b 470 0x00020002 0x00000035 471 0x00020003 0x0000003e 472 0x00020004 0x00000048 473 0x00020005 0x00000052 474 0x00020006 0x0000005c 475 /* Calibration data group 4 */ 476 0x00030000 0x00000011 477 0x00030001 0x0000001a 478 0x00030002 0x00000024 479 0x00030003 0x0000002e 480 0x00030004 0x00000038 481 0x00030005 0x00000042 482 0x00030006 0x0000004c 483 0x00030007 0x00000056>; 484 big-endian; 485 #thermal-sensor-cells = <1>; 486 }; 487 488 dspi: spi@2100000 { 489 compatible = "fsl,ls1021a-v1.0-dspi"; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 reg = <0x0 0x2100000 0x0 0x10000>; 493 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 494 clock-names = "dspi"; 495 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 496 QORIQ_CLK_PLL_DIV(2)>; 497 spi-num-chipselects = <5>; 498 big-endian; 499 status = "disabled"; 500 }; 501 502 i2c0: i2c@2180000 { 503 compatible = "fsl,vf610-i2c"; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 reg = <0x0 0x2180000 0x0 0x10000>; 507 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 509 QORIQ_CLK_PLL_DIV(2)>; 510 dmas = <&edma0 1 38>, 511 <&edma0 1 39>; 512 dma-names = "rx", "tx"; 513 status = "disabled"; 514 }; 515 516 i2c1: i2c@2190000 { 517 compatible = "fsl,vf610-i2c"; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 reg = <0x0 0x2190000 0x0 0x10000>; 521 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 523 QORIQ_CLK_PLL_DIV(2)>; 524 status = "disabled"; 525 }; 526 527 i2c2: i2c@21a0000 { 528 compatible = "fsl,vf610-i2c"; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 reg = <0x0 0x21a0000 0x0 0x10000>; 532 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 534 QORIQ_CLK_PLL_DIV(2)>; 535 status = "disabled"; 536 }; 537 538 i2c3: i2c@21b0000 { 539 compatible = "fsl,vf610-i2c"; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 reg = <0x0 0x21b0000 0x0 0x10000>; 543 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 545 QORIQ_CLK_PLL_DIV(2)>; 546 status = "disabled"; 547 }; 548 549 duart0: serial@21c0500 { 550 compatible = "fsl,ns16550", "ns16550a"; 551 reg = <0x00 0x21c0500 0x0 0x100>; 552 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 554 QORIQ_CLK_PLL_DIV(2)>; 555 status = "disabled"; 556 }; 557 558 duart1: serial@21c0600 { 559 compatible = "fsl,ns16550", "ns16550a"; 560 reg = <0x00 0x21c0600 0x0 0x100>; 561 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 563 QORIQ_CLK_PLL_DIV(2)>; 564 status = "disabled"; 565 }; 566 567 duart2: serial@21d0500 { 568 compatible = "fsl,ns16550", "ns16550a"; 569 reg = <0x0 0x21d0500 0x0 0x100>; 570 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 572 QORIQ_CLK_PLL_DIV(2)>; 573 status = "disabled"; 574 }; 575 576 duart3: serial@21d0600 { 577 compatible = "fsl,ns16550", "ns16550a"; 578 reg = <0x0 0x21d0600 0x0 0x100>; 579 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 581 QORIQ_CLK_PLL_DIV(2)>; 582 status = "disabled"; 583 }; 584 585 gpio0: gpio@2300000 { 586 compatible = "fsl,qoriq-gpio"; 587 reg = <0x0 0x2300000 0x0 0x10000>; 588 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 589 gpio-controller; 590 #gpio-cells = <2>; 591 interrupt-controller; 592 #interrupt-cells = <2>; 593 }; 594 595 gpio1: gpio@2310000 { 596 compatible = "fsl,qoriq-gpio"; 597 reg = <0x0 0x2310000 0x0 0x10000>; 598 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 599 gpio-controller; 600 #gpio-cells = <2>; 601 interrupt-controller; 602 #interrupt-cells = <2>; 603 }; 604 605 gpio2: gpio@2320000 { 606 compatible = "fsl,qoriq-gpio"; 607 reg = <0x0 0x2320000 0x0 0x10000>; 608 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 609 gpio-controller; 610 #gpio-cells = <2>; 611 interrupt-controller; 612 #interrupt-cells = <2>; 613 }; 614 615 gpio3: gpio@2330000 { 616 compatible = "fsl,qoriq-gpio"; 617 reg = <0x0 0x2330000 0x0 0x10000>; 618 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 619 gpio-controller; 620 #gpio-cells = <2>; 621 interrupt-controller; 622 #interrupt-cells = <2>; 623 }; 624 625 lpuart0: serial@2950000 { 626 compatible = "fsl,ls1021a-lpuart"; 627 reg = <0x0 0x2950000 0x0 0x1000>; 628 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 630 QORIQ_CLK_PLL_DIV(1)>; 631 clock-names = "ipg"; 632 status = "disabled"; 633 }; 634 635 lpuart1: serial@2960000 { 636 compatible = "fsl,ls1021a-lpuart"; 637 reg = <0x0 0x2960000 0x0 0x1000>; 638 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 640 QORIQ_CLK_PLL_DIV(2)>; 641 clock-names = "ipg"; 642 status = "disabled"; 643 }; 644 645 lpuart2: serial@2970000 { 646 compatible = "fsl,ls1021a-lpuart"; 647 reg = <0x0 0x2970000 0x0 0x1000>; 648 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 650 QORIQ_CLK_PLL_DIV(2)>; 651 clock-names = "ipg"; 652 status = "disabled"; 653 }; 654 655 lpuart3: serial@2980000 { 656 compatible = "fsl,ls1021a-lpuart"; 657 reg = <0x0 0x2980000 0x0 0x1000>; 658 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 660 QORIQ_CLK_PLL_DIV(2)>; 661 clock-names = "ipg"; 662 status = "disabled"; 663 }; 664 665 lpuart4: serial@2990000 { 666 compatible = "fsl,ls1021a-lpuart"; 667 reg = <0x0 0x2990000 0x0 0x1000>; 668 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 670 QORIQ_CLK_PLL_DIV(2)>; 671 clock-names = "ipg"; 672 status = "disabled"; 673 }; 674 675 lpuart5: serial@29a0000 { 676 compatible = "fsl,ls1021a-lpuart"; 677 reg = <0x0 0x29a0000 0x0 0x1000>; 678 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 680 QORIQ_CLK_PLL_DIV(2)>; 681 clock-names = "ipg"; 682 status = "disabled"; 683 }; 684 685 wdog0: watchdog@2ad0000 { 686 compatible = "fsl,imx21-wdt"; 687 reg = <0x0 0x2ad0000 0x0 0x10000>; 688 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 690 QORIQ_CLK_PLL_DIV(2)>; 691 big-endian; 692 }; 693 694 edma0: dma-controller@2c00000 { 695 #dma-cells = <2>; 696 compatible = "fsl,vf610-edma"; 697 reg = <0x0 0x2c00000 0x0 0x10000>, 698 <0x0 0x2c10000 0x0 0x10000>, 699 <0x0 0x2c20000 0x0 0x10000>; 700 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 702 interrupt-names = "edma-tx", "edma-err"; 703 dma-channels = <32>; 704 big-endian; 705 clock-names = "dmamux0", "dmamux1"; 706 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 707 QORIQ_CLK_PLL_DIV(2)>, 708 <&clockgen QORIQ_CLK_PLATFORM_PLL 709 QORIQ_CLK_PLL_DIV(2)>; 710 }; 711 712 usb0: usb@2f00000 { 713 compatible = "snps,dwc3"; 714 reg = <0x0 0x2f00000 0x0 0x10000>; 715 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 716 dr_mode = "host"; 717 snps,quirk-frame-length-adjustment = <0x20>; 718 snps,dis_rxdet_inp3_quirk; 719 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 720 }; 721 722 usb1: usb@3000000 { 723 compatible = "snps,dwc3"; 724 reg = <0x0 0x3000000 0x0 0x10000>; 725 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 726 dr_mode = "host"; 727 snps,quirk-frame-length-adjustment = <0x20>; 728 snps,dis_rxdet_inp3_quirk; 729 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 730 }; 731 732 usb2: usb@3100000 { 733 compatible = "snps,dwc3"; 734 reg = <0x0 0x3100000 0x0 0x10000>; 735 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 736 dr_mode = "host"; 737 snps,quirk-frame-length-adjustment = <0x20>; 738 snps,dis_rxdet_inp3_quirk; 739 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 740 }; 741 742 sata: sata@3200000 { 743 compatible = "fsl,ls1046a-ahci"; 744 reg = <0x0 0x3200000 0x0 0x10000>, 745 <0x0 0x20140520 0x0 0x4>; 746 reg-names = "ahci", "sata-ecc"; 747 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 749 QORIQ_CLK_PLL_DIV(2)>; 750 }; 751 752 msi1: msi-controller@1580000 { 753 compatible = "fsl,ls1046a-msi"; 754 msi-controller; 755 reg = <0x0 0x1580000 0x0 0x10000>; 756 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 760 }; 761 762 msi2: msi-controller@1590000 { 763 compatible = "fsl,ls1046a-msi"; 764 msi-controller; 765 reg = <0x0 0x1590000 0x0 0x10000>; 766 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 770 }; 771 772 msi3: msi-controller@15a0000 { 773 compatible = "fsl,ls1046a-msi"; 774 msi-controller; 775 reg = <0x0 0x15a0000 0x0 0x10000>; 776 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 780 }; 781 782 pcie1: pcie@3400000 { 783 compatible = "fsl,ls1046a-pcie"; 784 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 785 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 786 reg-names = "regs", "config"; 787 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 788 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 789 interrupt-names = "aer", "pme"; 790 #address-cells = <3>; 791 #size-cells = <2>; 792 device_type = "pci"; 793 dma-coherent; 794 num-viewport = <8>; 795 bus-range = <0x0 0xff>; 796 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 797 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 798 msi-parent = <&msi1>, <&msi2>, <&msi3>; 799 #interrupt-cells = <1>; 800 interrupt-map-mask = <0 0 0 7>; 801 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 802 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 803 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 804 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 805 status = "disabled"; 806 }; 807 808 pcie_ep1: pcie_ep@3400000 { 809 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 810 reg = <0x00 0x03400000 0x0 0x00100000>, 811 <0x40 0x00000000 0x8 0x00000000>; 812 reg-names = "regs", "addr_space"; 813 num-ib-windows = <6>; 814 num-ob-windows = <8>; 815 status = "disabled"; 816 }; 817 818 pcie2: pcie@3500000 { 819 compatible = "fsl,ls1046a-pcie"; 820 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 821 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 822 reg-names = "regs", "config"; 823 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 824 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 825 interrupt-names = "aer", "pme"; 826 #address-cells = <3>; 827 #size-cells = <2>; 828 device_type = "pci"; 829 dma-coherent; 830 num-viewport = <8>; 831 bus-range = <0x0 0xff>; 832 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 833 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 834 msi-parent = <&msi2>, <&msi3>, <&msi1>; 835 #interrupt-cells = <1>; 836 interrupt-map-mask = <0 0 0 7>; 837 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 838 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 839 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 840 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 841 status = "disabled"; 842 }; 843 844 pcie_ep2: pcie_ep@3500000 { 845 compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep"; 846 reg = <0x00 0x03500000 0x0 0x00100000>, 847 <0x48 0x00000000 0x8 0x00000000>; 848 reg-names = "regs", "addr_space"; 849 num-ib-windows = <6>; 850 num-ob-windows = <8>; 851 status = "disabled"; 852 }; 853 854 pcie3: pcie@3600000 { 855 compatible = "fsl,ls1046a-pcie"; 856 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 857 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 858 reg-names = "regs", "config"; 859 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 860 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 861 interrupt-names = "aer", "pme"; 862 #address-cells = <3>; 863 #size-cells = <2>; 864 device_type = "pci"; 865 dma-coherent; 866 num-viewport = <8>; 867 bus-range = <0x0 0xff>; 868 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 869 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 870 msi-parent = <&msi3>, <&msi1>, <&msi2>; 871 #interrupt-cells = <1>; 872 interrupt-map-mask = <0 0 0 7>; 873 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 874 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 875 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 876 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 877 status = "disabled"; 878 }; 879 880 pcie_ep3: pcie_ep@3600000 { 881 compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"; 882 reg = <0x00 0x03600000 0x0 0x00100000>, 883 <0x50 0x00000000 0x8 0x00000000>; 884 reg-names = "regs", "addr_space"; 885 num-ib-windows = <6>; 886 num-ob-windows = <8>; 887 status = "disabled"; 888 }; 889 890 qdma: dma-controller@8380000 { 891 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; 892 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 893 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 894 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 895 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 900 interrupt-names = "qdma-error", "qdma-queue0", 901 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 902 dma-channels = <8>; 903 block-number = <1>; 904 block-offset = <0x10000>; 905 fsl,dma-queues = <2>; 906 status-sizes = <64>; 907 queue-sizes = <64 64>; 908 big-endian; 909 }; 910 911 rcpm: power-controller@1ee2140 { 912 compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+"; 913 reg = <0x0 0x1ee2140 0x0 0x4>; 914 #fsl,rcpm-wakeup-cells = <1>; 915 }; 916 917 ftm_alarm0: timer@29d0000 { 918 compatible = "fsl,ls1046a-ftm-alarm"; 919 reg = <0x0 0x29d0000 0x0 0x10000>; 920 fsl,rcpm-wakeup = <&rcpm 0x20000>; 921 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 922 big-endian; 923 }; 924 }; 925 926 reserved-memory { 927 #address-cells = <2>; 928 #size-cells = <2>; 929 ranges; 930 931 bman_fbpr: bman-fbpr { 932 compatible = "shared-dma-pool"; 933 size = <0 0x1000000>; 934 alignment = <0 0x1000000>; 935 no-map; 936 }; 937 938 qman_fqd: qman-fqd { 939 compatible = "shared-dma-pool"; 940 size = <0 0x800000>; 941 alignment = <0 0x800000>; 942 no-map; 943 }; 944 945 qman_pfdr: qman-pfdr { 946 compatible = "shared-dma-pool"; 947 size = <0 0x2000000>; 948 alignment = <0 0x2000000>; 949 no-map; 950 }; 951 }; 952 953 firmware { 954 optee { 955 compatible = "linaro,optee-tz"; 956 method = "smc"; 957 }; 958 }; 959}; 960 961#include "qoriq-qman-portals.dtsi" 962#include "qoriq-bman-portals.dtsi" 963