1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Freescale Layerscape-1046A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2019-2020 NXP 7 * 8 * Mingkai Hu <mingkai.hu@nxp.com> 9 */ 10 11/dts-v1/; 12 13#include "fsl-ls1046a.dtsi" 14 15/ { 16 model = "LS1046A RDB Board"; 17 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; 18 19 aliases { 20 serial0 = &duart0; 21 serial1 = &duart1; 22 serial2 = &duart2; 23 serial3 = &duart3; 24 }; 25 26 chosen { 27 stdout-path = "serial0:115200n8"; 28 }; 29}; 30 31&duart0 { 32 status = "okay"; 33}; 34 35&duart1 { 36 status = "okay"; 37}; 38 39&esdhc { 40 mmc-hs200-1_8v; 41 sd-uhs-sdr104; 42 sd-uhs-sdr50; 43 sd-uhs-sdr25; 44 sd-uhs-sdr12; 45}; 46 47&i2c0 { 48 status = "okay"; 49 50 ina220@40 { 51 compatible = "ti,ina220"; 52 reg = <0x40>; 53 shunt-resistor = <1000>; 54 }; 55 56 temp-sensor@4c { 57 compatible = "adi,adt7461"; 58 reg = <0x4c>; 59 }; 60 61 eeprom@52 { 62 compatible = "onnn,cat24c05", "atmel,24c04"; 63 reg = <0x52>; 64 }; 65}; 66 67&i2c3 { 68 status = "okay"; 69 70 rtc@51 { 71 compatible = "nxp,pcf2129"; 72 reg = <0x51>; 73 /* IRQ_RTC_B -> IRQ05, active low */ 74 interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>; 75 }; 76}; 77 78&ifc { 79 #address-cells = <2>; 80 #size-cells = <1>; 81 /* NAND Flashe and CPLD on board */ 82 ranges = <0x0 0x0 0x0 0x7e800000 0x00010000 83 0x2 0x0 0x0 0x7fb00000 0x00000100>; 84 status = "okay"; 85 86 nand@0,0 { 87 compatible = "fsl,ifc-nand"; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 reg = <0x0 0x0 0x10000>; 91 }; 92 93 cpld: board-control@2,0 { 94 compatible = "fsl,ls1046ardb-cpld"; 95 reg = <0x2 0x0 0x0000100>; 96 }; 97}; 98 99&qspi { 100 status = "okay"; 101 102 s25fs512s0: flash@0 { 103 compatible = "jedec,spi-nor"; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 spi-max-frequency = <50000000>; 107 spi-rx-bus-width = <4>; 108 spi-tx-bus-width = <1>; 109 reg = <0>; 110 }; 111 112 s25fs512s1: flash@1 { 113 compatible = "jedec,spi-nor"; 114 #address-cells = <1>; 115 #size-cells = <1>; 116 spi-max-frequency = <50000000>; 117 spi-rx-bus-width = <4>; 118 spi-tx-bus-width = <1>; 119 reg = <1>; 120 }; 121}; 122 123&usb1 { 124 dr_mode = "otg"; 125}; 126 127#include "fsl-ls1046-post.dtsi" 128 129&fman0 { 130 ethernet@e4000 { 131 phy-handle = <&rgmii_phy1>; 132 phy-connection-type = "rgmii-id"; 133 }; 134 135 ethernet@e6000 { 136 phy-handle = <&rgmii_phy2>; 137 phy-connection-type = "rgmii-id"; 138 }; 139 140 ethernet@e8000 { 141 phy-handle = <&sgmii_phy1>; 142 phy-connection-type = "sgmii"; 143 }; 144 145 ethernet@ea000 { 146 phy-handle = <&sgmii_phy2>; 147 phy-connection-type = "sgmii"; 148 }; 149 150 ethernet@f0000 { /* 10GEC1 */ 151 phy-handle = <&aqr106_phy>; 152 phy-connection-type = "xgmii"; 153 }; 154 155 ethernet@f2000 { /* 10GEC2 */ 156 fixed-link = <0 1 1000 0 0>; 157 phy-connection-type = "xgmii"; 158 }; 159 160 mdio@fc000 { 161 rgmii_phy1: ethernet-phy@1 { 162 reg = <0x1>; 163 }; 164 165 rgmii_phy2: ethernet-phy@2 { 166 reg = <0x2>; 167 }; 168 169 sgmii_phy1: ethernet-phy@3 { 170 reg = <0x3>; 171 }; 172 173 sgmii_phy2: ethernet-phy@4 { 174 reg = <0x4>; 175 }; 176 }; 177 178 mdio@fd000 { 179 aqr106_phy: ethernet-phy@0 { 180 compatible = "ethernet-phy-ieee802.3-c45"; 181 interrupts = <0 131 4>; 182 reg = <0x0>; 183 }; 184 }; 185}; 186