xref: /freebsd/sys/contrib/device-tree/src/arm64/freescale/fsl-ls1046a-qds.dts (revision 0fca6ea1d4eea4c934cfff25ac9ee8ad6fe95583) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4 *
5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2018-2019 NXP
7 *
8 * Shaohui Xie <Shaohui.Xie@nxp.com>
9 */
10
11/dts-v1/;
12
13#include "fsl-ls1046a.dtsi"
14
15/ {
16	model = "LS1046A QDS Board";
17	compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
18
19	aliases {
20		emi1-slot1 = &ls1046mdio_s1;
21		emi1-slot2 = &ls1046mdio_s2;
22		emi1-slot4 = &ls1046mdio_s4;
23		gpio0 = &gpio0;
24		gpio1 = &gpio1;
25		gpio2 = &gpio2;
26		gpio3 = &gpio3;
27		qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
28		qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
29		qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
30		qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
31		serial0 = &duart0;
32		serial1 = &duart1;
33		serial2 = &duart2;
34		serial3 = &duart3;
35		sgmii-s1-p1 = &sgmii_phy_s1_p1;
36		sgmii-s1-p2 = &sgmii_phy_s1_p2;
37		sgmii-s1-p3 = &sgmii_phy_s1_p3;
38		sgmii-s1-p4 = &sgmii_phy_s1_p4;
39		sgmii-s4-p1 = &sgmii_phy_s4_p1;
40	};
41
42	chosen {
43		stdout-path = "serial0:115200n8";
44	};
45};
46
47&dspi {
48	bus-num = <0>;
49	status = "okay";
50
51	flash@0 {
52		#address-cells = <1>;
53		#size-cells = <1>;
54		compatible = "n25q128a11", "jedec,spi-nor";
55		reg = <0>;
56		spi-max-frequency = <10000000>;
57	};
58
59	flash@1 {
60		#address-cells = <1>;
61		#size-cells = <1>;
62		compatible = "sst25wf040b", "jedec,spi-nor";
63		spi-cpol;
64		spi-cpha;
65		reg = <1>;
66		spi-max-frequency = <10000000>;
67	};
68
69	flash@2 {
70		#address-cells = <1>;
71		#size-cells = <1>;
72		compatible = "en25s64", "jedec,spi-nor";
73		spi-cpol;
74		spi-cpha;
75		reg = <2>;
76		spi-max-frequency = <10000000>;
77	};
78};
79
80&duart0 {
81	status = "okay";
82};
83
84&duart1 {
85	status = "okay";
86};
87
88&i2c0 {
89	status = "okay";
90
91	i2c-mux@77 {
92		compatible = "nxp,pca9547";
93		reg = <0x77>;
94		#address-cells = <1>;
95		#size-cells = <0>;
96
97		i2c@2 {
98			#address-cells = <1>;
99			#size-cells = <0>;
100			reg = <0x2>;
101
102			ina220@40 {
103				compatible = "ti,ina220";
104				reg = <0x40>;
105				shunt-resistor = <1000>;
106			};
107
108			ina220@41 {
109				compatible = "ti,ina220";
110				reg = <0x41>;
111				shunt-resistor = <1000>;
112			};
113		};
114
115		i2c@3 {
116			#address-cells = <1>;
117			#size-cells = <0>;
118			reg = <0x3>;
119
120			rtc@51 {
121				compatible = "nxp,pcf2129";
122				reg = <0x51>;
123				/* IRQ10_B */
124				interrupts = <0 150 0x4>;
125			};
126
127			eeprom@56 {
128				compatible = "atmel,24c512";
129				reg = <0x56>;
130			};
131
132			eeprom@57 {
133				compatible = "atmel,24c512";
134				reg = <0x57>;
135			};
136
137			temp-sensor@4c {
138				compatible = "adi,adt7461a";
139				reg = <0x4c>;
140			};
141		};
142	};
143};
144
145&ifc {
146	#address-cells = <2>;
147	#size-cells = <1>;
148	/* NOR, NAND Flashes and FPGA on board */
149	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
150		  0x1 0x0 0x0 0x7e800000 0x00010000
151		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
152	status = "okay";
153
154	nor@0,0 {
155		compatible = "cfi-flash";
156		reg = <0x0 0x0 0x8000000>;
157		big-endian;
158		bank-width = <2>;
159		device-width = <1>;
160	};
161
162	nand@1,0 {
163		compatible = "fsl,ifc-nand";
164		reg = <0x1 0x0 0x10000>;
165	};
166
167	fpga: board-control@2,0 {
168		compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
169		reg = <0x2 0x0 0x0000100>;
170		ranges = <0 2 0 0x100>;
171	};
172};
173
174&lpuart0 {
175	status = "okay";
176};
177
178&qspi {
179	status = "okay";
180
181	qflash0: flash@0 {
182		compatible = "spansion,m25p80";
183		#address-cells = <1>;
184		#size-cells = <1>;
185		spi-max-frequency = <50000000>;
186		spi-rx-bus-width = <4>;
187		spi-tx-bus-width = <4>;
188		reg = <0>;
189	};
190};
191
192#include "fsl-ls1046-post.dtsi"
193
194&fman0 {
195	ethernet@e0000 {
196		phy-handle = <&qsgmii_phy_s2_p1>;
197		phy-connection-type = "sgmii";
198	};
199
200	ethernet@e2000 {
201		phy-handle = <&sgmii_phy_s4_p1>;
202		phy-connection-type = "sgmii";
203	};
204
205	ethernet@e4000 {
206		phy-handle = <&rgmii_phy1>;
207		phy-connection-type = "rgmii";
208	};
209
210	ethernet@e6000 {
211		phy-handle = <&rgmii_phy2>;
212		phy-connection-type = "rgmii";
213	};
214
215	ethernet@e8000 {
216		phy-handle = <&sgmii_phy_s1_p3>;
217		phy-connection-type = "sgmii";
218	};
219
220	ethernet@ea000 {
221		phy-handle = <&sgmii_phy_s1_p4>;
222		phy-connection-type = "sgmii";
223	};
224
225	ethernet@f0000 { /* DTSEC9/10GEC1 */
226		phy-handle = <&sgmii_phy_s1_p1>;
227		phy-connection-type = "xgmii";
228	};
229
230	ethernet@f2000 { /* DTSEC10/10GEC2 */
231		phy-handle = <&sgmii_phy_s1_p2>;
232		phy-connection-type = "xgmii";
233	};
234};
235
236&fpga {
237	#address-cells = <1>;
238	#size-cells = <1>;
239
240	mdio-mux-emi1 {
241		compatible = "mdio-mux-mmioreg", "mdio-mux";
242		mdio-parent-bus = <&mdio0>;
243		#address-cells = <1>;
244		#size-cells = <0>;
245		reg = <0x54 1>;    /* BRDCFG4 */
246		mux-mask = <0xe0>; /* EMI1 */
247
248		/* On-board RGMII1 PHY */
249		ls1046mdio0: mdio@0 {
250			reg = <0>;
251			#address-cells = <1>;
252			#size-cells = <0>;
253
254			rgmii_phy1: ethernet-phy@1 { /* MAC3 */
255				reg = <0x1>;
256			};
257		};
258
259		/* On-board RGMII2 PHY */
260		ls1046mdio1: mdio@1 {
261			reg = <0x20>;
262			#address-cells = <1>;
263			#size-cells = <0>;
264
265			rgmii_phy2: ethernet-phy@2 { /* MAC4 */
266				reg = <0x2>;
267			};
268		};
269
270		/* Slot 1 */
271		ls1046mdio_s1: mdio@2 {
272			reg = <0x40>;
273			#address-cells = <1>;
274			#size-cells = <0>;
275			status = "disabled";
276
277			sgmii_phy_s1_p1: ethernet-phy@1c {
278				reg = <0x1c>;
279			};
280
281			sgmii_phy_s1_p2: ethernet-phy@1d {
282				reg = <0x1d>;
283			};
284
285			sgmii_phy_s1_p3: ethernet-phy@1e {
286				reg = <0x1e>;
287			};
288
289			sgmii_phy_s1_p4: ethernet-phy@1f {
290				reg = <0x1f>;
291			};
292		};
293
294		/* Slot 2 */
295		ls1046mdio_s2: mdio@3 {
296			reg = <0x60>;
297			#address-cells = <1>;
298			#size-cells = <0>;
299			status = "disabled";
300
301			qsgmii_phy_s2_p1: ethernet-phy@8 {
302				reg = <0x8>;
303			};
304
305			qsgmii_phy_s2_p2: ethernet-phy@9 {
306				reg = <0x9>;
307			};
308
309			qsgmii_phy_s2_p3: ethernet-phy@a {
310				reg = <0xa>;
311			};
312
313			qsgmii_phy_s2_p4: ethernet-phy@b {
314				reg = <0xb>;
315			};
316		};
317
318		/* Slot 4 */
319		ls1046mdio_s4: mdio@5 {
320			reg = <0x80>;
321			#address-cells = <1>;
322			#size-cells = <0>;
323			status = "disabled";
324
325			sgmii_phy_s4_p1: ethernet-phy@1c {
326				reg = <0x1c>;
327			};
328		};
329	};
330};
331