1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Freescale Layerscape-1046A family SoC. 4 * 5 * Copyright 2019 NXP. 6 * 7 */ 8 9/dts-v1/; 10 11#include "fsl-ls1046a.dtsi" 12 13/ { 14 model = "LS1046A FRWY Board"; 15 compatible = "fsl,ls1046a-frwy", "fsl,ls1046a"; 16 17 aliases { 18 serial0 = &duart0; 19 serial1 = &duart1; 20 serial2 = &duart2; 21 serial3 = &duart3; 22 }; 23 24 chosen { 25 stdout-path = "serial0:115200n8"; 26 }; 27 28 sb_3v3: regulator-sb3v3 { 29 compatible = "regulator-fixed"; 30 regulator-name = "LT8642SEV-3.3V"; 31 regulator-min-microvolt = <3300000>; 32 regulator-max-microvolt = <3300000>; 33 regulator-boot-on; 34 regulator-always-on; 35 }; 36}; 37 38&duart0 { 39 status = "okay"; 40}; 41 42&duart1 { 43 status = "okay"; 44}; 45 46&duart2 { 47 status = "okay"; 48}; 49 50&duart3 { 51 status = "okay"; 52}; 53 54&i2c0 { 55 status = "okay"; 56 57 i2c-mux@77 { 58 compatible = "nxp,pca9546"; 59 reg = <0x77>; 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 i2c@0 { 64 #address-cells = <1>; 65 #size-cells = <0>; 66 reg = <0>; 67 68 power-monitor@40 { 69 compatible = "ti,ina220"; 70 reg = <0x40>; 71 shunt-resistor = <1000>; 72 }; 73 74 temperature-sensor@4c { 75 compatible = "nxp,sa56004"; 76 reg = <0x4c>; 77 vcc-supply = <&sb_3v3>; 78 }; 79 80 rtc@51 { 81 compatible = "nxp,pcf2129"; 82 reg = <0x51>; 83 }; 84 85 eeprom@52 { 86 compatible = "atmel,24c512"; 87 reg = <0x52>; 88 }; 89 90 eeprom@53 { 91 compatible = "atmel,24c512"; 92 reg = <0x53>; 93 }; 94 95 }; 96 }; 97}; 98 99&ifc { 100 #address-cells = <2>; 101 #size-cells = <1>; 102 /* NAND Flash */ 103 ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>; 104 status = "okay"; 105 106 nand@0,0 { 107 compatible = "fsl,ifc-nand"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 reg = <0x0 0x0 0x10000>; 111 }; 112 113}; 114 115&qspi { 116 status = "okay"; 117 118 mt25qu512a0: flash@0 { 119 compatible = "jedec,spi-nor"; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 spi-max-frequency = <50000000>; 123 spi-rx-bus-width = <4>; 124 spi-tx-bus-width = <1>; 125 reg = <0>; 126 }; 127}; 128 129#include "fsl-ls1046-post.dtsi" 130 131&fman0 { 132 ethernet@e0000 { 133 phy-handle = <&qsgmii_phy4>; 134 phy-connection-type = "qsgmii"; 135 }; 136 137 ethernet@e8000 { 138 phy-handle = <&qsgmii_phy2>; 139 phy-connection-type = "qsgmii"; 140 }; 141 142 ethernet@ea000 { 143 phy-handle = <&qsgmii_phy1>; 144 phy-connection-type = "qsgmii"; 145 }; 146 147 ethernet@f2000 { 148 phy-handle = <&qsgmii_phy3>; 149 phy-connection-type = "qsgmii"; 150 }; 151 152 mdio@fd000 { 153 qsgmii_phy1: ethernet-phy@1c { 154 reg = <0x1c>; 155 }; 156 157 qsgmii_phy2: ethernet-phy@1d { 158 reg = <0x1d>; 159 }; 160 161 qsgmii_phy3: ethernet-phy@1e { 162 reg = <0x1e>; 163 }; 164 165 qsgmii_phy4: ethernet-phy@1f { 166 reg = <0x1f>; 167 }; 168 }; 169}; 170