1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1043A family SoC. 4 * 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2020 NXP 7 * 8 * Mingkai Hu <Mingkai.hu@freescale.com> 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/thermal/thermal.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14 15/ { 16 compatible = "fsl,ls1043a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 crypto = &crypto; 23 fman0 = &fman0; 24 ethernet0 = &enet0; 25 ethernet1 = &enet1; 26 ethernet2 = &enet2; 27 ethernet3 = &enet3; 28 ethernet4 = &enet4; 29 ethernet5 = &enet5; 30 ethernet6 = &enet6; 31 rtc1 = &ftm_alarm0; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 /* 39 * We expect the enable-method for cpu's to be "psci", but this 40 * is dependent on the SoC FW, which will fill this in. 41 * 42 * Currently supported enable-method is psci v0.2 43 */ 44 cpu0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x0>; 48 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 49 next-level-cache = <&l2>; 50 cpu-idle-states = <&CPU_PH20>; 51 #cooling-cells = <2>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a53"; 57 reg = <0x1>; 58 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 59 next-level-cache = <&l2>; 60 cpu-idle-states = <&CPU_PH20>; 61 #cooling-cells = <2>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x2>; 68 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 69 next-level-cache = <&l2>; 70 cpu-idle-states = <&CPU_PH20>; 71 #cooling-cells = <2>; 72 }; 73 74 cpu3: cpu@3 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x3>; 78 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 79 next-level-cache = <&l2>; 80 cpu-idle-states = <&CPU_PH20>; 81 #cooling-cells = <2>; 82 }; 83 84 l2: l2-cache { 85 compatible = "cache"; 86 }; 87 }; 88 89 idle-states { 90 /* 91 * PSCI node is not added default, U-boot will add missing 92 * parts if it determines to use PSCI. 93 */ 94 entry-method = "psci"; 95 96 CPU_PH20: cpu-ph20 { 97 compatible = "arm,idle-state"; 98 idle-state-name = "PH20"; 99 arm,psci-suspend-param = <0x0>; 100 entry-latency-us = <1000>; 101 exit-latency-us = <1000>; 102 min-residency-us = <3000>; 103 }; 104 }; 105 106 memory@80000000 { 107 device_type = "memory"; 108 reg = <0x0 0x80000000 0 0x80000000>; 109 /* DRAM space 1, size: 2GiB DRAM */ 110 }; 111 112 reserved-memory { 113 #address-cells = <2>; 114 #size-cells = <2>; 115 ranges; 116 117 bman_fbpr: bman-fbpr { 118 compatible = "shared-dma-pool"; 119 size = <0 0x1000000>; 120 alignment = <0 0x1000000>; 121 no-map; 122 }; 123 124 qman_fqd: qman-fqd { 125 compatible = "shared-dma-pool"; 126 size = <0 0x400000>; 127 alignment = <0 0x400000>; 128 no-map; 129 }; 130 131 qman_pfdr: qman-pfdr { 132 compatible = "shared-dma-pool"; 133 size = <0 0x2000000>; 134 alignment = <0 0x2000000>; 135 no-map; 136 }; 137 }; 138 139 sysclk: sysclk { 140 compatible = "fixed-clock"; 141 #clock-cells = <0>; 142 clock-frequency = <100000000>; 143 clock-output-names = "sysclk"; 144 }; 145 146 reboot { 147 compatible ="syscon-reboot"; 148 regmap = <&dcfg>; 149 offset = <0xb0>; 150 mask = <0x02>; 151 }; 152 153 thermal-zones { 154 ddr-controller { 155 polling-delay-passive = <1000>; 156 polling-delay = <5000>; 157 thermal-sensors = <&tmu 0>; 158 159 trips { 160 ddr-ctrler-alert { 161 temperature = <85000>; 162 hysteresis = <2000>; 163 type = "passive"; 164 }; 165 166 ddr-ctrler-crit { 167 temperature = <95000>; 168 hysteresis = <2000>; 169 type = "critical"; 170 }; 171 }; 172 }; 173 174 serdes { 175 polling-delay-passive = <1000>; 176 polling-delay = <5000>; 177 thermal-sensors = <&tmu 1>; 178 179 trips { 180 serdes-alert { 181 temperature = <85000>; 182 hysteresis = <2000>; 183 type = "passive"; 184 }; 185 186 serdes-crit { 187 temperature = <95000>; 188 hysteresis = <2000>; 189 type = "critical"; 190 }; 191 }; 192 }; 193 194 fman { 195 polling-delay-passive = <1000>; 196 polling-delay = <5000>; 197 thermal-sensors = <&tmu 2>; 198 199 trips { 200 fman-alert { 201 temperature = <85000>; 202 hysteresis = <2000>; 203 type = "passive"; 204 }; 205 206 fman-crit { 207 temperature = <95000>; 208 hysteresis = <2000>; 209 type = "critical"; 210 }; 211 }; 212 }; 213 214 core-cluster { 215 polling-delay-passive = <1000>; 216 polling-delay = <5000>; 217 thermal-sensors = <&tmu 3>; 218 219 trips { 220 core_cluster_alert: core-cluster-alert { 221 temperature = <85000>; 222 hysteresis = <2000>; 223 type = "passive"; 224 }; 225 226 core_cluster_crit: core-cluster-crit { 227 temperature = <95000>; 228 hysteresis = <2000>; 229 type = "critical"; 230 }; 231 }; 232 233 cooling-maps { 234 map0 { 235 trip = <&core_cluster_alert>; 236 cooling-device = 237 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 238 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 239 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 240 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 241 }; 242 }; 243 }; 244 245 sec { 246 polling-delay-passive = <1000>; 247 polling-delay = <5000>; 248 thermal-sensors = <&tmu 4>; 249 250 trips { 251 sec-alert { 252 temperature = <85000>; 253 hysteresis = <2000>; 254 type = "passive"; 255 }; 256 257 sec-crit { 258 temperature = <95000>; 259 hysteresis = <2000>; 260 type = "critical"; 261 }; 262 }; 263 }; 264 }; 265 266 timer { 267 compatible = "arm,armv8-timer"; 268 interrupts = <1 13 0xf08>, /* Physical Secure PPI */ 269 <1 14 0xf08>, /* Physical Non-Secure PPI */ 270 <1 11 0xf08>, /* Virtual PPI */ 271 <1 10 0xf08>; /* Hypervisor PPI */ 272 fsl,erratum-a008585; 273 }; 274 275 pmu { 276 compatible = "arm,armv8-pmuv3"; 277 interrupts = <0 106 0x4>, 278 <0 107 0x4>, 279 <0 95 0x4>, 280 <0 97 0x4>; 281 interrupt-affinity = <&cpu0>, 282 <&cpu1>, 283 <&cpu2>, 284 <&cpu3>; 285 }; 286 287 gic: interrupt-controller@1400000 { 288 compatible = "arm,gic-400"; 289 #interrupt-cells = <3>; 290 interrupt-controller; 291 reg = <0x0 0x1401000 0 0x1000>, /* GICD */ 292 <0x0 0x1402000 0 0x2000>, /* GICC */ 293 <0x0 0x1404000 0 0x2000>, /* GICH */ 294 <0x0 0x1406000 0 0x2000>; /* GICV */ 295 interrupts = <1 9 0xf08>; 296 }; 297 298 soc: soc { 299 compatible = "simple-bus"; 300 #address-cells = <2>; 301 #size-cells = <2>; 302 ranges; 303 304 clockgen: clocking@1ee1000 { 305 compatible = "fsl,ls1043a-clockgen"; 306 reg = <0x0 0x1ee1000 0x0 0x1000>; 307 #clock-cells = <2>; 308 clocks = <&sysclk>; 309 }; 310 311 scfg: scfg@1570000 { 312 compatible = "fsl,ls1043a-scfg", "syscon"; 313 reg = <0x0 0x1570000 0x0 0x10000>; 314 big-endian; 315 #address-cells = <1>; 316 #size-cells = <1>; 317 ranges = <0x0 0x0 0x1570000 0x10000>; 318 319 extirq: interrupt-controller@1ac { 320 compatible = "fsl,ls1043a-extirq"; 321 #interrupt-cells = <2>; 322 #address-cells = <0>; 323 interrupt-controller; 324 reg = <0x1ac 4>; 325 interrupt-map = 326 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 327 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 328 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 329 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 330 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 331 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 332 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 333 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 334 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 335 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 336 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 337 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 338 interrupt-map-mask = <0xffffffff 0x0>; 339 }; 340 }; 341 342 crypto: crypto@1700000 { 343 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 344 "fsl,sec-v4.0"; 345 fsl,sec-era = <3>; 346 #address-cells = <1>; 347 #size-cells = <1>; 348 ranges = <0x0 0x00 0x1700000 0x100000>; 349 reg = <0x00 0x1700000 0x0 0x100000>; 350 interrupts = <0 75 0x4>; 351 dma-coherent; 352 353 sec_jr0: jr@10000 { 354 compatible = "fsl,sec-v5.4-job-ring", 355 "fsl,sec-v5.0-job-ring", 356 "fsl,sec-v4.0-job-ring"; 357 reg = <0x10000 0x10000>; 358 interrupts = <0 71 0x4>; 359 }; 360 361 sec_jr1: jr@20000 { 362 compatible = "fsl,sec-v5.4-job-ring", 363 "fsl,sec-v5.0-job-ring", 364 "fsl,sec-v4.0-job-ring"; 365 reg = <0x20000 0x10000>; 366 interrupts = <0 72 0x4>; 367 }; 368 369 sec_jr2: jr@30000 { 370 compatible = "fsl,sec-v5.4-job-ring", 371 "fsl,sec-v5.0-job-ring", 372 "fsl,sec-v4.0-job-ring"; 373 reg = <0x30000 0x10000>; 374 interrupts = <0 73 0x4>; 375 }; 376 377 sec_jr3: jr@40000 { 378 compatible = "fsl,sec-v5.4-job-ring", 379 "fsl,sec-v5.0-job-ring", 380 "fsl,sec-v4.0-job-ring"; 381 reg = <0x40000 0x10000>; 382 interrupts = <0 74 0x4>; 383 }; 384 }; 385 386 dcfg: dcfg@1ee0000 { 387 compatible = "fsl,ls1043a-dcfg", "syscon"; 388 reg = <0x0 0x1ee0000 0x0 0x10000>; 389 big-endian; 390 }; 391 392 ifc: ifc@1530000 { 393 compatible = "fsl,ifc", "simple-bus"; 394 reg = <0x0 0x1530000 0x0 0x10000>; 395 interrupts = <0 43 0x4>; 396 }; 397 398 qspi: spi@1550000 { 399 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi"; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 reg = <0x0 0x1550000 0x0 0x10000>, 403 <0x0 0x40000000 0x0 0x4000000>; 404 reg-names = "QuadSPI", "QuadSPI-memory"; 405 interrupts = <0 99 0x4>; 406 clock-names = "qspi_en", "qspi"; 407 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 408 QORIQ_CLK_PLL_DIV(1)>, 409 <&clockgen QORIQ_CLK_PLATFORM_PLL 410 QORIQ_CLK_PLL_DIV(1)>; 411 status = "disabled"; 412 }; 413 414 esdhc: esdhc@1560000 { 415 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; 416 reg = <0x0 0x1560000 0x0 0x10000>; 417 interrupts = <0 62 0x4>; 418 clock-frequency = <0>; 419 voltage-ranges = <1800 1800 3300 3300>; 420 sdhci,auto-cmd12; 421 big-endian; 422 bus-width = <4>; 423 }; 424 425 ddr: memory-controller@1080000 { 426 compatible = "fsl,qoriq-memory-controller"; 427 reg = <0x0 0x1080000 0x0 0x1000>; 428 interrupts = <0 144 0x4>; 429 big-endian; 430 }; 431 432 tmu: tmu@1f00000 { 433 compatible = "fsl,qoriq-tmu"; 434 reg = <0x0 0x1f00000 0x0 0x10000>; 435 interrupts = <0 33 0x4>; 436 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 437 fsl,tmu-calibration = <0x00000000 0x00000023 438 0x00000001 0x0000002a 439 0x00000002 0x00000031 440 0x00000003 0x00000037 441 0x00000004 0x0000003e 442 0x00000005 0x00000044 443 0x00000006 0x0000004b 444 0x00000007 0x00000051 445 0x00000008 0x00000058 446 0x00000009 0x0000005e 447 0x0000000a 0x00000065 448 0x0000000b 0x0000006b 449 450 0x00010000 0x00000023 451 0x00010001 0x0000002b 452 0x00010002 0x00000033 453 0x00010003 0x0000003b 454 0x00010004 0x00000043 455 0x00010005 0x0000004b 456 0x00010006 0x00000054 457 0x00010007 0x0000005c 458 0x00010008 0x00000064 459 0x00010009 0x0000006c 460 461 0x00020000 0x00000021 462 0x00020001 0x0000002c 463 0x00020002 0x00000036 464 0x00020003 0x00000040 465 0x00020004 0x0000004b 466 0x00020005 0x00000055 467 0x00020006 0x0000005f 468 469 0x00030000 0x00000013 470 0x00030001 0x0000001d 471 0x00030002 0x00000028 472 0x00030003 0x00000032 473 0x00030004 0x0000003d 474 0x00030005 0x00000047 475 0x00030006 0x00000052 476 0x00030007 0x0000005c>; 477 #thermal-sensor-cells = <1>; 478 }; 479 480 qman: qman@1880000 { 481 compatible = "fsl,qman"; 482 reg = <0x0 0x1880000 0x0 0x10000>; 483 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 484 memory-region = <&qman_fqd &qman_pfdr>; 485 }; 486 487 bman: bman@1890000 { 488 compatible = "fsl,bman"; 489 reg = <0x0 0x1890000 0x0 0x10000>; 490 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 491 memory-region = <&bman_fbpr>; 492 }; 493 494 bportals: bman-portals@508000000 { 495 ranges = <0x0 0x5 0x08000000 0x8000000>; 496 }; 497 498 qportals: qman-portals@500000000 { 499 ranges = <0x0 0x5 0x00000000 0x8000000>; 500 }; 501 502 dspi0: spi@2100000 { 503 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 reg = <0x0 0x2100000 0x0 0x10000>; 507 interrupts = <0 64 0x4>; 508 clock-names = "dspi"; 509 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 510 QORIQ_CLK_PLL_DIV(1)>; 511 spi-num-chipselects = <5>; 512 big-endian; 513 status = "disabled"; 514 }; 515 516 dspi1: spi@2110000 { 517 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 reg = <0x0 0x2110000 0x0 0x10000>; 521 interrupts = <0 65 0x4>; 522 clock-names = "dspi"; 523 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 524 QORIQ_CLK_PLL_DIV(1)>; 525 spi-num-chipselects = <5>; 526 big-endian; 527 status = "disabled"; 528 }; 529 530 i2c0: i2c@2180000 { 531 compatible = "fsl,vf610-i2c"; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 reg = <0x0 0x2180000 0x0 0x10000>; 535 interrupts = <0 56 0x4>; 536 clock-names = "i2c"; 537 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 538 QORIQ_CLK_PLL_DIV(1)>; 539 dmas = <&edma0 1 38>, 540 <&edma0 1 39>; 541 dma-names = "rx", "tx"; 542 status = "disabled"; 543 }; 544 545 i2c1: i2c@2190000 { 546 compatible = "fsl,vf610-i2c"; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 reg = <0x0 0x2190000 0x0 0x10000>; 550 interrupts = <0 57 0x4>; 551 clock-names = "i2c"; 552 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 553 QORIQ_CLK_PLL_DIV(1)>; 554 status = "disabled"; 555 }; 556 557 i2c2: i2c@21a0000 { 558 compatible = "fsl,vf610-i2c"; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 reg = <0x0 0x21a0000 0x0 0x10000>; 562 interrupts = <0 58 0x4>; 563 clock-names = "i2c"; 564 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 565 QORIQ_CLK_PLL_DIV(1)>; 566 status = "disabled"; 567 }; 568 569 i2c3: i2c@21b0000 { 570 compatible = "fsl,vf610-i2c"; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 reg = <0x0 0x21b0000 0x0 0x10000>; 574 interrupts = <0 59 0x4>; 575 clock-names = "i2c"; 576 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 577 QORIQ_CLK_PLL_DIV(1)>; 578 status = "disabled"; 579 }; 580 581 duart0: serial@21c0500 { 582 compatible = "fsl,ns16550", "ns16550a"; 583 reg = <0x00 0x21c0500 0x0 0x100>; 584 interrupts = <0 54 0x4>; 585 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 586 QORIQ_CLK_PLL_DIV(1)>; 587 }; 588 589 duart1: serial@21c0600 { 590 compatible = "fsl,ns16550", "ns16550a"; 591 reg = <0x00 0x21c0600 0x0 0x100>; 592 interrupts = <0 54 0x4>; 593 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 594 QORIQ_CLK_PLL_DIV(1)>; 595 }; 596 597 duart2: serial@21d0500 { 598 compatible = "fsl,ns16550", "ns16550a"; 599 reg = <0x0 0x21d0500 0x0 0x100>; 600 interrupts = <0 55 0x4>; 601 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 602 QORIQ_CLK_PLL_DIV(1)>; 603 }; 604 605 duart3: serial@21d0600 { 606 compatible = "fsl,ns16550", "ns16550a"; 607 reg = <0x0 0x21d0600 0x0 0x100>; 608 interrupts = <0 55 0x4>; 609 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 610 QORIQ_CLK_PLL_DIV(1)>; 611 }; 612 613 gpio1: gpio@2300000 { 614 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 615 reg = <0x0 0x2300000 0x0 0x10000>; 616 interrupts = <0 66 0x4>; 617 gpio-controller; 618 #gpio-cells = <2>; 619 interrupt-controller; 620 #interrupt-cells = <2>; 621 }; 622 623 gpio2: gpio@2310000 { 624 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 625 reg = <0x0 0x2310000 0x0 0x10000>; 626 interrupts = <0 67 0x4>; 627 gpio-controller; 628 #gpio-cells = <2>; 629 interrupt-controller; 630 #interrupt-cells = <2>; 631 }; 632 633 gpio3: gpio@2320000 { 634 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 635 reg = <0x0 0x2320000 0x0 0x10000>; 636 interrupts = <0 68 0x4>; 637 gpio-controller; 638 #gpio-cells = <2>; 639 interrupt-controller; 640 #interrupt-cells = <2>; 641 }; 642 643 gpio4: gpio@2330000 { 644 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 645 reg = <0x0 0x2330000 0x0 0x10000>; 646 interrupts = <0 134 0x4>; 647 gpio-controller; 648 #gpio-cells = <2>; 649 interrupt-controller; 650 #interrupt-cells = <2>; 651 }; 652 653 uqe: uqe@2400000 { 654 #address-cells = <1>; 655 #size-cells = <1>; 656 compatible = "fsl,qe", "simple-bus"; 657 ranges = <0x0 0x0 0x2400000 0x40000>; 658 reg = <0x0 0x2400000 0x0 0x480>; 659 brg-frequency = <100000000>; 660 bus-frequency = <200000000>; 661 fsl,qe-num-riscs = <1>; 662 fsl,qe-num-snums = <28>; 663 664 qeic: qeic@80 { 665 compatible = "fsl,qe-ic"; 666 reg = <0x80 0x80>; 667 #address-cells = <0>; 668 interrupt-controller; 669 #interrupt-cells = <1>; 670 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 672 }; 673 674 si1: si@700 { 675 #address-cells = <1>; 676 #size-cells = <0>; 677 compatible = "fsl,ls1043-qe-si", 678 "fsl,t1040-qe-si"; 679 reg = <0x700 0x80>; 680 }; 681 682 siram1: siram@1000 { 683 #address-cells = <1>; 684 #size-cells = <1>; 685 compatible = "fsl,ls1043-qe-siram", 686 "fsl,t1040-qe-siram"; 687 reg = <0x1000 0x800>; 688 }; 689 690 ucc@2000 { 691 cell-index = <1>; 692 reg = <0x2000 0x200>; 693 interrupts = <32>; 694 interrupt-parent = <&qeic>; 695 }; 696 697 ucc@2200 { 698 cell-index = <3>; 699 reg = <0x2200 0x200>; 700 interrupts = <34>; 701 interrupt-parent = <&qeic>; 702 }; 703 704 muram@10000 { 705 #address-cells = <1>; 706 #size-cells = <1>; 707 compatible = "fsl,qe-muram", "fsl,cpm-muram"; 708 ranges = <0x0 0x10000 0x6000>; 709 710 data-only@0 { 711 compatible = "fsl,qe-muram-data", 712 "fsl,cpm-muram-data"; 713 reg = <0x0 0x6000>; 714 }; 715 }; 716 }; 717 718 lpuart0: serial@2950000 { 719 compatible = "fsl,ls1021a-lpuart"; 720 reg = <0x0 0x2950000 0x0 0x1000>; 721 interrupts = <0 48 0x4>; 722 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>; 723 clock-names = "ipg"; 724 status = "disabled"; 725 }; 726 727 lpuart1: serial@2960000 { 728 compatible = "fsl,ls1021a-lpuart"; 729 reg = <0x0 0x2960000 0x0 0x1000>; 730 interrupts = <0 49 0x4>; 731 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 732 QORIQ_CLK_PLL_DIV(1)>; 733 clock-names = "ipg"; 734 status = "disabled"; 735 }; 736 737 lpuart2: serial@2970000 { 738 compatible = "fsl,ls1021a-lpuart"; 739 reg = <0x0 0x2970000 0x0 0x1000>; 740 interrupts = <0 50 0x4>; 741 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 742 QORIQ_CLK_PLL_DIV(1)>; 743 clock-names = "ipg"; 744 status = "disabled"; 745 }; 746 747 lpuart3: serial@2980000 { 748 compatible = "fsl,ls1021a-lpuart"; 749 reg = <0x0 0x2980000 0x0 0x1000>; 750 interrupts = <0 51 0x4>; 751 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 752 QORIQ_CLK_PLL_DIV(1)>; 753 clock-names = "ipg"; 754 status = "disabled"; 755 }; 756 757 lpuart4: serial@2990000 { 758 compatible = "fsl,ls1021a-lpuart"; 759 reg = <0x0 0x2990000 0x0 0x1000>; 760 interrupts = <0 52 0x4>; 761 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 762 QORIQ_CLK_PLL_DIV(1)>; 763 clock-names = "ipg"; 764 status = "disabled"; 765 }; 766 767 lpuart5: serial@29a0000 { 768 compatible = "fsl,ls1021a-lpuart"; 769 reg = <0x0 0x29a0000 0x0 0x1000>; 770 interrupts = <0 53 0x4>; 771 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 772 QORIQ_CLK_PLL_DIV(1)>; 773 clock-names = "ipg"; 774 status = "disabled"; 775 }; 776 777 wdog0: watchdog@2ad0000 { 778 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; 779 reg = <0x0 0x2ad0000 0x0 0x10000>; 780 interrupts = <0 83 0x4>; 781 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 782 QORIQ_CLK_PLL_DIV(1)>; 783 clock-names = "wdog"; 784 big-endian; 785 }; 786 787 edma0: edma@2c00000 { 788 #dma-cells = <2>; 789 compatible = "fsl,vf610-edma"; 790 reg = <0x0 0x2c00000 0x0 0x10000>, 791 <0x0 0x2c10000 0x0 0x10000>, 792 <0x0 0x2c20000 0x0 0x10000>; 793 interrupts = <0 103 0x4>, 794 <0 103 0x4>; 795 interrupt-names = "edma-tx", "edma-err"; 796 dma-channels = <32>; 797 big-endian; 798 clock-names = "dmamux0", "dmamux1"; 799 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 800 QORIQ_CLK_PLL_DIV(1)>, 801 <&clockgen QORIQ_CLK_PLATFORM_PLL 802 QORIQ_CLK_PLL_DIV(1)>; 803 }; 804 805 usb0: usb@2f00000 { 806 compatible = "snps,dwc3"; 807 reg = <0x0 0x2f00000 0x0 0x10000>; 808 interrupts = <0 60 0x4>; 809 dr_mode = "host"; 810 snps,quirk-frame-length-adjustment = <0x20>; 811 snps,dis_rxdet_inp3_quirk; 812 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 813 status = "disabled"; 814 }; 815 816 usb1: usb@3000000 { 817 compatible = "snps,dwc3"; 818 reg = <0x0 0x3000000 0x0 0x10000>; 819 interrupts = <0 61 0x4>; 820 dr_mode = "host"; 821 snps,quirk-frame-length-adjustment = <0x20>; 822 snps,dis_rxdet_inp3_quirk; 823 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 824 status = "disabled"; 825 }; 826 827 usb2: usb@3100000 { 828 compatible = "snps,dwc3"; 829 reg = <0x0 0x3100000 0x0 0x10000>; 830 interrupts = <0 63 0x4>; 831 dr_mode = "host"; 832 snps,quirk-frame-length-adjustment = <0x20>; 833 snps,dis_rxdet_inp3_quirk; 834 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 835 status = "disabled"; 836 }; 837 838 sata: sata@3200000 { 839 compatible = "fsl,ls1043a-ahci"; 840 reg = <0x0 0x3200000 0x0 0x10000>, 841 <0x0 0x20140520 0x0 0x4>; 842 reg-names = "ahci", "sata-ecc"; 843 interrupts = <0 69 0x4>; 844 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 845 QORIQ_CLK_PLL_DIV(1)>; 846 dma-coherent; 847 }; 848 849 msi1: msi-controller1@1571000 { 850 compatible = "fsl,ls1043a-msi"; 851 reg = <0x0 0x1571000 0x0 0x8>; 852 msi-controller; 853 interrupts = <0 116 0x4>; 854 }; 855 856 msi2: msi-controller2@1572000 { 857 compatible = "fsl,ls1043a-msi"; 858 reg = <0x0 0x1572000 0x0 0x8>; 859 msi-controller; 860 interrupts = <0 126 0x4>; 861 }; 862 863 msi3: msi-controller3@1573000 { 864 compatible = "fsl,ls1043a-msi"; 865 reg = <0x0 0x1573000 0x0 0x8>; 866 msi-controller; 867 interrupts = <0 160 0x4>; 868 }; 869 870 pcie1: pcie@3400000 { 871 compatible = "fsl,ls1043a-pcie"; 872 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 873 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 874 reg-names = "regs", "config"; 875 interrupts = <0 118 0x4>, /* controller interrupt */ 876 <0 117 0x4>; /* PME interrupt */ 877 interrupt-names = "intr", "pme"; 878 #address-cells = <3>; 879 #size-cells = <2>; 880 device_type = "pci"; 881 dma-coherent; 882 num-viewport = <6>; 883 bus-range = <0x0 0xff>; 884 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 885 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 886 msi-parent = <&msi1>, <&msi2>, <&msi3>; 887 #interrupt-cells = <1>; 888 interrupt-map-mask = <0 0 0 7>; 889 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, 890 <0000 0 0 2 &gic 0 111 0x4>, 891 <0000 0 0 3 &gic 0 112 0x4>, 892 <0000 0 0 4 &gic 0 113 0x4>; 893 status = "disabled"; 894 }; 895 896 pcie2: pcie@3500000 { 897 compatible = "fsl,ls1043a-pcie"; 898 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 899 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 900 reg-names = "regs", "config"; 901 interrupts = <0 128 0x4>, 902 <0 127 0x4>; 903 interrupt-names = "intr", "pme"; 904 #address-cells = <3>; 905 #size-cells = <2>; 906 device_type = "pci"; 907 dma-coherent; 908 num-viewport = <6>; 909 bus-range = <0x0 0xff>; 910 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 911 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 912 msi-parent = <&msi1>, <&msi2>, <&msi3>; 913 #interrupt-cells = <1>; 914 interrupt-map-mask = <0 0 0 7>; 915 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, 916 <0000 0 0 2 &gic 0 121 0x4>, 917 <0000 0 0 3 &gic 0 122 0x4>, 918 <0000 0 0 4 &gic 0 123 0x4>; 919 status = "disabled"; 920 }; 921 922 pcie3: pcie@3600000 { 923 compatible = "fsl,ls1043a-pcie"; 924 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 925 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 926 reg-names = "regs", "config"; 927 interrupts = <0 162 0x4>, 928 <0 161 0x4>; 929 interrupt-names = "intr", "pme"; 930 #address-cells = <3>; 931 #size-cells = <2>; 932 device_type = "pci"; 933 dma-coherent; 934 num-viewport = <6>; 935 bus-range = <0x0 0xff>; 936 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 937 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 938 msi-parent = <&msi1>, <&msi2>, <&msi3>; 939 #interrupt-cells = <1>; 940 interrupt-map-mask = <0 0 0 7>; 941 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, 942 <0000 0 0 2 &gic 0 155 0x4>, 943 <0000 0 0 3 &gic 0 156 0x4>, 944 <0000 0 0 4 &gic 0 157 0x4>; 945 status = "disabled"; 946 }; 947 948 qdma: dma-controller@8380000 { 949 compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma"; 950 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 951 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 952 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 953 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 958 interrupt-names = "qdma-error", "qdma-queue0", 959 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 960 dma-channels = <8>; 961 block-number = <1>; 962 block-offset = <0x10000>; 963 fsl,dma-queues = <2>; 964 status-sizes = <64>; 965 queue-sizes = <64 64>; 966 big-endian; 967 }; 968 969 rcpm: power-controller@1ee2140 { 970 compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+"; 971 reg = <0x0 0x1ee2140 0x0 0x4>; 972 #fsl,rcpm-wakeup-cells = <1>; 973 }; 974 975 ftm_alarm0: timer@29d0000 { 976 compatible = "fsl,ls1043a-ftm-alarm"; 977 reg = <0x0 0x29d0000 0x0 0x10000>; 978 fsl,rcpm-wakeup = <&rcpm 0x20000>; 979 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 980 big-endian; 981 }; 982 }; 983 984 firmware { 985 optee { 986 compatible = "linaro,optee-tz"; 987 method = "smc"; 988 }; 989 }; 990 991}; 992 993#include "qoriq-qman-portals.dtsi" 994#include "qoriq-bman-portals.dtsi" 995