1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018-2020 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "fsl,ls1028a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a72"; 28 reg = <0x0>; 29 enable-method = "psci"; 30 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 31 next-level-cache = <&l2>; 32 cpu-idle-states = <&CPU_PW20>; 33 #cooling-cells = <2>; 34 }; 35 36 cpu1: cpu@1 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a72"; 39 reg = <0x1>; 40 enable-method = "psci"; 41 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 42 next-level-cache = <&l2>; 43 cpu-idle-states = <&CPU_PW20>; 44 #cooling-cells = <2>; 45 }; 46 47 l2: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 cache-unified; 51 }; 52 }; 53 54 idle-states { 55 /* 56 * PSCI node is not added default, U-boot will add missing 57 * parts if it determines to use PSCI. 58 */ 59 entry-method = "psci"; 60 61 CPU_PW20: cpu-pw20 { 62 compatible = "arm,idle-state"; 63 idle-state-name = "PW20"; 64 arm,psci-suspend-param = <0x0>; 65 entry-latency-us = <2000>; 66 exit-latency-us = <2000>; 67 min-residency-us = <6000>; 68 }; 69 }; 70 71 rtc_clk: rtc-clk { 72 compatible = "fixed-clock"; 73 #clock-cells = <0>; 74 clock-frequency = <32768>; 75 clock-output-names = "rtc_clk"; 76 }; 77 78 sysclk: sysclk { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <100000000>; 82 clock-output-names = "sysclk"; 83 }; 84 85 osc_27m: clock-osc-27m { 86 compatible = "fixed-clock"; 87 #clock-cells = <0>; 88 clock-frequency = <27000000>; 89 clock-output-names = "phy_27m"; 90 }; 91 92 firmware { 93 optee: optee { 94 compatible = "linaro,optee-tz"; 95 method = "smc"; 96 status = "disabled"; 97 }; 98 }; 99 100 reboot { 101 compatible = "syscon-reboot"; 102 regmap = <&rst>; 103 offset = <0>; 104 mask = <0x02>; 105 }; 106 107 timer { 108 compatible = "arm,armv8-timer"; 109 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 110 IRQ_TYPE_LEVEL_LOW)>, 111 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 112 IRQ_TYPE_LEVEL_LOW)>, 113 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 114 IRQ_TYPE_LEVEL_LOW)>, 115 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 116 IRQ_TYPE_LEVEL_LOW)>; 117 }; 118 119 pmu { 120 compatible = "arm,cortex-a72-pmu"; 121 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 122 }; 123 124 gic: interrupt-controller@6000000 { 125 compatible = "arm,gic-v3"; 126 #address-cells = <2>; 127 #size-cells = <2>; 128 ranges; 129 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 130 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 131 #interrupt-cells = <3>; 132 interrupt-controller; 133 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 134 IRQ_TYPE_LEVEL_LOW)>; 135 its: msi-controller@6020000 { 136 compatible = "arm,gic-v3-its"; 137 msi-controller; 138 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 139 }; 140 }; 141 142 thermal-zones { 143 ddr-controller { 144 polling-delay-passive = <1000>; 145 polling-delay = <5000>; 146 thermal-sensors = <&tmu 0>; 147 148 trips { 149 ddr-ctrler-alert { 150 temperature = <85000>; 151 hysteresis = <2000>; 152 type = "passive"; 153 }; 154 155 ddr-ctrler-crit { 156 temperature = <95000>; 157 hysteresis = <2000>; 158 type = "critical"; 159 }; 160 }; 161 }; 162 163 core-cluster { 164 polling-delay-passive = <1000>; 165 polling-delay = <5000>; 166 thermal-sensors = <&tmu 1>; 167 168 trips { 169 core_cluster_alert: core-cluster-alert { 170 temperature = <85000>; 171 hysteresis = <2000>; 172 type = "passive"; 173 }; 174 175 core_cluster_crit: core-cluster-crit { 176 temperature = <95000>; 177 hysteresis = <2000>; 178 type = "critical"; 179 }; 180 }; 181 182 cooling-maps { 183 map0 { 184 trip = <&core_cluster_alert>; 185 cooling-device = 186 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 187 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 188 }; 189 }; 190 }; 191 }; 192 193 soc: soc { 194 compatible = "simple-bus"; 195 #address-cells = <2>; 196 #size-cells = <2>; 197 ranges; 198 199 ddr: memory-controller@1080000 { 200 compatible = "fsl,qoriq-memory-controller"; 201 reg = <0x0 0x1080000 0x0 0x1000>; 202 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 203 little-endian; 204 }; 205 206 dcfg: syscon@1e00000 { 207 #address-cells = <1>; 208 #size-cells = <1>; 209 compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; 210 reg = <0x0 0x1e00000 0x0 0x10000>; 211 ranges = <0x0 0x0 0x1e00000 0x10000>; 212 little-endian; 213 214 fspi_clk: clock-controller@900 { 215 compatible = "fsl,ls1028a-flexspi-clk"; 216 reg = <0x900 0x4>; 217 #clock-cells = <0>; 218 clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; 219 clock-output-names = "fspi_clk"; 220 }; 221 }; 222 223 rst: syscon@1e60000 { 224 compatible = "syscon"; 225 reg = <0x0 0x1e60000 0x0 0x10000>; 226 little-endian; 227 }; 228 229 sfp: efuse@1e80000 { 230 compatible = "fsl,ls1028a-sfp"; 231 reg = <0x0 0x1e80000 0x0 0x10000>; 232 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 233 QORIQ_CLK_PLL_DIV(4)>; 234 clock-names = "sfp"; 235 #address-cells = <1>; 236 #size-cells = <1>; 237 238 ls1028a_uid: unique-id@1c { 239 reg = <0x1c 0x8>; 240 }; 241 }; 242 243 scfg: syscon@1fc0000 { 244 compatible = "fsl,ls1028a-scfg", "syscon"; 245 reg = <0x0 0x1fc0000 0x0 0x10000>; 246 big-endian; 247 }; 248 249 clockgen: clock-controller@1300000 { 250 compatible = "fsl,ls1028a-clockgen"; 251 reg = <0x0 0x1300000 0x0 0xa0000>; 252 #clock-cells = <2>; 253 clocks = <&sysclk>; 254 }; 255 256 i2c0: i2c@2000000 { 257 compatible = "fsl,vf610-i2c"; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 reg = <0x0 0x2000000 0x0 0x10000>; 261 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 263 QORIQ_CLK_PLL_DIV(4)>; 264 status = "disabled"; 265 }; 266 267 i2c1: i2c@2010000 { 268 compatible = "fsl,vf610-i2c"; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 reg = <0x0 0x2010000 0x0 0x10000>; 272 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 274 QORIQ_CLK_PLL_DIV(4)>; 275 status = "disabled"; 276 }; 277 278 i2c2: i2c@2020000 { 279 compatible = "fsl,vf610-i2c"; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 reg = <0x0 0x2020000 0x0 0x10000>; 283 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 285 QORIQ_CLK_PLL_DIV(4)>; 286 status = "disabled"; 287 }; 288 289 i2c3: i2c@2030000 { 290 compatible = "fsl,vf610-i2c"; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 reg = <0x0 0x2030000 0x0 0x10000>; 294 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 296 QORIQ_CLK_PLL_DIV(4)>; 297 status = "disabled"; 298 }; 299 300 i2c4: i2c@2040000 { 301 compatible = "fsl,vf610-i2c"; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 reg = <0x0 0x2040000 0x0 0x10000>; 305 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 307 QORIQ_CLK_PLL_DIV(4)>; 308 status = "disabled"; 309 }; 310 311 i2c5: i2c@2050000 { 312 compatible = "fsl,vf610-i2c"; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 reg = <0x0 0x2050000 0x0 0x10000>; 316 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 318 QORIQ_CLK_PLL_DIV(4)>; 319 status = "disabled"; 320 }; 321 322 i2c6: i2c@2060000 { 323 compatible = "fsl,vf610-i2c"; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 reg = <0x0 0x2060000 0x0 0x10000>; 327 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 329 QORIQ_CLK_PLL_DIV(4)>; 330 status = "disabled"; 331 }; 332 333 i2c7: i2c@2070000 { 334 compatible = "fsl,vf610-i2c"; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 reg = <0x0 0x2070000 0x0 0x10000>; 338 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 340 QORIQ_CLK_PLL_DIV(4)>; 341 status = "disabled"; 342 }; 343 344 fspi: spi@20c0000 { 345 compatible = "nxp,lx2160a-fspi"; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 reg = <0x0 0x20c0000 0x0 0x10000>, 349 <0x0 0x20000000 0x0 0x10000000>; 350 reg-names = "fspi_base", "fspi_mmap"; 351 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&fspi_clk>, <&fspi_clk>; 353 clock-names = "fspi_en", "fspi"; 354 status = "disabled"; 355 }; 356 357 dspi0: spi@2100000 { 358 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 reg = <0x0 0x2100000 0x0 0x10000>; 362 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 363 clock-names = "dspi"; 364 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 365 QORIQ_CLK_PLL_DIV(2)>; 366 dmas = <&edma0 0 62>, <&edma0 0 60>; 367 dma-names = "tx", "rx"; 368 spi-num-chipselects = <4>; 369 little-endian; 370 status = "disabled"; 371 }; 372 373 dspi1: spi@2110000 { 374 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 reg = <0x0 0x2110000 0x0 0x10000>; 378 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 379 clock-names = "dspi"; 380 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 381 QORIQ_CLK_PLL_DIV(2)>; 382 dmas = <&edma0 0 58>, <&edma0 0 56>; 383 dma-names = "tx", "rx"; 384 spi-num-chipselects = <4>; 385 little-endian; 386 status = "disabled"; 387 }; 388 389 dspi2: spi@2120000 { 390 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 reg = <0x0 0x2120000 0x0 0x10000>; 394 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 395 clock-names = "dspi"; 396 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 397 QORIQ_CLK_PLL_DIV(2)>; 398 dmas = <&edma0 0 54>, <&edma0 0 2>; 399 dma-names = "tx", "rx"; 400 spi-num-chipselects = <3>; 401 little-endian; 402 status = "disabled"; 403 }; 404 405 esdhc: mmc@2140000 { 406 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 407 reg = <0x0 0x2140000 0x0 0x10000>; 408 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 409 clock-frequency = <0>; /* fixed up by bootloader */ 410 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 411 voltage-ranges = <1800 1800 3300 3300>; 412 sdhci,auto-cmd12; 413 little-endian; 414 bus-width = <4>; 415 status = "disabled"; 416 }; 417 418 esdhc1: mmc@2150000 { 419 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 420 reg = <0x0 0x2150000 0x0 0x10000>; 421 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 422 clock-frequency = <0>; /* fixed up by bootloader */ 423 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 424 voltage-ranges = <1800 1800>; 425 sdhci,auto-cmd12; 426 non-removable; 427 little-endian; 428 bus-width = <4>; 429 status = "disabled"; 430 }; 431 432 can0: can@2180000 { 433 compatible = "fsl,lx2160ar1-flexcan"; 434 reg = <0x0 0x2180000 0x0 0x10000>; 435 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 437 QORIQ_CLK_PLL_DIV(2)>, 438 <&clockgen QORIQ_CLK_PLATFORM_PLL 439 QORIQ_CLK_PLL_DIV(2)>; 440 clock-names = "ipg", "per"; 441 status = "disabled"; 442 }; 443 444 can1: can@2190000 { 445 compatible = "fsl,lx2160ar1-flexcan"; 446 reg = <0x0 0x2190000 0x0 0x10000>; 447 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 449 QORIQ_CLK_PLL_DIV(2)>, 450 <&clockgen QORIQ_CLK_PLATFORM_PLL 451 QORIQ_CLK_PLL_DIV(2)>; 452 clock-names = "ipg", "per"; 453 status = "disabled"; 454 }; 455 456 duart0: serial@21c0500 { 457 compatible = "fsl,ns16550", "ns16550a"; 458 reg = <0x00 0x21c0500 0x0 0x100>; 459 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 461 QORIQ_CLK_PLL_DIV(2)>; 462 status = "disabled"; 463 }; 464 465 duart1: serial@21c0600 { 466 compatible = "fsl,ns16550", "ns16550a"; 467 reg = <0x00 0x21c0600 0x0 0x100>; 468 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 470 QORIQ_CLK_PLL_DIV(2)>; 471 status = "disabled"; 472 }; 473 474 475 lpuart0: serial@2260000 { 476 compatible = "fsl,ls1028a-lpuart"; 477 reg = <0x0 0x2260000 0x0 0x1000>; 478 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 480 QORIQ_CLK_PLL_DIV(2)>; 481 clock-names = "ipg"; 482 dma-names = "rx","tx"; 483 dmas = <&edma0 1 32>, 484 <&edma0 1 33>; 485 status = "disabled"; 486 }; 487 488 lpuart1: serial@2270000 { 489 compatible = "fsl,ls1028a-lpuart"; 490 reg = <0x0 0x2270000 0x0 0x1000>; 491 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 493 QORIQ_CLK_PLL_DIV(2)>; 494 clock-names = "ipg"; 495 dma-names = "rx","tx"; 496 dmas = <&edma0 1 30>, 497 <&edma0 1 31>; 498 status = "disabled"; 499 }; 500 501 lpuart2: serial@2280000 { 502 compatible = "fsl,ls1028a-lpuart"; 503 reg = <0x0 0x2280000 0x0 0x1000>; 504 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 506 QORIQ_CLK_PLL_DIV(2)>; 507 clock-names = "ipg"; 508 dma-names = "rx","tx"; 509 dmas = <&edma0 1 28>, 510 <&edma0 1 29>; 511 status = "disabled"; 512 }; 513 514 lpuart3: serial@2290000 { 515 compatible = "fsl,ls1028a-lpuart"; 516 reg = <0x0 0x2290000 0x0 0x1000>; 517 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 519 QORIQ_CLK_PLL_DIV(2)>; 520 clock-names = "ipg"; 521 dma-names = "rx","tx"; 522 dmas = <&edma0 1 26>, 523 <&edma0 1 27>; 524 status = "disabled"; 525 }; 526 527 lpuart4: serial@22a0000 { 528 compatible = "fsl,ls1028a-lpuart"; 529 reg = <0x0 0x22a0000 0x0 0x1000>; 530 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 532 QORIQ_CLK_PLL_DIV(2)>; 533 clock-names = "ipg"; 534 dma-names = "rx","tx"; 535 dmas = <&edma0 1 24>, 536 <&edma0 1 25>; 537 status = "disabled"; 538 }; 539 540 lpuart5: serial@22b0000 { 541 compatible = "fsl,ls1028a-lpuart"; 542 reg = <0x0 0x22b0000 0x0 0x1000>; 543 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 545 QORIQ_CLK_PLL_DIV(2)>; 546 clock-names = "ipg"; 547 dma-names = "rx","tx"; 548 dmas = <&edma0 1 22>, 549 <&edma0 1 23>; 550 status = "disabled"; 551 }; 552 553 edma0: dma-controller@22c0000 { 554 #dma-cells = <2>; 555 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; 556 reg = <0x0 0x22c0000 0x0 0x10000>, 557 <0x0 0x22d0000 0x0 0x10000>, 558 <0x0 0x22e0000 0x0 0x10000>; 559 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 561 interrupt-names = "edma-tx", "edma-err"; 562 dma-channels = <32>; 563 clock-names = "dmamux0", "dmamux1"; 564 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 565 QORIQ_CLK_PLL_DIV(2)>, 566 <&clockgen QORIQ_CLK_PLATFORM_PLL 567 QORIQ_CLK_PLL_DIV(2)>; 568 }; 569 570 gpio1: gpio@2300000 { 571 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 572 reg = <0x0 0x2300000 0x0 0x10000>; 573 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 574 gpio-controller; 575 #gpio-cells = <2>; 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 little-endian; 579 }; 580 581 gpio2: gpio@2310000 { 582 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 583 reg = <0x0 0x2310000 0x0 0x10000>; 584 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 585 gpio-controller; 586 #gpio-cells = <2>; 587 interrupt-controller; 588 #interrupt-cells = <2>; 589 little-endian; 590 }; 591 592 gpio3: gpio@2320000 { 593 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 594 reg = <0x0 0x2320000 0x0 0x10000>; 595 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 596 gpio-controller; 597 #gpio-cells = <2>; 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 little-endian; 601 }; 602 603 usb0: usb@3100000 { 604 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 605 reg = <0x0 0x3100000 0x0 0x10000>; 606 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 607 snps,dis_rxdet_inp3_quirk; 608 snps,quirk-frame-length-adjustment = <0x20>; 609 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 610 status = "disabled"; 611 }; 612 613 usb1: usb@3110000 { 614 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 615 reg = <0x0 0x3110000 0x0 0x10000>; 616 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 617 snps,dis_rxdet_inp3_quirk; 618 snps,quirk-frame-length-adjustment = <0x20>; 619 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 620 status = "disabled"; 621 }; 622 623 sata: sata@3200000 { 624 compatible = "fsl,ls1028a-ahci"; 625 reg = <0x0 0x3200000 0x0 0x10000>, 626 <0x7 0x100520 0x0 0x4>; 627 reg-names = "ahci", "sata-ecc"; 628 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 630 QORIQ_CLK_PLL_DIV(2)>; 631 status = "disabled"; 632 }; 633 634 pcie1: pcie@3400000 { 635 compatible = "fsl,ls1028a-pcie"; 636 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 637 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 638 reg-names = "regs", "config"; 639 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 640 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 641 interrupt-names = "pme", "aer"; 642 #address-cells = <3>; 643 #size-cells = <2>; 644 device_type = "pci"; 645 dma-coherent; 646 num-viewport = <8>; 647 bus-range = <0x0 0xff>; 648 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ 649 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 650 msi-parent = <&its>; 651 #interrupt-cells = <1>; 652 interrupt-map-mask = <0 0 0 7>; 653 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 654 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 655 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 656 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 657 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 658 status = "disabled"; 659 }; 660 661 pcie_ep1: pcie-ep@3400000 { 662 compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; 663 reg = <0x00 0x03400000 0x0 0x00100000 664 0x80 0x00000000 0x8 0x00000000>; 665 reg-names = "regs", "addr_space"; 666 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 667 interrupt-names = "pme"; 668 num-ib-windows = <6>; 669 num-ob-windows = <8>; 670 status = "disabled"; 671 }; 672 673 pcie2: pcie@3500000 { 674 compatible = "fsl,ls1028a-pcie"; 675 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 676 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 677 reg-names = "regs", "config"; 678 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 680 interrupt-names = "pme", "aer"; 681 #address-cells = <3>; 682 #size-cells = <2>; 683 device_type = "pci"; 684 dma-coherent; 685 num-viewport = <8>; 686 bus-range = <0x0 0xff>; 687 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ 688 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 689 msi-parent = <&its>; 690 #interrupt-cells = <1>; 691 interrupt-map-mask = <0 0 0 7>; 692 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 693 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 694 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 695 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 696 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 697 status = "disabled"; 698 }; 699 700 pcie_ep2: pcie-ep@3500000 { 701 compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; 702 reg = <0x00 0x03500000 0x0 0x00100000 703 0x88 0x00000000 0x8 0x00000000>; 704 reg-names = "regs", "addr_space"; 705 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 706 interrupt-names = "pme"; 707 num-ib-windows = <6>; 708 num-ob-windows = <8>; 709 status = "disabled"; 710 }; 711 712 smmu: iommu@5000000 { 713 compatible = "arm,mmu-500"; 714 reg = <0 0x5000000 0 0x800000>; 715 #global-interrupts = <8>; 716 #iommu-cells = <1>; 717 dma-coherent; 718 stream-match-mask = <0x7c00>; 719 /* global secure fault */ 720 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 721 /* combined secure interrupt */ 722 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 723 /* global non-secure fault */ 724 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 725 /* combined non-secure interrupt */ 726 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 727 /* performance counter interrupts 0-7 */ 728 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 730 /* per context interrupt, 64 interrupts */ 731 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 763 }; 764 765 crypto: crypto@8000000 { 766 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 767 fsl,sec-era = <10>; 768 #address-cells = <1>; 769 #size-cells = <1>; 770 ranges = <0x0 0x00 0x8000000 0x100000>; 771 reg = <0x00 0x8000000 0x0 0x100000>; 772 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 773 dma-coherent; 774 775 sec_jr0: jr@10000 { 776 compatible = "fsl,sec-v5.0-job-ring", 777 "fsl,sec-v4.0-job-ring"; 778 reg = <0x10000 0x10000>; 779 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 780 }; 781 782 sec_jr1: jr@20000 { 783 compatible = "fsl,sec-v5.0-job-ring", 784 "fsl,sec-v4.0-job-ring"; 785 reg = <0x20000 0x10000>; 786 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 787 }; 788 789 sec_jr2: jr@30000 { 790 compatible = "fsl,sec-v5.0-job-ring", 791 "fsl,sec-v4.0-job-ring"; 792 reg = <0x30000 0x10000>; 793 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 794 }; 795 796 sec_jr3: jr@40000 { 797 compatible = "fsl,sec-v5.0-job-ring", 798 "fsl,sec-v4.0-job-ring"; 799 reg = <0x40000 0x10000>; 800 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 801 }; 802 }; 803 804 qdma: dma-controller@8380000 { 805 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 806 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 807 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 808 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 809 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 814 interrupt-names = "qdma-error", "qdma-queue0", 815 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 816 dma-channels = <8>; 817 block-number = <1>; 818 block-offset = <0x10000>; 819 fsl,dma-queues = <2>; 820 status-sizes = <64>; 821 queue-sizes = <64 64>; 822 }; 823 824 cluster1_core0_watchdog: watchdog@c000000 { 825 compatible = "arm,sp805", "arm,primecell"; 826 reg = <0x0 0xc000000 0x0 0x1000>; 827 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 828 QORIQ_CLK_PLL_DIV(16)>, 829 <&clockgen QORIQ_CLK_PLATFORM_PLL 830 QORIQ_CLK_PLL_DIV(16)>; 831 clock-names = "wdog_clk", "apb_pclk"; 832 }; 833 834 cluster1_core1_watchdog: watchdog@c010000 { 835 compatible = "arm,sp805", "arm,primecell"; 836 reg = <0x0 0xc010000 0x0 0x1000>; 837 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 838 QORIQ_CLK_PLL_DIV(16)>, 839 <&clockgen QORIQ_CLK_PLATFORM_PLL 840 QORIQ_CLK_PLL_DIV(16)>; 841 clock-names = "wdog_clk", "apb_pclk"; 842 }; 843 844 malidp0: display@f080000 { 845 compatible = "arm,mali-dp500"; 846 reg = <0x0 0xf080000 0x0 0x10000>; 847 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 848 <0 223 IRQ_TYPE_LEVEL_HIGH>; 849 interrupt-names = "DE", "SE"; 850 clocks = <&dpclk>, 851 <&clockgen QORIQ_CLK_HWACCEL 2>, 852 <&clockgen QORIQ_CLK_HWACCEL 2>, 853 <&clockgen QORIQ_CLK_HWACCEL 2>; 854 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 855 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 856 arm,malidp-arqos-value = <0xd000d000>; 857 858 port { 859 dpi0_out: endpoint { 860 861 }; 862 }; 863 }; 864 865 gpu: gpu@f0c0000 { 866 compatible = "vivante,gc"; 867 reg = <0x0 0xf0c0000 0x0 0x10000>; 868 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&clockgen QORIQ_CLK_HWACCEL 2>, 870 <&clockgen QORIQ_CLK_HWACCEL 2>, 871 <&clockgen QORIQ_CLK_HWACCEL 2>; 872 clock-names = "core", "shader", "bus"; 873 #cooling-cells = <2>; 874 }; 875 876 sai1: audio-controller@f100000 { 877 #sound-dai-cells = <0>; 878 compatible = "fsl,vf610-sai"; 879 reg = <0x0 0xf100000 0x0 0x10000>; 880 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 882 QORIQ_CLK_PLL_DIV(2)>, 883 <&clockgen QORIQ_CLK_PLATFORM_PLL 884 QORIQ_CLK_PLL_DIV(2)>, 885 <&clockgen QORIQ_CLK_PLATFORM_PLL 886 QORIQ_CLK_PLL_DIV(2)>, 887 <&clockgen QORIQ_CLK_PLATFORM_PLL 888 QORIQ_CLK_PLL_DIV(2)>; 889 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 890 dma-names = "tx", "rx"; 891 dmas = <&edma0 1 4>, 892 <&edma0 1 3>; 893 fsl,sai-asynchronous; 894 status = "disabled"; 895 }; 896 897 sai2: audio-controller@f110000 { 898 #sound-dai-cells = <0>; 899 compatible = "fsl,vf610-sai"; 900 reg = <0x0 0xf110000 0x0 0x10000>; 901 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 903 QORIQ_CLK_PLL_DIV(2)>, 904 <&clockgen QORIQ_CLK_PLATFORM_PLL 905 QORIQ_CLK_PLL_DIV(2)>, 906 <&clockgen QORIQ_CLK_PLATFORM_PLL 907 QORIQ_CLK_PLL_DIV(2)>, 908 <&clockgen QORIQ_CLK_PLATFORM_PLL 909 QORIQ_CLK_PLL_DIV(2)>; 910 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 911 dma-names = "tx", "rx"; 912 dmas = <&edma0 1 6>, 913 <&edma0 1 5>; 914 fsl,sai-asynchronous; 915 status = "disabled"; 916 }; 917 918 sai3: audio-controller@f120000 { 919 #sound-dai-cells = <0>; 920 compatible = "fsl,vf610-sai"; 921 reg = <0x0 0xf120000 0x0 0x10000>; 922 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 923 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 924 QORIQ_CLK_PLL_DIV(2)>, 925 <&clockgen QORIQ_CLK_PLATFORM_PLL 926 QORIQ_CLK_PLL_DIV(2)>, 927 <&clockgen QORIQ_CLK_PLATFORM_PLL 928 QORIQ_CLK_PLL_DIV(2)>, 929 <&clockgen QORIQ_CLK_PLATFORM_PLL 930 QORIQ_CLK_PLL_DIV(2)>; 931 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 932 dma-names = "tx", "rx"; 933 dmas = <&edma0 1 8>, 934 <&edma0 1 7>; 935 fsl,sai-asynchronous; 936 status = "disabled"; 937 }; 938 939 sai4: audio-controller@f130000 { 940 #sound-dai-cells = <0>; 941 compatible = "fsl,vf610-sai"; 942 reg = <0x0 0xf130000 0x0 0x10000>; 943 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 944 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 945 QORIQ_CLK_PLL_DIV(2)>, 946 <&clockgen QORIQ_CLK_PLATFORM_PLL 947 QORIQ_CLK_PLL_DIV(2)>, 948 <&clockgen QORIQ_CLK_PLATFORM_PLL 949 QORIQ_CLK_PLL_DIV(2)>, 950 <&clockgen QORIQ_CLK_PLATFORM_PLL 951 QORIQ_CLK_PLL_DIV(2)>; 952 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 953 dma-names = "tx", "rx"; 954 dmas = <&edma0 1 10>, 955 <&edma0 1 9>; 956 fsl,sai-asynchronous; 957 status = "disabled"; 958 }; 959 960 sai5: audio-controller@f140000 { 961 #sound-dai-cells = <0>; 962 compatible = "fsl,vf610-sai"; 963 reg = <0x0 0xf140000 0x0 0x10000>; 964 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 966 QORIQ_CLK_PLL_DIV(2)>, 967 <&clockgen QORIQ_CLK_PLATFORM_PLL 968 QORIQ_CLK_PLL_DIV(2)>, 969 <&clockgen QORIQ_CLK_PLATFORM_PLL 970 QORIQ_CLK_PLL_DIV(2)>, 971 <&clockgen QORIQ_CLK_PLATFORM_PLL 972 QORIQ_CLK_PLL_DIV(2)>; 973 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 974 dma-names = "tx", "rx"; 975 dmas = <&edma0 1 12>, 976 <&edma0 1 11>; 977 fsl,sai-asynchronous; 978 status = "disabled"; 979 }; 980 981 sai6: audio-controller@f150000 { 982 #sound-dai-cells = <0>; 983 compatible = "fsl,vf610-sai"; 984 reg = <0x0 0xf150000 0x0 0x10000>; 985 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 987 QORIQ_CLK_PLL_DIV(2)>, 988 <&clockgen QORIQ_CLK_PLATFORM_PLL 989 QORIQ_CLK_PLL_DIV(2)>, 990 <&clockgen QORIQ_CLK_PLATFORM_PLL 991 QORIQ_CLK_PLL_DIV(2)>, 992 <&clockgen QORIQ_CLK_PLATFORM_PLL 993 QORIQ_CLK_PLL_DIV(2)>; 994 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 995 dma-names = "tx", "rx"; 996 dmas = <&edma0 1 14>, 997 <&edma0 1 13>; 998 fsl,sai-asynchronous; 999 status = "disabled"; 1000 }; 1001 1002 dpclk: clock-controller@f1f0000 { 1003 compatible = "fsl,ls1028a-plldig"; 1004 reg = <0x0 0xf1f0000 0x0 0x10000>; 1005 #clock-cells = <0>; 1006 clocks = <&osc_27m>; 1007 }; 1008 1009 tmu: tmu@1f80000 { 1010 compatible = "fsl,qoriq-tmu"; 1011 reg = <0x0 0x1f80000 0x0 0x10000>; 1012 interrupts = <0 23 0x4>; 1013 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 1014 fsl,tmu-calibration = <0x00000000 0x00000024 1015 0x00000001 0x0000002b 1016 0x00000002 0x00000031 1017 0x00000003 0x00000038 1018 0x00000004 0x0000003f 1019 0x00000005 0x00000045 1020 0x00000006 0x0000004c 1021 0x00000007 0x00000053 1022 0x00000008 0x00000059 1023 0x00000009 0x00000060 1024 0x0000000a 0x00000066 1025 0x0000000b 0x0000006d 1026 1027 0x00010000 0x0000001c 1028 0x00010001 0x00000024 1029 0x00010002 0x0000002c 1030 0x00010003 0x00000035 1031 0x00010004 0x0000003d 1032 0x00010005 0x00000045 1033 0x00010006 0x0000004d 1034 0x00010007 0x00000055 1035 0x00010008 0x0000005e 1036 0x00010009 0x00000066 1037 0x0001000a 0x0000006e 1038 1039 0x00020000 0x00000018 1040 0x00020001 0x00000022 1041 0x00020002 0x0000002d 1042 0x00020003 0x00000038 1043 0x00020004 0x00000043 1044 0x00020005 0x0000004d 1045 0x00020006 0x00000058 1046 0x00020007 0x00000063 1047 0x00020008 0x0000006e 1048 1049 0x00030000 0x00000010 1050 0x00030001 0x0000001c 1051 0x00030002 0x00000029 1052 0x00030003 0x00000036 1053 0x00030004 0x00000042 1054 0x00030005 0x0000004f 1055 0x00030006 0x0000005b 1056 0x00030007 0x00000068>; 1057 little-endian; 1058 #thermal-sensor-cells = <1>; 1059 }; 1060 1061 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 1062 compatible = "pci-host-ecam-generic"; 1063 reg = <0x01 0xf0000000 0x0 0x100000>; 1064 #address-cells = <3>; 1065 #size-cells = <2>; 1066 msi-parent = <&its>; 1067 device_type = "pci"; 1068 bus-range = <0x0 0x0>; 1069 dma-coherent; 1070 msi-map = <0 &its 0x17 0xe>; 1071 iommu-map = <0 &smmu 0x17 0xe>; 1072 /* PF0-6 BAR0 - non-prefetchable memory */ 1073 ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 1074 /* PF0-6 BAR2 - prefetchable memory */ 1075 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 1076 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 1077 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 1078 /* PF0: VF0-1 BAR2 - prefetchable memory */ 1079 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 1080 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 1081 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 1082 /* PF1: VF0-1 BAR2 - prefetchable memory */ 1083 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 1084 /* BAR4 (PF5) - non-prefetchable memory */ 1085 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; 1086 1087 enetc_port0: ethernet@0,0 { 1088 compatible = "fsl,enetc"; 1089 reg = <0x000000 0 0 0 0>; 1090 status = "disabled"; 1091 }; 1092 1093 enetc_port1: ethernet@0,1 { 1094 compatible = "fsl,enetc"; 1095 reg = <0x000100 0 0 0 0>; 1096 status = "disabled"; 1097 }; 1098 1099 enetc_port2: ethernet@0,2 { 1100 compatible = "fsl,enetc"; 1101 reg = <0x000200 0 0 0 0>; 1102 phy-mode = "internal"; 1103 status = "disabled"; 1104 1105 fixed-link { 1106 speed = <2500>; 1107 full-duplex; 1108 pause; 1109 }; 1110 }; 1111 1112 enetc_mdio_pf3: mdio@0,3 { 1113 compatible = "fsl,enetc-mdio"; 1114 reg = <0x000300 0 0 0 0>; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 }; 1118 1119 ethernet@0,4 { 1120 compatible = "fsl,enetc-ptp"; 1121 reg = <0x000400 0 0 0 0>; 1122 clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; 1123 little-endian; 1124 fsl,extts-fifo; 1125 }; 1126 1127 mscc_felix: ethernet-switch@0,5 { 1128 reg = <0x000500 0 0 0 0>; 1129 /* IEP INT_B */ 1130 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1131 status = "disabled"; 1132 1133 mscc_felix_ports: ports { 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 1137 /* External ports */ 1138 mscc_felix_port0: port@0 { 1139 reg = <0>; 1140 status = "disabled"; 1141 }; 1142 1143 mscc_felix_port1: port@1 { 1144 reg = <1>; 1145 status = "disabled"; 1146 }; 1147 1148 mscc_felix_port2: port@2 { 1149 reg = <2>; 1150 status = "disabled"; 1151 }; 1152 1153 mscc_felix_port3: port@3 { 1154 reg = <3>; 1155 status = "disabled"; 1156 }; 1157 1158 /* Internal ports */ 1159 mscc_felix_port4: port@4 { 1160 reg = <4>; 1161 phy-mode = "internal"; 1162 ethernet = <&enetc_port2>; 1163 status = "disabled"; 1164 1165 fixed-link { 1166 speed = <2500>; 1167 full-duplex; 1168 pause; 1169 }; 1170 }; 1171 1172 mscc_felix_port5: port@5 { 1173 reg = <5>; 1174 phy-mode = "internal"; 1175 ethernet = <&enetc_port3>; 1176 status = "disabled"; 1177 1178 fixed-link { 1179 speed = <1000>; 1180 full-duplex; 1181 pause; 1182 }; 1183 }; 1184 }; 1185 }; 1186 1187 enetc_port3: ethernet@0,6 { 1188 compatible = "fsl,enetc"; 1189 reg = <0x000600 0 0 0 0>; 1190 phy-mode = "internal"; 1191 status = "disabled"; 1192 1193 fixed-link { 1194 speed = <1000>; 1195 full-duplex; 1196 pause; 1197 }; 1198 }; 1199 1200 rcec@1f,0 { 1201 reg = <0x00f800 0 0 0 0>; 1202 /* IEP INT_A */ 1203 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1204 }; 1205 }; 1206 1207 /* Integrated Endpoint Register Block */ 1208 ierb@1f0800000 { 1209 compatible = "fsl,ls1028a-enetc-ierb"; 1210 reg = <0x01 0xf0800000 0x0 0x10000>; 1211 }; 1212 1213 pwm0: pwm@2800000 { 1214 compatible = "fsl,vf610-ftm-pwm"; 1215 #pwm-cells = <3>; 1216 reg = <0x0 0x2800000 0x0 0x10000>; 1217 clock-names = "ftm_sys", "ftm_ext", 1218 "ftm_fix", "ftm_cnt_clk_en"; 1219 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1220 <&rtc_clk>, <&clockgen 4 1>; 1221 status = "disabled"; 1222 }; 1223 1224 pwm1: pwm@2810000 { 1225 compatible = "fsl,vf610-ftm-pwm"; 1226 #pwm-cells = <3>; 1227 reg = <0x0 0x2810000 0x0 0x10000>; 1228 clock-names = "ftm_sys", "ftm_ext", 1229 "ftm_fix", "ftm_cnt_clk_en"; 1230 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1231 <&rtc_clk>, <&clockgen 4 1>; 1232 status = "disabled"; 1233 }; 1234 1235 pwm2: pwm@2820000 { 1236 compatible = "fsl,vf610-ftm-pwm"; 1237 #pwm-cells = <3>; 1238 reg = <0x0 0x2820000 0x0 0x10000>; 1239 clock-names = "ftm_sys", "ftm_ext", 1240 "ftm_fix", "ftm_cnt_clk_en"; 1241 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1242 <&rtc_clk>, <&clockgen 4 1>; 1243 status = "disabled"; 1244 }; 1245 1246 pwm3: pwm@2830000 { 1247 compatible = "fsl,vf610-ftm-pwm"; 1248 #pwm-cells = <3>; 1249 reg = <0x0 0x2830000 0x0 0x10000>; 1250 clock-names = "ftm_sys", "ftm_ext", 1251 "ftm_fix", "ftm_cnt_clk_en"; 1252 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1253 <&rtc_clk>, <&clockgen 4 1>; 1254 status = "disabled"; 1255 }; 1256 1257 pwm4: pwm@2840000 { 1258 compatible = "fsl,vf610-ftm-pwm"; 1259 #pwm-cells = <3>; 1260 reg = <0x0 0x2840000 0x0 0x10000>; 1261 clock-names = "ftm_sys", "ftm_ext", 1262 "ftm_fix", "ftm_cnt_clk_en"; 1263 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1264 <&rtc_clk>, <&clockgen 4 1>; 1265 status = "disabled"; 1266 }; 1267 1268 pwm5: pwm@2850000 { 1269 compatible = "fsl,vf610-ftm-pwm"; 1270 #pwm-cells = <3>; 1271 reg = <0x0 0x2850000 0x0 0x10000>; 1272 clock-names = "ftm_sys", "ftm_ext", 1273 "ftm_fix", "ftm_cnt_clk_en"; 1274 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1275 <&rtc_clk>, <&clockgen 4 1>; 1276 status = "disabled"; 1277 }; 1278 1279 pwm6: pwm@2860000 { 1280 compatible = "fsl,vf610-ftm-pwm"; 1281 #pwm-cells = <3>; 1282 reg = <0x0 0x2860000 0x0 0x10000>; 1283 clock-names = "ftm_sys", "ftm_ext", 1284 "ftm_fix", "ftm_cnt_clk_en"; 1285 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1286 <&rtc_clk>, <&clockgen 4 1>; 1287 status = "disabled"; 1288 }; 1289 1290 pwm7: pwm@2870000 { 1291 compatible = "fsl,vf610-ftm-pwm"; 1292 #pwm-cells = <3>; 1293 reg = <0x0 0x2870000 0x0 0x10000>; 1294 clock-names = "ftm_sys", "ftm_ext", 1295 "ftm_fix", "ftm_cnt_clk_en"; 1296 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 1297 <&rtc_clk>, <&clockgen 4 1>; 1298 status = "disabled"; 1299 }; 1300 1301 rcpm: power-controller@1e34040 { 1302 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1303 reg = <0x0 0x1e34040 0x0 0x1c>; 1304 #fsl,rcpm-wakeup-cells = <7>; 1305 little-endian; 1306 }; 1307 1308 ftm_alarm0: timer@2800000 { 1309 compatible = "fsl,ls1028a-ftm-alarm"; 1310 reg = <0x0 0x2800000 0x0 0x10000>; 1311 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1312 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1313 status = "disabled"; 1314 }; 1315 1316 ftm_alarm1: timer@2810000 { 1317 compatible = "fsl,ls1028a-ftm-alarm"; 1318 reg = <0x0 0x2810000 0x0 0x10000>; 1319 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1320 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1321 status = "disabled"; 1322 }; 1323 }; 1324 1325}; 1326