xref: /freebsd/sys/contrib/device-tree/src/arm64/exynos/exynosautov920.dtsi (revision 67be1e195acfaec99ce4fffeb17111ce085755f7) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's ExynosAutov920 SoC device tree source
4 *
5 * Copyright (c) 2023 Samsung Electronics Co., Ltd.
6 *
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/soc/samsung,exynos-usi.h>
11
12/ {
13	compatible = "samsung,exynosautov920";
14	#address-cells = <2>;
15	#size-cells = <1>;
16
17	interrupt-parent = <&gic>;
18
19	aliases {
20		pinctrl0 = &pinctrl_alive;
21		pinctrl1 = &pinctrl_aud;
22		pinctrl2 = &pinctrl_hsi0;
23		pinctrl3 = &pinctrl_hsi1;
24		pinctrl4 = &pinctrl_hsi2;
25		pinctrl5 = &pinctrl_hsi2ufs;
26		pinctrl6 = &pinctrl_peric0;
27		pinctrl7 = &pinctrl_peric1;
28	};
29
30	arm-pmu {
31		compatible = "arm,cortex-a78-pmu";
32		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
33	};
34
35	xtcxo: clock {
36		compatible = "fixed-clock";
37		#clock-cells = <0>;
38		clock-output-names = "oscclk";
39	};
40
41	/*
42	 * FIXME: Keep the stub clock for serial driver, until proper clock
43	 * driver is implemented.
44	 */
45	clock_usi: clock-usi {
46		compatible = "fixed-clock";
47		#clock-cells = <0>;
48		clock-frequency = <200000000>;
49		clock-output-names = "usi";
50	};
51
52	cpus: cpus {
53		#address-cells = <2>;
54		#size-cells = <0>;
55
56		cpu-map {
57			cluster0 {
58				core0 {
59					cpu = <&cpu0>;
60				};
61				core1 {
62					cpu = <&cpu1>;
63				};
64				core2 {
65					cpu = <&cpu2>;
66				};
67				core3 {
68					cpu = <&cpu3>;
69				};
70			};
71
72			cluster1 {
73				core0 {
74					cpu = <&cpu4>;
75				};
76				core1 {
77					cpu = <&cpu5>;
78				};
79				core2 {
80					cpu = <&cpu6>;
81				};
82				core3 {
83					cpu = <&cpu7>;
84				};
85			};
86
87			cluster2 {
88				core0 {
89					cpu = <&cpu8>;
90				};
91				core1 {
92					cpu = <&cpu9>;
93				};
94			};
95		};
96
97		cpu0: cpu@0 {
98			device_type = "cpu";
99			compatible = "arm,cortex-a78ae";
100			reg = <0x0 0x0>;
101			enable-method = "psci";
102		};
103
104		cpu1: cpu@100 {
105			device_type = "cpu";
106			compatible = "arm,cortex-a78ae";
107			reg = <0x0 0x100>;
108			enable-method = "psci";
109		};
110
111		cpu2: cpu@200 {
112			device_type = "cpu";
113			compatible = "arm,cortex-a78ae";
114			reg = <0x0 0x200>;
115			enable-method = "psci";
116		};
117
118		cpu3: cpu@300 {
119			device_type = "cpu";
120			compatible = "arm,cortex-a78ae";
121			reg = <0x0 0x300>;
122			enable-method = "psci";
123		};
124
125		cpu4: cpu@10000 {
126			device_type = "cpu";
127			compatible = "arm,cortex-a78ae";
128			reg = <0x0 0x10000>;
129			enable-method = "psci";
130		};
131
132		cpu5: cpu@10100 {
133			device_type = "cpu";
134			compatible = "arm,cortex-a78ae";
135			reg = <0x0 0x10100>;
136			enable-method = "psci";
137		};
138
139		cpu6: cpu@10200 {
140			device_type = "cpu";
141			compatible = "arm,cortex-a78ae";
142			reg = <0x0 0x10200>;
143			enable-method = "psci";
144		};
145
146		cpu7: cpu@10300 {
147			device_type = "cpu";
148			compatible = "arm,cortex-a78ae";
149			reg = <0x0 0x10300>;
150			enable-method = "psci";
151		};
152
153		cpu8: cpu@20000 {
154			device_type = "cpu";
155			compatible = "arm,cortex-a78ae";
156			reg = <0x0 0x20000>;
157			enable-method = "psci";
158		};
159
160		cpu9: cpu@20100 {
161			device_type = "cpu";
162			compatible = "arm,cortex-a78ae";
163			reg = <0x0 0x20100>;
164			enable-method = "psci";
165		};
166	};
167
168	psci {
169		compatible = "arm,psci-1.0";
170		method = "smc";
171	};
172
173	soc: soc@0 {
174		compatible = "simple-bus";
175		#address-cells = <1>;
176		#size-cells = <1>;
177		ranges = <0x0 0x0 0x0 0x20000000>;
178
179		chipid@10000000 {
180			compatible = "samsung,exynosautov920-chipid",
181				     "samsung,exynos850-chipid";
182			reg = <0x10000000 0x24>;
183		};
184
185		gic: interrupt-controller@10400000 {
186			compatible = "arm,gic-v3";
187			#interrupt-cells = <3>;
188			#address-cells = <0>;
189			interrupt-controller;
190			reg = <0x10400000 0x10000>,
191			      <0x10460000 0x140000>;
192			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
193		};
194
195		syscon_peric0: syscon@10820000 {
196			compatible = "samsung,exynosautov920-peric0-sysreg",
197				     "syscon";
198			reg = <0x10820000 0x2000>;
199		};
200
201		pinctrl_peric0: pinctrl@10830000 {
202			compatible = "samsung,exynosautov920-pinctrl";
203			reg = <0x10830000 0x10000>;
204			interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>;
205		};
206
207		usi_0: usi@108800c0 {
208			compatible = "samsung,exynosautov920-usi",
209				     "samsung,exynos850-usi";
210			reg = <0x108800c0 0x20>;
211			samsung,sysreg = <&syscon_peric0 0x1000>;
212			samsung,mode = <USI_V2_UART>;
213			#address-cells = <1>;
214			#size-cells = <1>;
215			ranges;
216			clocks = <&clock_usi>, <&clock_usi>;
217			clock-names = "pclk", "ipclk";
218			status = "disabled";
219
220			serial_0: serial@10880000 {
221				compatible = "samsung,exynosautov920-uart",
222					     "samsung,exynos850-uart";
223				reg = <0x10880000 0xc0>;
224				interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
225				pinctrl-names = "default";
226				pinctrl-0 = <&uart0_bus>;
227				clocks = <&clock_usi>, <&clock_usi>;
228				clock-names = "uart", "clk_uart_baud0";
229				samsung,uart-fifosize = <256>;
230				status = "disabled";
231			};
232		};
233
234		pwm: pwm@109b0000 {
235			compatible = "samsung,exynosautov920-pwm",
236				     "samsung,exynos4210-pwm";
237			reg = <0x109b0000 0x100>;
238			samsung,pwm-outputs = <0>, <1>, <2>, <3>;
239			#pwm-cells = <3>;
240			clocks = <&xtcxo>;
241			clock-names = "timers";
242			status = "disabled";
243		};
244
245		syscon_peric1: syscon@10c20000 {
246			compatible = "samsung,exynosautov920-peric1-sysreg",
247				     "syscon";
248			reg = <0x10c20000 0x2000>;
249		};
250
251		pinctrl_peric1: pinctrl@10c30000 {
252			compatible = "samsung,exynosautov920-pinctrl";
253			reg = <0x10c30000 0x10000>;
254			interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
255		};
256
257		pinctrl_alive: pinctrl@11850000 {
258			compatible = "samsung,exynosautov920-pinctrl";
259			reg = <0x11850000 0x10000>;
260
261			wakeup-interrupt-controller {
262				compatible = "samsung,exynosautov920-wakeup-eint";
263			};
264		};
265
266		pmu_system_controller: system-controller@11860000 {
267			compatible = "samsung,exynosautov920-pmu",
268				     "samsung,exynos7-pmu","syscon";
269			reg = <0x11860000 0x10000>;
270		};
271
272		pinctrl_hsi0: pinctrl@16040000 {
273			compatible = "samsung,exynosautov920-pinctrl";
274			reg = <0x16040000 0x10000>;
275			interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
276		};
277
278		pinctrl_hsi1: pinctrl@16450000 {
279			compatible = "samsung,exynosautov920-pinctrl";
280			reg = <0x16450000 0x10000>;
281			interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
282		};
283
284		pinctrl_hsi2: pinctrl@16c10000 {
285			compatible = "samsung,exynosautov920-pinctrl";
286			reg = <0x16c10000 0x10000>;
287			interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
288		};
289
290		pinctrl_hsi2ufs: pinctrl@16d20000 {
291			compatible = "samsung,exynosautov920-pinctrl";
292			reg = <0x16d20000 0x10000>;
293			interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
294		};
295
296		pinctrl_aud: pinctrl@1a460000 {
297			compatible = "samsung,exynosautov920-pinctrl";
298			reg = <0x1a460000 0x10000>;
299		};
300	};
301
302	timer {
303		compatible = "arm,armv8-timer";
304		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
305			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
306			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
307			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
308			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
309	};
310};
311
312#include "exynosautov920-pinctrl.dtsi"
313