1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung's ExynosAuto v9 SoC device tree source 4 * 5 * Copyright (c) 2021 Samsung Electronics Co., Ltd. 6 * 7 */ 8 9#include <dt-bindings/clock/samsung,exynosautov9.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/samsung,boot-mode.h> 12#include <dt-bindings/soc/samsung,exynos-usi.h> 13 14/ { 15 compatible = "samsung,exynosautov9"; 16 #address-cells = <2>; 17 #size-cells = <1>; 18 19 interrupt-parent = <&gic>; 20 21 aliases { 22 pinctrl0 = &pinctrl_alive; 23 pinctrl1 = &pinctrl_aud; 24 pinctrl2 = &pinctrl_fsys0; 25 pinctrl3 = &pinctrl_fsys1; 26 pinctrl4 = &pinctrl_fsys2; 27 pinctrl5 = &pinctrl_peric0; 28 pinctrl6 = &pinctrl_peric1; 29 }; 30 31 arm-pmu { 32 compatible = "arm,cortex-a76-pmu"; 33 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 41 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 42 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu-map { 50 cluster0 { 51 core0 { 52 cpu = <&cpu0>; 53 }; 54 core1 { 55 cpu = <&cpu1>; 56 }; 57 core2 { 58 cpu = <&cpu2>; 59 }; 60 core3 { 61 cpu = <&cpu3>; 62 }; 63 }; 64 65 cluster1 { 66 core0 { 67 cpu = <&cpu4>; 68 }; 69 core1 { 70 cpu = <&cpu5>; 71 }; 72 core2 { 73 cpu = <&cpu6>; 74 }; 75 core3 { 76 cpu = <&cpu7>; 77 }; 78 }; 79 }; 80 81 cpu0: cpu@0 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a76"; 84 reg = <0x0>; 85 enable-method = "psci"; 86 }; 87 88 cpu1: cpu@100 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a76"; 91 reg = <0x100>; 92 enable-method = "psci"; 93 }; 94 95 cpu2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a76"; 98 reg = <0x200>; 99 enable-method = "psci"; 100 }; 101 102 cpu3: cpu@300 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a76"; 105 reg = <0x300>; 106 enable-method = "psci"; 107 }; 108 109 cpu4: cpu@10000 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a76"; 112 reg = <0x10000>; 113 enable-method = "psci"; 114 }; 115 116 cpu5: cpu@10100 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a76"; 119 reg = <0x10100>; 120 enable-method = "psci"; 121 }; 122 123 cpu6: cpu@10200 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a76"; 126 reg = <0x10200>; 127 enable-method = "psci"; 128 }; 129 130 cpu7: cpu@10300 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a76"; 133 reg = <0x10300>; 134 enable-method = "psci"; 135 }; 136 }; 137 138 psci { 139 compatible = "arm,psci-1.0"; 140 method = "smc"; 141 cpu_suspend = <0xc4000001>; 142 cpu_off = <0x84000002>; 143 cpu_on = <0xc4000003>; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 149 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 152 }; 153 154 fixed-rate-clocks { 155 xtcxo: clock { 156 compatible = "fixed-clock"; 157 #clock-cells = <0>; 158 clock-output-names = "oscclk"; 159 }; 160 }; 161 162 soc: soc@0 { 163 compatible = "simple-bus"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 ranges = <0x0 0x0 0x0 0x20000000>; 167 168 chipid@10000000 { 169 compatible = "samsung,exynosautov9-chipid", 170 "samsung,exynos850-chipid"; 171 reg = <0x10000000 0x24>; 172 }; 173 174 cmu_peris: clock-controller@10020000 { 175 compatible = "samsung,exynosautov9-cmu-peris"; 176 reg = <0x10020000 0x8000>; 177 #clock-cells = <1>; 178 179 clocks = <&xtcxo>, 180 <&cmu_top DOUT_CLKCMU_PERIS_BUS>; 181 clock-names = "oscclk", 182 "dout_clkcmu_peris_bus"; 183 }; 184 185 cmu_peric0: clock-controller@10200000 { 186 compatible = "samsung,exynosautov9-cmu-peric0"; 187 reg = <0x10200000 0x8000>; 188 #clock-cells = <1>; 189 190 clocks = <&xtcxo>, 191 <&cmu_top DOUT_CLKCMU_PERIC0_BUS>, 192 <&cmu_top DOUT_CLKCMU_PERIC0_IP>; 193 clock-names = "oscclk", 194 "dout_clkcmu_peric0_bus", 195 "dout_clkcmu_peric0_ip"; 196 }; 197 198 cmu_peric1: clock-controller@10800000 { 199 compatible = "samsung,exynosautov9-cmu-peric1"; 200 reg = <0x10800000 0x8000>; 201 #clock-cells = <1>; 202 203 clocks = <&xtcxo>, 204 <&cmu_top DOUT_CLKCMU_PERIC1_BUS>, 205 <&cmu_top DOUT_CLKCMU_PERIC1_IP>; 206 clock-names = "oscclk", 207 "dout_clkcmu_peric1_bus", 208 "dout_clkcmu_peric1_ip"; 209 }; 210 211 cmu_fsys1: clock-controller@17040000 { 212 compatible = "samsung,exynosautov9-cmu-fsys1"; 213 reg = <0x17040000 0x8000>; 214 #clock-cells = <1>; 215 216 clocks = <&xtcxo>, 217 <&cmu_top DOUT_CLKCMU_FSYS1_BUS>, 218 <&cmu_top GOUT_CLKCMU_FSYS1_MMC_CARD>, 219 <&cmu_top DOUT_CLKCMU_FSYS1_USBDRD>; 220 clock-names = "oscclk", 221 "dout_clkcmu_fsys1_bus", 222 "gout_clkcmu_fsys1_mmc_card", 223 "dout_clkcmu_fsys1_usbdrd"; 224 }; 225 226 cmu_fsys0: clock-controller@17700000 { 227 compatible = "samsung,exynosautov9-cmu-fsys0"; 228 reg = <0x17700000 0x8000>; 229 #clock-cells = <1>; 230 231 clocks = <&xtcxo>, 232 <&cmu_top DOUT_CLKCMU_FSYS0_BUS>, 233 <&cmu_top DOUT_CLKCMU_FSYS0_PCIE>; 234 clock-names = "oscclk", 235 "dout_clkcmu_fsys0_bus", 236 "dout_clkcmu_fsys0_pcie"; 237 }; 238 239 cmu_fsys2: clock-controller@17c00000 { 240 compatible = "samsung,exynosautov9-cmu-fsys2"; 241 reg = <0x17c00000 0x8000>; 242 #clock-cells = <1>; 243 244 clocks = <&xtcxo>, 245 <&cmu_top DOUT_CLKCMU_FSYS2_BUS>, 246 <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>, 247 <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>; 248 clock-names = "oscclk", 249 "dout_clkcmu_fsys2_bus", 250 "dout_fsys2_clkcmu_ufs_embd", 251 "dout_fsys2_clkcmu_ethernet"; 252 }; 253 254 cmu_core: clock-controller@1b030000 { 255 compatible = "samsung,exynosautov9-cmu-core"; 256 reg = <0x1b030000 0x8000>; 257 #clock-cells = <1>; 258 259 clocks = <&xtcxo>, 260 <&cmu_top DOUT_CLKCMU_CORE_BUS>; 261 clock-names = "oscclk", 262 "dout_clkcmu_core_bus"; 263 }; 264 265 cmu_busmc: clock-controller@1b200000 { 266 compatible = "samsung,exynosautov9-cmu-busmc"; 267 reg = <0x1b200000 0x8000>; 268 #clock-cells = <1>; 269 270 clocks = <&xtcxo>, 271 <&cmu_top DOUT_CLKCMU_BUSMC_BUS>; 272 clock-names = "oscclk", 273 "dout_clkcmu_busmc_bus"; 274 }; 275 276 cmu_top: clock-controller@1b240000 { 277 compatible = "samsung,exynosautov9-cmu-top"; 278 reg = <0x1b240000 0x8000>; 279 #clock-cells = <1>; 280 281 clocks = <&xtcxo>; 282 clock-names = "oscclk"; 283 }; 284 285 gic: interrupt-controller@10101000 { 286 compatible = "arm,gic-400"; 287 #interrupt-cells = <3>; 288 #address-cells = <0>; 289 interrupt-controller; 290 reg = <0x10101000 0x1000>, 291 <0x10102000 0x2000>, 292 <0x10104000 0x2000>, 293 <0x10106000 0x2000>; 294 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 295 IRQ_TYPE_LEVEL_HIGH)>; 296 }; 297 298 pdma0: dma-controller@1b2e0000 { 299 compatible = "arm,pl330", "arm,primecell"; 300 reg = <0x1b2e0000 0x1000>; 301 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&cmu_busmc CLK_GOUT_BUSMC_PDMA0_PCLK>; 303 clock-names = "apb_pclk"; 304 arm,pl330-broken-no-flushp; 305 #dma-cells = <1>; 306 }; 307 308 pinctrl_alive: pinctrl@10450000 { 309 compatible = "samsung,exynosautov9-pinctrl"; 310 reg = <0x10450000 0x1000>; 311 312 wakeup-interrupt-controller { 313 compatible = "samsung,exynosautov9-wakeup-eint", 314 "samsung,exynos850-wakeup-eint", 315 "samsung,exynos7-wakeup-eint"; 316 }; 317 }; 318 319 pinctrl_aud: pinctrl@19c60000 { 320 compatible = "samsung,exynosautov9-pinctrl"; 321 reg = <0x19c60000 0x1000>; 322 }; 323 324 pinctrl_fsys0: pinctrl@17740000 { 325 compatible = "samsung,exynosautov9-pinctrl"; 326 reg = <0x17740000 0x1000>; 327 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 328 }; 329 330 pinctrl_fsys1: pinctrl@17060000 { 331 compatible = "samsung,exynosautov9-pinctrl"; 332 reg = <0x17060000 0x1000>; 333 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 334 }; 335 336 pinctrl_fsys2: pinctrl@17c30000 { 337 compatible = "samsung,exynosautov9-pinctrl"; 338 reg = <0x17c30000 0x1000>; 339 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 340 }; 341 342 pinctrl_peric0: pinctrl@10230000 { 343 compatible = "samsung,exynosautov9-pinctrl"; 344 reg = <0x10230000 0x1000>; 345 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 346 }; 347 348 pinctrl_peric1: pinctrl@10830000 { 349 compatible = "samsung,exynosautov9-pinctrl"; 350 reg = <0x10830000 0x1000>; 351 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 352 }; 353 354 pmu_system_controller: system-controller@10460000 { 355 compatible = "samsung,exynosautov9-pmu", 356 "samsung,exynos7-pmu", "syscon"; 357 reg = <0x10460000 0x10000>; 358 359 reboot: syscon-reboot { 360 compatible = "syscon-reboot"; 361 regmap = <&pmu_system_controller>; 362 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 363 value = <0x2>; 364 mask = <0x2>; 365 }; 366 367 reboot-mode { 368 compatible = "syscon-reboot-mode"; 369 offset = <0x810>; /* SYSIP_DAT0 */ 370 mode-bootloader = <EXYNOSAUTOV9_BOOT_BOOTLOADER>; 371 mode-fastboot = <EXYNOSAUTOV9_BOOT_FASTBOOT>; 372 mode-recovery = <EXYNOSAUTOV9_BOOT_RECOVERY>; 373 }; 374 }; 375 376 syscon_fsys2: syscon@17c20000 { 377 compatible = "samsung,exynosautov9-fsys2-sysreg", 378 "samsung,exynosautov9-sysreg", "syscon"; 379 reg = <0x17c20000 0x1000>; 380 }; 381 382 syscon_peric0: syscon@10220000 { 383 compatible = "samsung,exynosautov9-peric0-sysreg", 384 "samsung,exynosautov9-sysreg", "syscon"; 385 reg = <0x10220000 0x2000>; 386 }; 387 388 syscon_peric1: syscon@10820000 { 389 compatible = "samsung,exynosautov9-peric1-sysreg", 390 "samsung,exynosautov9-sysreg", "syscon"; 391 reg = <0x10820000 0x2000>; 392 }; 393 394 usi_0: usi@103000c0 { 395 compatible = "samsung,exynosautov9-usi", 396 "samsung,exynos850-usi"; 397 reg = <0x103000c0 0x20>; 398 samsung,sysreg = <&syscon_peric0 0x1000>; 399 samsung,mode = <USI_V2_UART>; 400 #address-cells = <1>; 401 #size-cells = <1>; 402 ranges; 403 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, 404 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; 405 clock-names = "pclk", "ipclk"; 406 status = "disabled"; 407 408 serial_0: serial@10300000 { 409 compatible = "samsung,exynosautov9-uart", 410 "samsung,exynos850-uart"; 411 reg = <0x10300000 0xc0>; 412 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&uart0_bus>; 415 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, 416 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; 417 clock-names = "uart", "clk_uart_baud0"; 418 samsung,uart-fifosize = <256>; 419 status = "disabled"; 420 }; 421 422 spi_0: spi@10300000 { 423 compatible = "samsung,exynosautov9-spi"; 424 reg = <0x10300000 0x30>; 425 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&spi0_bus &spi0_cs_func>; 428 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>, 429 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>, 430 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>; 431 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 432 samsung,spi-src-clk = <0>; 433 dmas = <&pdma0 1>, <&pdma0 0>; 434 dma-names = "tx", "rx"; 435 num-cs = <1>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 status = "disabled"; 439 }; 440 441 hsi2c_0: i2c@10300000 { 442 compatible = "samsung,exynosautov9-hsi2c"; 443 reg = <0x10300000 0xc0>; 444 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&hsi2c0_bus>; 447 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>, 448 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>; 449 clock-names = "hsi2c", "hsi2c_pclk"; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 status = "disabled"; 453 }; 454 }; 455 456 usi_i2c_0: usi@103100c0 { 457 compatible = "samsung,exynosautov9-usi", 458 "samsung,exynos850-usi"; 459 reg = <0x103100c0 0x20>; 460 samsung,sysreg = <&syscon_peric0 0x1004>; 461 samsung,mode = <USI_V2_I2C>; 462 #address-cells = <1>; 463 #size-cells = <1>; 464 ranges; 465 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>, 466 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>; 467 clock-names = "pclk", "ipclk"; 468 status = "disabled"; 469 470 hsi2c_1: i2c@10310000 { 471 compatible = "samsung,exynosautov9-hsi2c"; 472 reg = <0x10310000 0xc0>; 473 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&hsi2c1_bus>; 476 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_1>, 477 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_1>; 478 clock-names = "hsi2c", "hsi2c_pclk"; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 status = "disabled"; 482 }; 483 }; 484 485 usi_1: usi@103200c0 { 486 compatible = "samsung,exynosautov9-usi", 487 "samsung,exynos850-usi"; 488 reg = <0x103200c0 0x20>; 489 samsung,sysreg = <&syscon_peric0 0x1008>; 490 samsung,mode = <USI_V2_UART>; 491 #address-cells = <1>; 492 #size-cells = <1>; 493 ranges; 494 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>, 495 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>; 496 clock-names = "pclk", "ipclk"; 497 status = "disabled"; 498 499 serial_1: serial@10320000 { 500 compatible = "samsung,exynosautov9-uart", 501 "samsung,exynos850-uart"; 502 reg = <0x10320000 0xc0>; 503 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&uart1_bus>; 506 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>, 507 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>; 508 clock-names = "uart", "clk_uart_baud0"; 509 samsung,uart-fifosize = <256>; 510 status = "disabled"; 511 }; 512 513 spi_1: spi@10320000 { 514 compatible = "samsung,exynosautov9-spi"; 515 reg = <0x10320000 0x30>; 516 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 517 pinctrl-names = "default"; 518 pinctrl-0 = <&spi1_bus &spi1_cs_func>; 519 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>, 520 <&cmu_peric0 CLK_DOUT_PERIC0_USI01_USI>, 521 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>; 522 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 523 samsung,spi-src-clk = <0>; 524 dmas = <&pdma0 3>, <&pdma0 2>; 525 dma-names = "tx", "rx"; 526 num-cs = <1>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 status = "disabled"; 530 }; 531 532 hsi2c_2: i2c@10320000 { 533 compatible = "samsung,exynosautov9-hsi2c"; 534 reg = <0x10320000 0xc0>; 535 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&hsi2c2_bus>; 538 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_2>, 539 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_2>; 540 clock-names = "hsi2c", "hsi2c_pclk"; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 status = "disabled"; 544 }; 545 }; 546 547 usi_i2c_1: usi@103300c0 { 548 compatible = "samsung,exynosautov9-usi", 549 "samsung,exynos850-usi"; 550 reg = <0x103300c0 0x20>; 551 samsung,sysreg = <&syscon_peric0 0x100c>; 552 samsung,mode = <USI_V2_I2C>; 553 #address-cells = <1>; 554 #size-cells = <1>; 555 ranges; 556 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>, 557 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>; 558 clock-names = "pclk", "ipclk"; 559 status = "disabled"; 560 561 hsi2c_3: i2c@10330000 { 562 compatible = "samsung,exynosautov9-hsi2c"; 563 reg = <0x10330000 0xc0>; 564 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 565 pinctrl-names = "default"; 566 pinctrl-0 = <&hsi2c3_bus>; 567 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_3>, 568 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_3>; 569 clock-names = "hsi2c", "hsi2c_pclk"; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 status = "disabled"; 573 }; 574 }; 575 576 usi_2: usi@103400c0 { 577 compatible = "samsung,exynosautov9-usi", 578 "samsung,exynos850-usi"; 579 reg = <0x103400c0 0x20>; 580 samsung,sysreg = <&syscon_peric0 0x1010>; 581 samsung,mode = <USI_V2_UART>; 582 #address-cells = <1>; 583 #size-cells = <1>; 584 ranges; 585 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>, 586 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>; 587 clock-names = "pclk", "ipclk"; 588 status = "disabled"; 589 590 serial_2: serial@10340000 { 591 compatible = "samsung,exynosautov9-uart", 592 "samsung,exynos850-uart"; 593 reg = <0x10340000 0xc0>; 594 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&uart2_bus>; 597 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>, 598 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>; 599 clock-names = "uart", "clk_uart_baud0"; 600 samsung,uart-fifosize = <64>; 601 status = "disabled"; 602 }; 603 604 spi_2: spi@10340000 { 605 compatible = "samsung,exynosautov9-spi"; 606 reg = <0x10340000 0x30>; 607 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 608 pinctrl-names = "default"; 609 pinctrl-0 = <&spi2_bus &spi2_cs_func>; 610 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>, 611 <&cmu_peric0 CLK_DOUT_PERIC0_USI02_USI>, 612 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>; 613 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 614 samsung,spi-src-clk = <0>; 615 dmas = <&pdma0 5>, <&pdma0 4>; 616 dma-names = "tx", "rx"; 617 num-cs = <1>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 status = "disabled"; 621 }; 622 623 hsi2c_4: i2c@10340000 { 624 compatible = "samsung,exynosautov9-hsi2c"; 625 reg = <0x10340000 0xc0>; 626 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 627 pinctrl-names = "default"; 628 pinctrl-0 = <&hsi2c4_bus>; 629 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_4>, 630 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_4>; 631 clock-names = "hsi2c", "hsi2c_pclk"; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 status = "disabled"; 635 }; 636 }; 637 638 usi_i2c_2: usi@103500c0 { 639 compatible = "samsung,exynosautov9-usi", 640 "samsung,exynos850-usi"; 641 reg = <0x103500c0 0x20>; 642 samsung,sysreg = <&syscon_peric0 0x1014>; 643 samsung,mode = <USI_V2_I2C>; 644 #address-cells = <1>; 645 #size-cells = <1>; 646 ranges; 647 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>, 648 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>; 649 clock-names = "pclk", "ipclk"; 650 status = "disabled"; 651 652 hsi2c_5: i2c@10350000 { 653 compatible = "samsung,exynosautov9-hsi2c"; 654 reg = <0x10350000 0xc0>; 655 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&hsi2c5_bus>; 658 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_5>, 659 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_5>; 660 clock-names = "hsi2c", "hsi2c_pclk"; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 status = "disabled"; 664 }; 665 }; 666 667 usi_3: usi@103600c0 { 668 compatible = "samsung,exynosautov9-usi", 669 "samsung,exynos850-usi"; 670 reg = <0x103600c0 0x20>; 671 samsung,sysreg = <&syscon_peric0 0x1018>; 672 samsung,mode = <USI_V2_UART>; 673 #address-cells = <1>; 674 #size-cells = <1>; 675 ranges; 676 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>, 677 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>; 678 clock-names = "pclk", "ipclk"; 679 status = "disabled"; 680 681 serial_3: serial@10360000 { 682 compatible = "samsung,exynosautov9-uart", 683 "samsung,exynos850-uart"; 684 reg = <0x10360000 0xc0>; 685 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 686 pinctrl-names = "default"; 687 pinctrl-0 = <&uart3_bus>; 688 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>, 689 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>; 690 clock-names = "uart", "clk_uart_baud0"; 691 samsung,uart-fifosize = <64>; 692 status = "disabled"; 693 }; 694 695 spi_3: spi@10360000 { 696 compatible = "samsung,exynosautov9-spi"; 697 reg = <0x10360000 0x30>; 698 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 699 pinctrl-names = "default"; 700 pinctrl-0 = <&spi3_bus &spi3_cs_func>; 701 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>, 702 <&cmu_peric0 CLK_DOUT_PERIC0_USI03_USI>, 703 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>; 704 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 705 samsung,spi-src-clk = <0>; 706 dmas = <&pdma0 7>, <&pdma0 6>; 707 dma-names = "tx", "rx"; 708 num-cs = <1>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 status = "disabled"; 712 }; 713 714 hsi2c_6: i2c@10360000 { 715 compatible = "samsung,exynosautov9-hsi2c"; 716 reg = <0x10360000 0xc0>; 717 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 718 pinctrl-names = "default"; 719 pinctrl-0 = <&hsi2c6_bus>; 720 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_6>, 721 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_6>; 722 clock-names = "hsi2c", "hsi2c_pclk"; 723 #address-cells = <1>; 724 #size-cells = <0>; 725 status = "disabled"; 726 }; 727 }; 728 729 usi_i2c_3: usi@103700c0 { 730 compatible = "samsung,exynosautov9-usi", 731 "samsung,exynos850-usi"; 732 reg = <0x103700c0 0x20>; 733 samsung,sysreg = <&syscon_peric0 0x101c>; 734 samsung,mode = <USI_V2_I2C>; 735 #address-cells = <1>; 736 #size-cells = <1>; 737 ranges; 738 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>, 739 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>; 740 clock-names = "pclk", "ipclk"; 741 status = "disabled"; 742 743 hsi2c_7: i2c@10370000 { 744 compatible = "samsung,exynosautov9-hsi2c"; 745 reg = <0x10370000 0xc0>; 746 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 747 pinctrl-names = "default"; 748 pinctrl-0 = <&hsi2c7_bus>; 749 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_7>, 750 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_7>; 751 clock-names = "hsi2c", "hsi2c_pclk"; 752 #address-cells = <1>; 753 #size-cells = <0>; 754 status = "disabled"; 755 }; 756 }; 757 758 usi_4: usi@103800c0 { 759 compatible = "samsung,exynosautov9-usi", 760 "samsung,exynos850-usi"; 761 reg = <0x103800c0 0x20>; 762 samsung,sysreg = <&syscon_peric0 0x1020>; 763 samsung,mode = <USI_V2_UART>; 764 #address-cells = <1>; 765 #size-cells = <1>; 766 ranges; 767 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>, 768 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>; 769 clock-names = "pclk", "ipclk"; 770 status = "disabled"; 771 772 serial_4: serial@10380000 { 773 compatible = "samsung,exynosautov9-uart", 774 "samsung,exynos850-uart"; 775 reg = <0x10380000 0xc0>; 776 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 777 pinctrl-names = "default"; 778 pinctrl-0 = <&uart4_bus>; 779 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>, 780 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>; 781 clock-names = "uart", "clk_uart_baud0"; 782 samsung,uart-fifosize = <64>; 783 status = "disabled"; 784 }; 785 786 spi_4: spi@10380000 { 787 compatible = "samsung,exynosautov9-spi"; 788 reg = <0x10380000 0x30>; 789 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 790 pinctrl-names = "default"; 791 pinctrl-0 = <&spi4_bus &spi4_cs_func>; 792 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>, 793 <&cmu_peric0 CLK_DOUT_PERIC0_USI04_USI>, 794 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>; 795 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 796 samsung,spi-src-clk = <0>; 797 dmas = <&pdma0 9>, <&pdma0 8>; 798 dma-names = "tx", "rx"; 799 num-cs = <1>; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 status = "disabled"; 803 }; 804 805 hsi2c_8: i2c@10380000 { 806 compatible = "samsung,exynosautov9-hsi2c"; 807 reg = <0x10380000 0xc0>; 808 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 809 pinctrl-names = "default"; 810 pinctrl-0 = <&hsi2c8_bus>; 811 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_8>, 812 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_8>; 813 clock-names = "hsi2c", "hsi2c_pclk"; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 status = "disabled"; 817 }; 818 }; 819 820 usi_i2c_4: usi@103900c0 { 821 compatible = "samsung,exynosautov9-usi", 822 "samsung,exynos850-usi"; 823 reg = <0x103900c0 0x20>; 824 samsung,sysreg = <&syscon_peric0 0x1024>; 825 samsung,mode = <USI_V2_I2C>; 826 #address-cells = <1>; 827 #size-cells = <1>; 828 ranges; 829 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>, 830 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>; 831 clock-names = "pclk", "ipclk"; 832 status = "disabled"; 833 834 hsi2c_9: i2c@10390000 { 835 compatible = "samsung,exynosautov9-hsi2c"; 836 reg = <0x10390000 0xc0>; 837 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 838 pinctrl-names = "default"; 839 pinctrl-0 = <&hsi2c9_bus>; 840 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_9>, 841 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_9>; 842 clock-names = "hsi2c", "hsi2c_pclk"; 843 #address-cells = <1>; 844 #size-cells = <0>; 845 status = "disabled"; 846 }; 847 }; 848 849 usi_5: usi@103a00c0 { 850 compatible = "samsung,exynosautov9-usi", 851 "samsung,exynos850-usi"; 852 reg = <0x103a00c0 0x20>; 853 samsung,sysreg = <&syscon_peric0 0x1028>; 854 samsung,mode = <USI_V2_UART>; 855 #address-cells = <1>; 856 #size-cells = <1>; 857 ranges; 858 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>, 859 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>; 860 clock-names = "pclk", "ipclk"; 861 status = "disabled"; 862 863 serial_5: serial@103a0000 { 864 compatible = "samsung,exynosautov9-uart", 865 "samsung,exynos850-uart"; 866 reg = <0x103a0000 0xc0>; 867 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 868 pinctrl-names = "default"; 869 pinctrl-0 = <&uart5_bus>; 870 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>, 871 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>; 872 clock-names = "uart", "clk_uart_baud0"; 873 samsung,uart-fifosize = <64>; 874 status = "disabled"; 875 }; 876 877 spi_5: spi@103a0000 { 878 compatible = "samsung,exynosautov9-spi"; 879 reg = <0x103a0000 0x30>; 880 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 881 pinctrl-names = "default"; 882 pinctrl-0 = <&spi5_bus &spi5_cs_func>; 883 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>, 884 <&cmu_peric0 CLK_DOUT_PERIC0_USI05_USI>, 885 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>; 886 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 887 samsung,spi-src-clk = <0>; 888 dmas = <&pdma0 11>, <&pdma0 10>; 889 dma-names = "tx", "rx"; 890 num-cs = <1>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 status = "disabled"; 894 }; 895 896 hsi2c_10: i2c@103a0000 { 897 compatible = "samsung,exynosautov9-hsi2c"; 898 reg = <0x103a0000 0xc0>; 899 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 900 pinctrl-names = "default"; 901 pinctrl-0 = <&hsi2c10_bus>; 902 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_10>, 903 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_10>; 904 clock-names = "hsi2c", "hsi2c_pclk"; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 status = "disabled"; 908 }; 909 }; 910 911 usi_i2c_5: usi@103b00c0 { 912 compatible = "samsung,exynosautov9-usi", 913 "samsung,exynos850-usi"; 914 reg = <0x103b00c0 0x20>; 915 samsung,sysreg = <&syscon_peric0 0x102c>; 916 samsung,mode = <USI_V2_I2C>; 917 #address-cells = <1>; 918 #size-cells = <1>; 919 ranges; 920 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>, 921 <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>; 922 clock-names = "pclk", "ipclk"; 923 status = "disabled"; 924 925 hsi2c_11: i2c@103b0000 { 926 compatible = "samsung,exynosautov9-hsi2c"; 927 reg = <0x103b0000 0xc0>; 928 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 929 pinctrl-names = "default"; 930 pinctrl-0 = <&hsi2c11_bus>; 931 clocks = <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_11>, 932 <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_11>; 933 clock-names = "hsi2c", "hsi2c_pclk"; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 status = "disabled"; 937 }; 938 }; 939 940 usi_6: usi@109000c0 { 941 compatible = "samsung,exynosautov9-usi", 942 "samsung,exynos850-usi"; 943 reg = <0x109000c0 0x20>; 944 samsung,sysreg = <&syscon_peric1 0x1000>; 945 samsung,mode = <USI_V2_UART>; 946 #address-cells = <1>; 947 #size-cells = <1>; 948 ranges; 949 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>, 950 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>; 951 clock-names = "pclk", "ipclk"; 952 status = "disabled"; 953 954 serial_6: serial@10900000 { 955 compatible = "samsung,exynosautov9-uart", 956 "samsung,exynos850-uart"; 957 reg = <0x10900000 0xc0>; 958 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&uart6_bus>; 961 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>, 962 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>; 963 clock-names = "uart", "clk_uart_baud0"; 964 samsung,uart-fifosize = <256>; 965 status = "disabled"; 966 }; 967 968 spi_6: spi@10900000 { 969 compatible = "samsung,exynosautov9-spi"; 970 reg = <0x10900000 0x30>; 971 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&spi6_bus &spi6_cs_func>; 974 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>, 975 <&cmu_peric1 CLK_DOUT_PERIC1_USI06_USI>, 976 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>; 977 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 978 samsung,spi-src-clk = <0>; 979 dmas = <&pdma0 13>, <&pdma0 12>; 980 dma-names = "tx", "rx"; 981 num-cs = <1>; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 hsi2c_12: i2c@10900000 { 988 compatible = "samsung,exynosautov9-hsi2c"; 989 reg = <0x10900000 0xc0>; 990 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&hsi2c12_bus>; 993 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_0>, 994 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_0>; 995 clock-names = "hsi2c", "hsi2c_pclk"; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 status = "disabled"; 999 }; 1000 }; 1001 1002 usi_i2c_6: usi@109100c0 { 1003 compatible = "samsung,exynosautov9-usi", 1004 "samsung,exynos850-usi"; 1005 reg = <0x109100c0 0x20>; 1006 samsung,sysreg = <&syscon_peric1 0x1004>; 1007 samsung,mode = <USI_V2_I2C>; 1008 #address-cells = <1>; 1009 #size-cells = <1>; 1010 ranges; 1011 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>, 1012 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>; 1013 clock-names = "pclk", "ipclk"; 1014 status = "disabled"; 1015 1016 hsi2c_13: i2c@10910000 { 1017 compatible = "samsung,exynosautov9-hsi2c"; 1018 reg = <0x10910000 0xc0>; 1019 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&hsi2c13_bus>; 1022 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_1>, 1023 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_1>; 1024 clock-names = "hsi2c", "hsi2c_pclk"; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 status = "disabled"; 1028 }; 1029 }; 1030 1031 usi_7: usi@109200c0 { 1032 compatible = "samsung,exynosautov9-usi", 1033 "samsung,exynos850-usi"; 1034 reg = <0x109200c0 0x20>; 1035 samsung,sysreg = <&syscon_peric1 0x1008>; 1036 samsung,mode = <USI_V2_UART>; 1037 #address-cells = <1>; 1038 #size-cells = <1>; 1039 ranges; 1040 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>, 1041 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>; 1042 clock-names = "pclk", "ipclk"; 1043 status = "disabled"; 1044 1045 serial_7: serial@10920000 { 1046 compatible = "samsung,exynosautov9-uart", 1047 "samsung,exynos850-uart"; 1048 reg = <0x10920000 0xc0>; 1049 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1050 pinctrl-names = "default"; 1051 pinctrl-0 = <&uart7_bus>; 1052 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>, 1053 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>; 1054 clock-names = "uart", "clk_uart_baud0"; 1055 samsung,uart-fifosize = <64>; 1056 status = "disabled"; 1057 }; 1058 1059 spi_7: spi@10920000 { 1060 compatible = "samsung,exynosautov9-spi"; 1061 reg = <0x10920000 0x30>; 1062 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1063 pinctrl-names = "default"; 1064 pinctrl-0 = <&spi7_bus &spi7_cs_func>; 1065 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>, 1066 <&cmu_peric1 CLK_DOUT_PERIC1_USI07_USI>, 1067 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>; 1068 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1069 samsung,spi-src-clk = <0>; 1070 dmas = <&pdma0 15>, <&pdma0 14>; 1071 dma-names = "tx", "rx"; 1072 num-cs = <1>; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 status = "disabled"; 1076 }; 1077 1078 hsi2c_14: i2c@10920000 { 1079 compatible = "samsung,exynosautov9-hsi2c"; 1080 reg = <0x10920000 0xc0>; 1081 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1082 pinctrl-names = "default"; 1083 pinctrl-0 = <&hsi2c14_bus>; 1084 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_2>, 1085 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_2>; 1086 clock-names = "hsi2c", "hsi2c_pclk"; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 status = "disabled"; 1090 }; 1091 }; 1092 1093 usi_i2c_7: usi@109300c0 { 1094 compatible = "samsung,exynosautov9-usi", 1095 "samsung,exynos850-usi"; 1096 reg = <0x109300c0 0x20>; 1097 samsung,sysreg = <&syscon_peric1 0x100c>; 1098 samsung,mode = <USI_V2_I2C>; 1099 #address-cells = <1>; 1100 #size-cells = <1>; 1101 ranges; 1102 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>, 1103 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>; 1104 clock-names = "pclk", "ipclk"; 1105 status = "disabled"; 1106 1107 hsi2c_15: i2c@10930000 { 1108 compatible = "samsung,exynosautov9-hsi2c"; 1109 reg = <0x10930000 0xc0>; 1110 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1111 pinctrl-names = "default"; 1112 pinctrl-0 = <&hsi2c15_bus>; 1113 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_3>, 1114 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_3>; 1115 clock-names = "hsi2c", "hsi2c_pclk"; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 status = "disabled"; 1119 }; 1120 }; 1121 1122 usi_8: usi@109400c0 { 1123 compatible = "samsung,exynosautov9-usi", 1124 "samsung,exynos850-usi"; 1125 reg = <0x109400c0 0x20>; 1126 samsung,sysreg = <&syscon_peric1 0x1010>; 1127 samsung,mode = <USI_V2_UART>; 1128 #address-cells = <1>; 1129 #size-cells = <1>; 1130 ranges; 1131 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>, 1132 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>; 1133 clock-names = "pclk", "ipclk"; 1134 status = "disabled"; 1135 1136 serial_8: serial@10940000 { 1137 compatible = "samsung,exynosautov9-uart", 1138 "samsung,exynos850-uart"; 1139 reg = <0x10940000 0xc0>; 1140 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&uart8_bus>; 1143 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>, 1144 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>; 1145 clock-names = "uart", "clk_uart_baud0"; 1146 samsung,uart-fifosize = <64>; 1147 status = "disabled"; 1148 }; 1149 1150 spi_8: spi@10940000 { 1151 compatible = "samsung,exynosautov9-spi"; 1152 reg = <0x10940000 0x30>; 1153 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1154 pinctrl-names = "default"; 1155 pinctrl-0 = <&spi8_bus &spi8_cs_func>; 1156 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>, 1157 <&cmu_peric1 CLK_DOUT_PERIC1_USI08_USI>, 1158 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>; 1159 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1160 samsung,spi-src-clk = <0>; 1161 dmas = <&pdma0 17>, <&pdma0 16>; 1162 dma-names = "tx", "rx"; 1163 num-cs = <1>; 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 status = "disabled"; 1167 }; 1168 1169 hsi2c_16: i2c@10940000 { 1170 compatible = "samsung,exynosautov9-hsi2c"; 1171 reg = <0x10940000 0xc0>; 1172 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>; 1173 pinctrl-names = "default"; 1174 pinctrl-0 = <&hsi2c16_bus>; 1175 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_4>, 1176 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_4>; 1177 clock-names = "hsi2c", "hsi2c_pclk"; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 status = "disabled"; 1181 }; 1182 }; 1183 1184 usi_i2c_8: usi@109500c0 { 1185 compatible = "samsung,exynosautov9-usi", 1186 "samsung,exynos850-usi"; 1187 reg = <0x109500c0 0x20>; 1188 samsung,sysreg = <&syscon_peric1 0x1014>; 1189 samsung,mode = <USI_V2_I2C>; 1190 #address-cells = <1>; 1191 #size-cells = <1>; 1192 ranges; 1193 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>, 1194 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>; 1195 clock-names = "pclk", "ipclk"; 1196 status = "disabled"; 1197 1198 hsi2c_17: i2c@10950000 { 1199 compatible = "samsung,exynosautov9-hsi2c"; 1200 reg = <0x10950000 0xc0>; 1201 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1202 pinctrl-names = "default"; 1203 pinctrl-0 = <&hsi2c17_bus>; 1204 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_5>, 1205 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_5>; 1206 clock-names = "hsi2c", "hsi2c_pclk"; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 status = "disabled"; 1210 }; 1211 }; 1212 1213 usi_9: usi@109600c0 { 1214 compatible = "samsung,exynosautov9-usi", 1215 "samsung,exynos850-usi"; 1216 reg = <0x109600c0 0x20>; 1217 samsung,sysreg = <&syscon_peric1 0x1018>; 1218 samsung,mode = <USI_V2_UART>; 1219 #address-cells = <1>; 1220 #size-cells = <1>; 1221 ranges; 1222 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>, 1223 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>; 1224 clock-names = "pclk", "ipclk"; 1225 status = "disabled"; 1226 1227 serial_9: serial@10960000 { 1228 compatible = "samsung,exynosautov9-uart", 1229 "samsung,exynos850-uart"; 1230 reg = <0x10960000 0xc0>; 1231 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&uart9_bus>; 1234 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>, 1235 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>; 1236 clock-names = "uart", "clk_uart_baud0"; 1237 samsung,uart-fifosize = <64>; 1238 status = "disabled"; 1239 }; 1240 1241 spi_9: spi@10960000 { 1242 compatible = "samsung,exynosautov9-spi"; 1243 reg = <0x10960000 0x30>; 1244 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1245 pinctrl-names = "default"; 1246 pinctrl-0 = <&spi9_bus &spi9_cs_func>; 1247 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>, 1248 <&cmu_peric1 CLK_DOUT_PERIC1_USI09_USI>, 1249 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>; 1250 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1251 samsung,spi-src-clk = <0>; 1252 dmas = <&pdma0 19>, <&pdma0 18>; 1253 dma-names = "tx", "rx"; 1254 num-cs = <1>; 1255 #address-cells = <1>; 1256 #size-cells = <0>; 1257 status = "disabled"; 1258 }; 1259 1260 hsi2c_18: i2c@10960000 { 1261 compatible = "samsung,exynosautov9-hsi2c"; 1262 reg = <0x10960000 0xc0>; 1263 interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&hsi2c18_bus>; 1266 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_6>, 1267 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_6>; 1268 clock-names = "hsi2c", "hsi2c_pclk"; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 }; 1274 1275 usi_i2c_9: usi@109700c0 { 1276 compatible = "samsung,exynosautov9-usi", 1277 "samsung,exynos850-usi"; 1278 reg = <0x109700c0 0x20>; 1279 samsung,sysreg = <&syscon_peric1 0x101c>; 1280 samsung,mode = <USI_V2_I2C>; 1281 #address-cells = <1>; 1282 #size-cells = <1>; 1283 ranges; 1284 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>, 1285 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>; 1286 clock-names = "pclk", "ipclk"; 1287 status = "disabled"; 1288 1289 hsi2c_19: i2c@10970000 { 1290 compatible = "samsung,exynosautov9-hsi2c"; 1291 reg = <0x10970000 0xc0>; 1292 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&hsi2c19_bus>; 1295 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_7>, 1296 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_7>; 1297 clock-names = "hsi2c", "hsi2c_pclk"; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 status = "disabled"; 1301 }; 1302 }; 1303 1304 usi_10: usi@109800c0 { 1305 compatible = "samsung,exynosautov9-usi", 1306 "samsung,exynos850-usi"; 1307 reg = <0x109800c0 0x20>; 1308 samsung,sysreg = <&syscon_peric1 0x1020>; 1309 samsung,mode = <USI_V2_UART>; 1310 #address-cells = <1>; 1311 #size-cells = <1>; 1312 ranges; 1313 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>, 1314 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>; 1315 clock-names = "pclk", "ipclk"; 1316 status = "disabled"; 1317 1318 serial_10: serial@10980000 { 1319 compatible = "samsung,exynosautov9-uart", 1320 "samsung,exynos850-uart"; 1321 reg = <0x10980000 0xc0>; 1322 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1323 pinctrl-names = "default"; 1324 pinctrl-0 = <&uart10_bus>; 1325 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>, 1326 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>; 1327 clock-names = "uart", "clk_uart_baud0"; 1328 samsung,uart-fifosize = <64>; 1329 status = "disabled"; 1330 }; 1331 1332 spi_10: spi@10980000 { 1333 compatible = "samsung,exynosautov9-spi"; 1334 reg = <0x10980000 0x30>; 1335 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&spi10_bus &spi10_cs_func>; 1338 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>, 1339 <&cmu_peric1 CLK_DOUT_PERIC1_USI10_USI>, 1340 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>; 1341 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1342 samsung,spi-src-clk = <0>; 1343 dmas = <&pdma0 21>, <&pdma0 20>; 1344 dma-names = "tx", "rx"; 1345 num-cs = <1>; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 status = "disabled"; 1349 }; 1350 1351 hsi2c_20: i2c@10980000 { 1352 compatible = "samsung,exynosautov9-hsi2c"; 1353 reg = <0x10980000 0xc0>; 1354 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>; 1355 pinctrl-names = "default"; 1356 pinctrl-0 = <&hsi2c20_bus>; 1357 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_8>, 1358 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_8>; 1359 clock-names = "hsi2c", "hsi2c_pclk"; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 status = "disabled"; 1363 }; 1364 }; 1365 1366 usi_i2c_10: usi@109900c0 { 1367 compatible = "samsung,exynosautov9-usi", 1368 "samsung,exynos850-usi"; 1369 reg = <0x109900c0 0x20>; 1370 samsung,sysreg = <&syscon_peric1 0x1024>; 1371 samsung,mode = <USI_V2_I2C>; 1372 #address-cells = <1>; 1373 #size-cells = <1>; 1374 ranges; 1375 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>, 1376 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>; 1377 clock-names = "pclk", "ipclk"; 1378 status = "disabled"; 1379 1380 hsi2c_21: i2c@10990000 { 1381 compatible = "samsung,exynosautov9-hsi2c"; 1382 reg = <0x10990000 0xc0>; 1383 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; 1384 pinctrl-names = "default"; 1385 pinctrl-0 = <&hsi2c21_bus>; 1386 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_9>, 1387 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_9>; 1388 clock-names = "hsi2c", "hsi2c_pclk"; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 status = "disabled"; 1392 }; 1393 }; 1394 1395 usi_11: usi@109a00c0 { 1396 compatible = "samsung,exynosautov9-usi", 1397 "samsung,exynos850-usi"; 1398 reg = <0x109a00c0 0x20>; 1399 samsung,sysreg = <&syscon_peric1 0x1028>; 1400 samsung,mode = <USI_V2_UART>; 1401 #address-cells = <1>; 1402 #size-cells = <1>; 1403 ranges; 1404 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>, 1405 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>; 1406 clock-names = "pclk", "ipclk"; 1407 status = "disabled"; 1408 1409 serial_11: serial@109a0000 { 1410 compatible = "samsung,exynosautov9-uart", 1411 "samsung,exynos850-uart"; 1412 reg = <0x109a0000 0xc0>; 1413 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1414 pinctrl-names = "default"; 1415 pinctrl-0 = <&uart11_bus>; 1416 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>, 1417 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>; 1418 clock-names = "uart", "clk_uart_baud0"; 1419 samsung,uart-fifosize = <64>; 1420 status = "disabled"; 1421 }; 1422 1423 spi_11: spi@109a0000 { 1424 compatible = "samsung,exynosautov9-spi"; 1425 reg = <0x109a0000 0x30>; 1426 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1427 pinctrl-names = "default"; 1428 pinctrl-0 = <&spi11_bus &spi11_cs_func>; 1429 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>, 1430 <&cmu_peric1 CLK_DOUT_PERIC1_USI11_USI>, 1431 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>; 1432 clock-names = "spi", "spi_busclk0", "spi_ioclk"; 1433 samsung,spi-src-clk = <0>; 1434 num-cs = <1>; 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 status = "disabled"; 1438 }; 1439 1440 hsi2c_22: i2c@109a0000 { 1441 compatible = "samsung,exynosautov9-hsi2c"; 1442 reg = <0x109a0000 0xc0>; 1443 pinctrl-names = "default"; 1444 pinctrl-0 = <&hsi2c22_bus>; 1445 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1446 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_10>, 1447 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_10>; 1448 clock-names = "hsi2c", "hsi2c_pclk"; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 status = "disabled"; 1452 }; 1453 }; 1454 1455 usi_i2c_11: usi@109b00c0 { 1456 compatible = "samsung,exynosautov9-usi", 1457 "samsung,exynos850-usi"; 1458 reg = <0x109b00c0 0x20>; 1459 samsung,sysreg = <&syscon_peric1 0x102c>; 1460 samsung,mode = <USI_V2_I2C>; 1461 #address-cells = <1>; 1462 #size-cells = <1>; 1463 ranges; 1464 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>, 1465 <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>; 1466 clock-names = "pclk", "ipclk"; 1467 status = "disabled"; 1468 1469 hsi2c_23: i2c@109b0000 { 1470 compatible = "samsung,exynosautov9-hsi2c"; 1471 reg = <0x109b0000 0xc0>; 1472 interrupts = <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 1473 pinctrl-names = "default"; 1474 pinctrl-0 = <&hsi2c23_bus>; 1475 clocks = <&cmu_peric1 CLK_GOUT_PERIC1_IPCLK_11>, 1476 <&cmu_peric1 CLK_GOUT_PERIC1_PCLK_11>; 1477 clock-names = "hsi2c", "hsi2c_pclk"; 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 status = "disabled"; 1481 }; 1482 }; 1483 1484 ufs_0_phy: phy@17e04000 { 1485 compatible = "samsung,exynosautov9-ufs-phy"; 1486 reg = <0x17e04000 0xc00>; 1487 reg-names = "phy-pma"; 1488 samsung,pmu-syscon = <&pmu_system_controller>; 1489 #phy-cells = <0>; 1490 clocks = <&xtcxo>; 1491 clock-names = "ref_clk"; 1492 status = "disabled"; 1493 }; 1494 1495 ufs_0: ufs@17e00000 { 1496 compatible = "samsung,exynosautov9-ufs"; 1497 1498 reg = <0x17e00000 0x100>, 1499 <0x17e01100 0x410>, 1500 <0x17e80000 0x8000>, 1501 <0x17dc0000 0x2200>; 1502 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1503 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1504 clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>, 1505 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO>; 1506 clock-names = "core_clk", "sclk_unipro_main"; 1507 freq-table-hz = <0 0>, <0 0>; 1508 pinctrl-names = "default"; 1509 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 1510 phys = <&ufs_0_phy>; 1511 phy-names = "ufs-phy"; 1512 samsung,sysreg = <&syscon_fsys2 0x710>; 1513 status = "disabled"; 1514 }; 1515 1516 ufs_1_phy: phy@17f04000 { 1517 compatible = "samsung,exynosautov9-ufs-phy"; 1518 reg = <0x17f04000 0xc00>; 1519 reg-names = "phy-pma"; 1520 samsung,pmu-syscon = <&pmu_system_controller 0x72c>; 1521 #phy-cells = <0>; 1522 clocks = <&xtcxo>; 1523 clock-names = "ref_clk"; 1524 status = "disabled"; 1525 }; 1526 1527 ufs_1: ufs@17f00000 { 1528 compatible = "samsung,exynosautov9-ufs"; 1529 1530 reg = <0x17f00000 0x100>, 1531 <0x17f01100 0x410>, 1532 <0x17f80000 0x8000>, 1533 <0x17de0000 0x2200>; 1534 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 1535 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1536 clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_ACLK>, 1537 <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO>; 1538 clock-names = "core_clk", "sclk_unipro_main"; 1539 freq-table-hz = <0 0>, <0 0>; 1540 pinctrl-names = "default"; 1541 pinctrl-0 = <&ufs_rst_n_1 &ufs_refclk_out_1>; 1542 phys = <&ufs_1_phy>; 1543 phy-names = "ufs-phy"; 1544 samsung,sysreg = <&syscon_fsys2 0x714>; 1545 status = "disabled"; 1546 }; 1547 1548 watchdog_cl0: watchdog@10050000 { 1549 compatible = "samsung,exynosautov9-wdt"; 1550 reg = <0x10050000 0x100>; 1551 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 1552 clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER0>, <&xtcxo>; 1553 clock-names = "watchdog", "watchdog_src"; 1554 samsung,syscon-phandle = <&pmu_system_controller>; 1555 samsung,cluster-index = <0>; 1556 }; 1557 1558 watchdog_cl1: watchdog@10060000 { 1559 compatible = "samsung,exynosautov9-wdt"; 1560 reg = <0x10060000 0x100>; 1561 interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 1562 clocks = <&cmu_peris CLK_GOUT_WDT_CLUSTER1>, <&xtcxo>; 1563 clock-names = "watchdog", "watchdog_src"; 1564 samsung,syscon-phandle = <&pmu_system_controller>; 1565 samsung,cluster-index = <1>; 1566 }; 1567 1568 pwm: pwm@103f0000 { 1569 compatible = "samsung,exynosautov9-pwm", 1570 "samsung,exynos4210-pwm"; 1571 reg = <0x103f0000 0x100>; 1572 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 1573 #pwm-cells = <3>; 1574 clocks = <&xtcxo>; 1575 clock-names = "timers"; 1576 status = "disabled"; 1577 }; 1578 }; 1579}; 1580 1581#include "exynosautov9-pinctrl.dtsi" 1582