1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos850 SoC device tree source 4 * 5 * Copyright (C) 2018 Samsung Electronics Co., Ltd. 6 * Copyright (C) 2021 Linaro Ltd. 7 * 8 * Samsung Exynos850 SoC device nodes are listed in this file. 9 * Exynos850 based board files can include this file and provide 10 * values for board specific bindings. 11 */ 12 13#include <dt-bindings/clock/exynos850.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/samsung,exynos-usi.h> 16 17/ { 18 /* Also known under engineering name Exynos3830 */ 19 compatible = "samsung,exynos850"; 20 #address-cells = <2>; 21 #size-cells = <1>; 22 23 interrupt-parent = <&gic>; 24 25 aliases { 26 pinctrl0 = &pinctrl_alive; 27 pinctrl1 = &pinctrl_cmgp; 28 pinctrl2 = &pinctrl_aud; 29 pinctrl3 = &pinctrl_hsi; 30 pinctrl4 = &pinctrl_core; 31 pinctrl5 = &pinctrl_peri; 32 mmc0 = &mmc_0; 33 serial0 = &serial_0; 34 serial1 = &serial_1; 35 serial2 = &serial_2; 36 i2c0 = &i2c_0; 37 i2c1 = &i2c_1; 38 i2c2 = &i2c_2; 39 i2c3 = &i2c_3; 40 i2c4 = &i2c_4; 41 i2c5 = &i2c_5; 42 i2c6 = &i2c_6; 43 i2c7 = &hsi2c_0; 44 i2c8 = &hsi2c_1; 45 i2c9 = &hsi2c_2; 46 i2c10 = &hsi2c_3; 47 i2c11 = &hsi2c_4; 48 }; 49 50 arm-pmu { 51 compatible = "arm,cortex-a55-pmu"; 52 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 60 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 61 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 62 }; 63 64 /* Main system clock (XTCXO); external, must be 26 MHz */ 65 oscclk: clock-oscclk { 66 compatible = "fixed-clock"; 67 clock-output-names = "oscclk"; 68 #clock-cells = <0>; 69 }; 70 71 cpus { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 75 cpu-map { 76 cluster0 { 77 core0 { 78 cpu = <&cpu0>; 79 }; 80 core1 { 81 cpu = <&cpu1>; 82 }; 83 core2 { 84 cpu = <&cpu2>; 85 }; 86 core3 { 87 cpu = <&cpu3>; 88 }; 89 }; 90 91 cluster1 { 92 core0 { 93 cpu = <&cpu4>; 94 }; 95 core1 { 96 cpu = <&cpu5>; 97 }; 98 core2 { 99 cpu = <&cpu6>; 100 }; 101 core3 { 102 cpu = <&cpu7>; 103 }; 104 }; 105 }; 106 107 cpu0: cpu@0 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a55"; 110 reg = <0x0>; 111 enable-method = "psci"; 112 }; 113 cpu1: cpu@1 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a55"; 116 reg = <0x1>; 117 enable-method = "psci"; 118 }; 119 cpu2: cpu@2 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a55"; 122 reg = <0x2>; 123 enable-method = "psci"; 124 }; 125 cpu3: cpu@3 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a55"; 128 reg = <0x3>; 129 enable-method = "psci"; 130 }; 131 cpu4: cpu@100 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a55"; 134 reg = <0x100>; 135 enable-method = "psci"; 136 }; 137 cpu5: cpu@101 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a55"; 140 reg = <0x101>; 141 enable-method = "psci"; 142 }; 143 cpu6: cpu@102 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a55"; 146 reg = <0x102>; 147 enable-method = "psci"; 148 }; 149 cpu7: cpu@103 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a55"; 152 reg = <0x103>; 153 enable-method = "psci"; 154 }; 155 }; 156 157 psci { 158 compatible = "arm,psci-1.0"; 159 method = "smc"; 160 }; 161 162 timer { 163 compatible = "arm,armv8-timer"; 164 /* Hypervisor Virtual Timer interrupt is not wired to GIC */ 165 interrupts = 166 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 170 }; 171 172 soc: soc@0 { 173 compatible = "simple-bus"; 174 #address-cells = <1>; 175 #size-cells = <1>; 176 ranges = <0x0 0x0 0x0 0x20000000>; 177 178 chipid@10000000 { 179 compatible = "samsung,exynos850-chipid"; 180 reg = <0x10000000 0x100>; 181 }; 182 183 timer@10040000 { 184 compatible = "samsung,exynos4210-mct"; 185 reg = <0x10040000 0x800>; 186 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>; 199 clock-names = "fin_pll", "mct"; 200 }; 201 202 gic: interrupt-controller@12a01000 { 203 compatible = "arm,gic-400"; 204 #interrupt-cells = <3>; 205 #address-cells = <0>; 206 reg = <0x12a01000 0x1000>, 207 <0x12a02000 0x2000>, 208 <0x12a04000 0x2000>, 209 <0x12a06000 0x2000>; 210 interrupt-controller; 211 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 212 IRQ_TYPE_LEVEL_HIGH)>; 213 }; 214 215 pmu_system_controller: system-controller@11860000 { 216 compatible = "samsung,exynos850-pmu", "syscon"; 217 reg = <0x11860000 0x10000>; 218 clocks = <&cmu_apm CLK_GOUT_PMU_ALIVE_PCLK>; 219 220 reboot: syscon-reboot { 221 compatible = "syscon-reboot"; 222 regmap = <&pmu_system_controller>; 223 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 224 mask = <0x2>; /* SWRESET_SYSTEM */ 225 value = <0x2>; /* reset value */ 226 }; 227 }; 228 229 watchdog_cl0: watchdog@10050000 { 230 compatible = "samsung,exynos850-wdt"; 231 reg = <0x10050000 0x100>; 232 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; 234 clock-names = "watchdog", "watchdog_src"; 235 samsung,syscon-phandle = <&pmu_system_controller>; 236 samsung,cluster-index = <0>; 237 status = "disabled"; 238 }; 239 240 watchdog_cl1: watchdog@10060000 { 241 compatible = "samsung,exynos850-wdt"; 242 reg = <0x10060000 0x100>; 243 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; 245 clock-names = "watchdog", "watchdog_src"; 246 samsung,syscon-phandle = <&pmu_system_controller>; 247 samsung,cluster-index = <1>; 248 status = "disabled"; 249 }; 250 251 cmu_peri: clock-controller@10030000 { 252 compatible = "samsung,exynos850-cmu-peri"; 253 reg = <0x10030000 0x8000>; 254 #clock-cells = <1>; 255 256 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, 257 <&cmu_top CLK_DOUT_PERI_UART>, 258 <&cmu_top CLK_DOUT_PERI_IP>; 259 clock-names = "oscclk", "dout_peri_bus", 260 "dout_peri_uart", "dout_peri_ip"; 261 }; 262 263 cmu_apm: clock-controller@11800000 { 264 compatible = "samsung,exynos850-cmu-apm"; 265 reg = <0x11800000 0x8000>; 266 #clock-cells = <1>; 267 268 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>; 269 clock-names = "oscclk", "dout_clkcmu_apm_bus"; 270 }; 271 272 cmu_cmgp: clock-controller@11c00000 { 273 compatible = "samsung,exynos850-cmu-cmgp"; 274 reg = <0x11c00000 0x8000>; 275 #clock-cells = <1>; 276 277 clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>; 278 clock-names = "oscclk", "gout_clkcmu_cmgp_bus"; 279 }; 280 281 cmu_core: clock-controller@12000000 { 282 compatible = "samsung,exynos850-cmu-core"; 283 reg = <0x12000000 0x8000>; 284 #clock-cells = <1>; 285 286 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>, 287 <&cmu_top CLK_DOUT_CORE_CCI>, 288 <&cmu_top CLK_DOUT_CORE_MMC_EMBD>, 289 <&cmu_top CLK_DOUT_CORE_SSS>; 290 clock-names = "oscclk", "dout_core_bus", 291 "dout_core_cci", "dout_core_mmc_embd", 292 "dout_core_sss"; 293 }; 294 295 cmu_top: clock-controller@120e0000 { 296 compatible = "samsung,exynos850-cmu-top"; 297 reg = <0x120e0000 0x8000>; 298 #clock-cells = <1>; 299 300 clocks = <&oscclk>; 301 clock-names = "oscclk"; 302 }; 303 304 cmu_dpu: clock-controller@13000000 { 305 compatible = "samsung,exynos850-cmu-dpu"; 306 reg = <0x13000000 0x8000>; 307 #clock-cells = <1>; 308 309 clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>; 310 clock-names = "oscclk", "dout_dpu"; 311 }; 312 313 cmu_hsi: clock-controller@13400000 { 314 compatible = "samsung,exynos850-cmu-hsi"; 315 reg = <0x13400000 0x8000>; 316 #clock-cells = <1>; 317 318 clocks = <&oscclk>, 319 <&cmu_top CLK_DOUT_HSI_BUS>, 320 <&cmu_top CLK_DOUT_HSI_MMC_CARD>, 321 <&cmu_top CLK_DOUT_HSI_USB20DRD>; 322 clock-names = "oscclk", "dout_hsi_bus", 323 "dout_hsi_mmc_card", "dout_hsi_usb20drd"; 324 }; 325 326 pinctrl_alive: pinctrl@11850000 { 327 compatible = "samsung,exynos850-pinctrl"; 328 reg = <0x11850000 0x1000>; 329 330 wakeup-interrupt-controller { 331 compatible = "samsung,exynos850-wakeup-eint"; 332 }; 333 }; 334 335 pinctrl_cmgp: pinctrl@11c30000 { 336 compatible = "samsung,exynos850-pinctrl"; 337 reg = <0x11c30000 0x1000>; 338 339 wakeup-interrupt-controller { 340 compatible = "samsung,exynos850-wakeup-eint"; 341 }; 342 }; 343 344 pinctrl_core: pinctrl@12070000 { 345 compatible = "samsung,exynos850-pinctrl"; 346 reg = <0x12070000 0x1000>; 347 interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>; 348 }; 349 350 pinctrl_hsi: pinctrl@13430000 { 351 compatible = "samsung,exynos850-pinctrl"; 352 reg = <0x13430000 0x1000>; 353 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 354 }; 355 356 pinctrl_peri: pinctrl@139b0000 { 357 compatible = "samsung,exynos850-pinctrl"; 358 reg = <0x139b0000 0x1000>; 359 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 360 }; 361 362 pinctrl_aud: pinctrl@14a60000 { 363 compatible = "samsung,exynos850-pinctrl"; 364 reg = <0x14a60000 0x1000>; 365 }; 366 367 rtc: rtc@11a30000 { 368 compatible = "samsung,s3c6410-rtc"; 369 reg = <0x11a30000 0x100>; 370 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>; 373 clock-names = "rtc"; 374 status = "disabled"; 375 }; 376 377 mmc_0: mmc@12100000 { 378 compatible = "samsung,exynos7-dw-mshc-smu"; 379 reg = <0x12100000 0x2000>; 380 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>, 384 <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; 385 clock-names = "biu", "ciu"; 386 fifo-depth = <0x40>; 387 status = "disabled"; 388 }; 389 390 i2c_0: i2c@13830000 { 391 compatible = "samsung,s3c2440-i2c"; 392 reg = <0x13830000 0x100>; 393 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 pinctrl-names = "default"; 397 pinctrl-0 = <&i2c0_pins>; 398 clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; 399 clock-names = "i2c"; 400 status = "disabled"; 401 }; 402 403 i2c_1: i2c@13840000 { 404 compatible = "samsung,s3c2440-i2c"; 405 reg = <0x13840000 0x100>; 406 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&i2c1_pins>; 411 clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; 412 clock-names = "i2c"; 413 status = "disabled"; 414 }; 415 416 i2c_2: i2c@13850000 { 417 compatible = "samsung,s3c2440-i2c"; 418 reg = <0x13850000 0x100>; 419 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 pinctrl-names = "default"; 423 pinctrl-0 = <&i2c2_pins>; 424 clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; 425 clock-names = "i2c"; 426 status = "disabled"; 427 }; 428 429 i2c_3: i2c@13860000 { 430 compatible = "samsung,s3c2440-i2c"; 431 reg = <0x13860000 0x100>; 432 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&i2c3_pins>; 437 clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; 438 clock-names = "i2c"; 439 status = "disabled"; 440 }; 441 442 i2c_4: i2c@13870000 { 443 compatible = "samsung,s3c2440-i2c"; 444 reg = <0x13870000 0x100>; 445 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&i2c4_pins>; 450 clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; 451 clock-names = "i2c"; 452 status = "disabled"; 453 }; 454 455 /* I2C_5 (also called CAM_PMIC_I2C in TRM) */ 456 i2c_5: i2c@13880000 { 457 compatible = "samsung,s3c2440-i2c"; 458 reg = <0x13880000 0x100>; 459 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&i2c5_pins>; 464 clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; 465 clock-names = "i2c"; 466 status = "disabled"; 467 }; 468 469 /* I2C_6 (also called MOTOR_I2C in TRM) */ 470 i2c_6: i2c@13890000 { 471 compatible = "samsung,s3c2440-i2c"; 472 reg = <0x13890000 0x100>; 473 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&i2c6_pins>; 478 clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; 479 clock-names = "i2c"; 480 status = "disabled"; 481 }; 482 483 sysreg_peri: syscon@10020000 { 484 compatible = "samsung,exynos850-sysreg", "syscon"; 485 reg = <0x10020000 0x10000>; 486 clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; 487 }; 488 489 sysreg_cmgp: syscon@11c20000 { 490 compatible = "samsung,exynos850-sysreg", "syscon"; 491 reg = <0x11c20000 0x10000>; 492 clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; 493 }; 494 495 usi_uart: usi@138200c0 { 496 compatible = "samsung,exynos850-usi"; 497 reg = <0x138200c0 0x20>; 498 samsung,sysreg = <&sysreg_peri 0x1010>; 499 samsung,mode = <USI_V2_UART>; 500 #address-cells = <1>; 501 #size-cells = <1>; 502 ranges; 503 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 504 <&cmu_peri CLK_GOUT_UART_IPCLK>; 505 clock-names = "pclk", "ipclk"; 506 status = "disabled"; 507 508 serial_0: serial@13820000 { 509 compatible = "samsung,exynos850-uart"; 510 reg = <0x13820000 0xc0>; 511 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&uart0_pins>; 514 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 515 <&cmu_peri CLK_GOUT_UART_IPCLK>; 516 clock-names = "uart", "clk_uart_baud0"; 517 status = "disabled"; 518 }; 519 }; 520 521 usi_hsi2c_0: usi@138a00c0 { 522 compatible = "samsung,exynos850-usi"; 523 reg = <0x138a00c0 0x20>; 524 samsung,sysreg = <&sysreg_peri 0x1020>; 525 samsung,mode = <USI_V2_I2C>; 526 #address-cells = <1>; 527 #size-cells = <1>; 528 ranges; 529 clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, 530 <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; 531 clock-names = "pclk", "ipclk"; 532 status = "disabled"; 533 534 hsi2c_0: i2c@138a0000 { 535 compatible = "samsung,exynosautov9-hsi2c"; 536 reg = <0x138a0000 0xc0>; 537 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&hsi2c0_pins>; 542 clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, 543 <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; 544 clock-names = "hsi2c", "hsi2c_pclk"; 545 status = "disabled"; 546 }; 547 }; 548 549 usi_hsi2c_1: usi@138b00c0 { 550 compatible = "samsung,exynos850-usi"; 551 reg = <0x138b00c0 0x20>; 552 samsung,sysreg = <&sysreg_peri 0x1030>; 553 samsung,mode = <USI_V2_I2C>; 554 #address-cells = <1>; 555 #size-cells = <1>; 556 ranges; 557 clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, 558 <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; 559 clock-names = "pclk", "ipclk"; 560 status = "disabled"; 561 562 hsi2c_1: i2c@138b0000 { 563 compatible = "samsung,exynosautov9-hsi2c"; 564 reg = <0x138b0000 0xc0>; 565 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&hsi2c1_pins>; 570 clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, 571 <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; 572 clock-names = "hsi2c", "hsi2c_pclk"; 573 status = "disabled"; 574 }; 575 }; 576 577 usi_hsi2c_2: usi@138c00c0 { 578 compatible = "samsung,exynos850-usi"; 579 reg = <0x138c00c0 0x20>; 580 samsung,sysreg = <&sysreg_peri 0x1040>; 581 samsung,mode = <USI_V2_I2C>; 582 #address-cells = <1>; 583 #size-cells = <1>; 584 ranges; 585 clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, 586 <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; 587 clock-names = "pclk", "ipclk"; 588 status = "disabled"; 589 590 hsi2c_2: i2c@138c0000 { 591 compatible = "samsung,exynosautov9-hsi2c"; 592 reg = <0x138c0000 0xc0>; 593 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&hsi2c2_pins>; 598 clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, 599 <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; 600 clock-names = "hsi2c", "hsi2c_pclk"; 601 status = "disabled"; 602 }; 603 }; 604 605 usi_spi_0: usi@139400c0 { 606 compatible = "samsung,exynos850-usi"; 607 reg = <0x139400c0 0x20>; 608 samsung,sysreg = <&sysreg_peri 0x1050>; 609 samsung,mode = <USI_V2_SPI>; 610 #address-cells = <1>; 611 #size-cells = <1>; 612 ranges; 613 clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, 614 <&cmu_peri CLK_GOUT_SPI0_IPCLK>; 615 clock-names = "pclk", "ipclk"; 616 status = "disabled"; 617 }; 618 619 usi_cmgp0: usi@11d000c0 { 620 compatible = "samsung,exynos850-usi"; 621 reg = <0x11d000c0 0x20>; 622 samsung,sysreg = <&sysreg_cmgp 0x2000>; 623 samsung,mode = <USI_V2_I2C>; 624 #address-cells = <1>; 625 #size-cells = <1>; 626 ranges; 627 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 628 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 629 clock-names = "pclk", "ipclk"; 630 status = "disabled"; 631 632 hsi2c_3: i2c@11d00000 { 633 compatible = "samsung,exynosautov9-hsi2c"; 634 reg = <0x11d00000 0xc0>; 635 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 pinctrl-names = "default"; 639 pinctrl-0 = <&hsi2c3_pins>; 640 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, 641 <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; 642 clock-names = "hsi2c", "hsi2c_pclk"; 643 status = "disabled"; 644 }; 645 646 serial_1: serial@11d00000 { 647 compatible = "samsung,exynos850-uart"; 648 reg = <0x11d00000 0xc0>; 649 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 650 pinctrl-names = "default"; 651 pinctrl-0 = <&uart1_single_pins>; 652 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 653 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 654 clock-names = "uart", "clk_uart_baud0"; 655 status = "disabled"; 656 }; 657 }; 658 659 usi_cmgp1: usi@11d200c0 { 660 compatible = "samsung,exynos850-usi"; 661 reg = <0x11d200c0 0x20>; 662 samsung,sysreg = <&sysreg_cmgp 0x2010>; 663 samsung,mode = <USI_V2_I2C>; 664 #address-cells = <1>; 665 #size-cells = <1>; 666 ranges; 667 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 668 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 669 clock-names = "pclk", "ipclk"; 670 status = "disabled"; 671 672 hsi2c_4: i2c@11d20000 { 673 compatible = "samsung,exynosautov9-hsi2c"; 674 reg = <0x11d20000 0xc0>; 675 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&hsi2c4_pins>; 680 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, 681 <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; 682 clock-names = "hsi2c", "hsi2c_pclk"; 683 status = "disabled"; 684 }; 685 686 serial_2: serial@11d20000 { 687 compatible = "samsung,exynos850-uart"; 688 reg = <0x11d20000 0xc0>; 689 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 690 pinctrl-names = "default"; 691 pinctrl-0 = <&uart2_single_pins>; 692 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 693 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 694 clock-names = "uart", "clk_uart_baud0"; 695 status = "disabled"; 696 }; 697 }; 698 }; 699}; 700 701#include "exynos850-pinctrl.dtsi" 702