1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos850 SoC device tree source 4 * 5 * Copyright (C) 2018 Samsung Electronics Co., Ltd. 6 * Copyright (C) 2021 Linaro Ltd. 7 * 8 * Samsung Exynos850 SoC device nodes are listed in this file. 9 * Exynos850 based board files can include this file and provide 10 * values for board specific bindings. 11 */ 12 13#include <dt-bindings/clock/exynos850.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/samsung,exynos-usi.h> 16 17/ { 18 /* Also known under engineering name Exynos3830 */ 19 compatible = "samsung,exynos850"; 20 #address-cells = <2>; 21 #size-cells = <1>; 22 23 interrupt-parent = <&gic>; 24 25 aliases { 26 pinctrl0 = &pinctrl_alive; 27 pinctrl1 = &pinctrl_cmgp; 28 pinctrl2 = &pinctrl_aud; 29 pinctrl3 = &pinctrl_hsi; 30 pinctrl4 = &pinctrl_core; 31 pinctrl5 = &pinctrl_peri; 32 }; 33 34 arm-pmu { 35 compatible = "arm,cortex-a55-pmu"; 36 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 44 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 45 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 46 }; 47 48 /* Main system clock (XTCXO); external, must be 26 MHz */ 49 oscclk: clock-oscclk { 50 compatible = "fixed-clock"; 51 clock-output-names = "oscclk"; 52 #clock-cells = <0>; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu-map { 60 cluster0 { 61 core0 { 62 cpu = <&cpu0>; 63 }; 64 core1 { 65 cpu = <&cpu1>; 66 }; 67 core2 { 68 cpu = <&cpu2>; 69 }; 70 core3 { 71 cpu = <&cpu3>; 72 }; 73 }; 74 75 cluster1 { 76 core0 { 77 cpu = <&cpu4>; 78 }; 79 core1 { 80 cpu = <&cpu5>; 81 }; 82 core2 { 83 cpu = <&cpu6>; 84 }; 85 core3 { 86 cpu = <&cpu7>; 87 }; 88 }; 89 }; 90 91 cpu0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0>; 95 enable-method = "psci"; 96 }; 97 cpu1: cpu@1 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a55"; 100 reg = <0x1>; 101 enable-method = "psci"; 102 }; 103 cpu2: cpu@2 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a55"; 106 reg = <0x2>; 107 enable-method = "psci"; 108 }; 109 cpu3: cpu@3 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a55"; 112 reg = <0x3>; 113 enable-method = "psci"; 114 }; 115 cpu4: cpu@100 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x100>; 119 enable-method = "psci"; 120 }; 121 cpu5: cpu@101 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a55"; 124 reg = <0x101>; 125 enable-method = "psci"; 126 }; 127 cpu6: cpu@102 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a55"; 130 reg = <0x102>; 131 enable-method = "psci"; 132 }; 133 cpu7: cpu@103 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a55"; 136 reg = <0x103>; 137 enable-method = "psci"; 138 }; 139 }; 140 141 psci { 142 compatible = "arm,psci-1.0"; 143 method = "smc"; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 /* Hypervisor Virtual Timer interrupt is not wired to GIC */ 149 interrupts = 150 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 152 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 153 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 154 }; 155 156 soc: soc@0 { 157 compatible = "simple-bus"; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 ranges = <0x0 0x0 0x0 0x20000000>; 161 162 chipid@10000000 { 163 compatible = "samsung,exynos850-chipid"; 164 reg = <0x10000000 0x100>; 165 }; 166 167 timer@10040000 { 168 compatible = "samsung,exynos850-mct", 169 "samsung,exynos4210-mct"; 170 reg = <0x10040000 0x800>; 171 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>; 184 clock-names = "fin_pll", "mct"; 185 }; 186 187 gic: interrupt-controller@12a01000 { 188 compatible = "arm,gic-400"; 189 #interrupt-cells = <3>; 190 #address-cells = <0>; 191 reg = <0x12a01000 0x1000>, 192 <0x12a02000 0x2000>, 193 <0x12a04000 0x2000>, 194 <0x12a06000 0x2000>; 195 interrupt-controller; 196 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 197 IRQ_TYPE_LEVEL_HIGH)>; 198 }; 199 200 pmu_system_controller: system-controller@11860000 { 201 compatible = "samsung,exynos850-pmu", "syscon"; 202 reg = <0x11860000 0x10000>; 203 204 reboot: syscon-reboot { 205 compatible = "syscon-reboot"; 206 regmap = <&pmu_system_controller>; 207 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 208 mask = <0x2>; /* SWRESET_SYSTEM */ 209 value = <0x2>; /* reset value */ 210 }; 211 }; 212 213 watchdog_cl0: watchdog@10050000 { 214 compatible = "samsung,exynos850-wdt"; 215 reg = <0x10050000 0x100>; 216 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; 218 clock-names = "watchdog", "watchdog_src"; 219 samsung,syscon-phandle = <&pmu_system_controller>; 220 samsung,cluster-index = <0>; 221 status = "disabled"; 222 }; 223 224 watchdog_cl1: watchdog@10060000 { 225 compatible = "samsung,exynos850-wdt"; 226 reg = <0x10060000 0x100>; 227 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; 229 clock-names = "watchdog", "watchdog_src"; 230 samsung,syscon-phandle = <&pmu_system_controller>; 231 samsung,cluster-index = <1>; 232 status = "disabled"; 233 }; 234 235 cmu_peri: clock-controller@10030000 { 236 compatible = "samsung,exynos850-cmu-peri"; 237 reg = <0x10030000 0x8000>; 238 #clock-cells = <1>; 239 240 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, 241 <&cmu_top CLK_DOUT_PERI_UART>, 242 <&cmu_top CLK_DOUT_PERI_IP>; 243 clock-names = "oscclk", "dout_peri_bus", 244 "dout_peri_uart", "dout_peri_ip"; 245 }; 246 247 cmu_g3d: clock-controller@11400000 { 248 compatible = "samsung,exynos850-cmu-g3d"; 249 reg = <0x11400000 0x8000>; 250 #clock-cells = <1>; 251 252 clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>; 253 clock-names = "oscclk", "dout_g3d_switch"; 254 }; 255 256 cmu_apm: clock-controller@11800000 { 257 compatible = "samsung,exynos850-cmu-apm"; 258 reg = <0x11800000 0x8000>; 259 #clock-cells = <1>; 260 261 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>; 262 clock-names = "oscclk", "dout_clkcmu_apm_bus"; 263 }; 264 265 cmu_cmgp: clock-controller@11c00000 { 266 compatible = "samsung,exynos850-cmu-cmgp"; 267 reg = <0x11c00000 0x8000>; 268 #clock-cells = <1>; 269 270 clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>; 271 clock-names = "oscclk", "gout_clkcmu_cmgp_bus"; 272 }; 273 274 cmu_core: clock-controller@12000000 { 275 compatible = "samsung,exynos850-cmu-core"; 276 reg = <0x12000000 0x8000>; 277 #clock-cells = <1>; 278 279 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>, 280 <&cmu_top CLK_DOUT_CORE_CCI>, 281 <&cmu_top CLK_DOUT_CORE_MMC_EMBD>, 282 <&cmu_top CLK_DOUT_CORE_SSS>; 283 clock-names = "oscclk", "dout_core_bus", 284 "dout_core_cci", "dout_core_mmc_embd", 285 "dout_core_sss"; 286 }; 287 288 cmu_top: clock-controller@120e0000 { 289 compatible = "samsung,exynos850-cmu-top"; 290 reg = <0x120e0000 0x8000>; 291 #clock-cells = <1>; 292 293 clocks = <&oscclk>; 294 clock-names = "oscclk"; 295 }; 296 297 cmu_mfcmscl: clock-controller@12c00000 { 298 compatible = "samsung,exynos850-cmu-mfcmscl"; 299 reg = <0x12c00000 0x8000>; 300 #clock-cells = <1>; 301 302 clocks = <&oscclk>, 303 <&cmu_top CLK_DOUT_MFCMSCL_MFC>, 304 <&cmu_top CLK_DOUT_MFCMSCL_M2M>, 305 <&cmu_top CLK_DOUT_MFCMSCL_MCSC>, 306 <&cmu_top CLK_DOUT_MFCMSCL_JPEG>; 307 clock-names = "oscclk", "dout_mfcmscl_mfc", 308 "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc", 309 "dout_mfcmscl_jpeg"; 310 }; 311 312 cmu_dpu: clock-controller@13000000 { 313 compatible = "samsung,exynos850-cmu-dpu"; 314 reg = <0x13000000 0x8000>; 315 #clock-cells = <1>; 316 317 clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>; 318 clock-names = "oscclk", "dout_dpu"; 319 }; 320 321 cmu_hsi: clock-controller@13400000 { 322 compatible = "samsung,exynos850-cmu-hsi"; 323 reg = <0x13400000 0x8000>; 324 #clock-cells = <1>; 325 326 clocks = <&oscclk>, 327 <&cmu_top CLK_DOUT_HSI_BUS>, 328 <&cmu_top CLK_DOUT_HSI_MMC_CARD>, 329 <&cmu_top CLK_DOUT_HSI_USB20DRD>; 330 clock-names = "oscclk", "dout_hsi_bus", 331 "dout_hsi_mmc_card", "dout_hsi_usb20drd"; 332 }; 333 334 cmu_is: clock-controller@14500000 { 335 compatible = "samsung,exynos850-cmu-is"; 336 reg = <0x14500000 0x8000>; 337 #clock-cells = <1>; 338 339 clocks = <&oscclk>, 340 <&cmu_top CLK_DOUT_IS_BUS>, 341 <&cmu_top CLK_DOUT_IS_ITP>, 342 <&cmu_top CLK_DOUT_IS_VRA>, 343 <&cmu_top CLK_DOUT_IS_GDC>; 344 clock-names = "oscclk", "dout_is_bus", "dout_is_itp", 345 "dout_is_vra", "dout_is_gdc"; 346 }; 347 348 cmu_aud: clock-controller@14a00000 { 349 compatible = "samsung,exynos850-cmu-aud"; 350 reg = <0x14a00000 0x8000>; 351 #clock-cells = <1>; 352 353 clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>; 354 clock-names = "oscclk", "dout_aud"; 355 }; 356 357 pinctrl_alive: pinctrl@11850000 { 358 compatible = "samsung,exynos850-pinctrl"; 359 reg = <0x11850000 0x1000>; 360 361 wakeup-interrupt-controller { 362 compatible = "samsung,exynos850-wakeup-eint", 363 "samsung,exynos7-wakeup-eint"; 364 }; 365 }; 366 367 pinctrl_cmgp: pinctrl@11c30000 { 368 compatible = "samsung,exynos850-pinctrl"; 369 reg = <0x11c30000 0x1000>; 370 371 wakeup-interrupt-controller { 372 compatible = "samsung,exynos850-wakeup-eint", 373 "samsung,exynos7-wakeup-eint"; 374 }; 375 }; 376 377 pinctrl_core: pinctrl@12070000 { 378 compatible = "samsung,exynos850-pinctrl"; 379 reg = <0x12070000 0x1000>; 380 interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>; 381 }; 382 383 pinctrl_hsi: pinctrl@13430000 { 384 compatible = "samsung,exynos850-pinctrl"; 385 reg = <0x13430000 0x1000>; 386 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 387 }; 388 389 pinctrl_peri: pinctrl@139b0000 { 390 compatible = "samsung,exynos850-pinctrl"; 391 reg = <0x139b0000 0x1000>; 392 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 393 }; 394 395 pinctrl_aud: pinctrl@14a60000 { 396 compatible = "samsung,exynos850-pinctrl"; 397 reg = <0x14a60000 0x1000>; 398 }; 399 400 rtc: rtc@11a30000 { 401 compatible = "samsung,exynos850-rtc", "samsung,s3c6410-rtc"; 402 reg = <0x11a30000 0x100>; 403 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>; 406 clock-names = "rtc"; 407 status = "disabled"; 408 }; 409 410 mmc_0: mmc@12100000 { 411 compatible = "samsung,exynos850-dw-mshc-smu", 412 "samsung,exynos7-dw-mshc-smu"; 413 reg = <0x12100000 0x2000>; 414 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>, 418 <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; 419 clock-names = "biu", "ciu"; 420 fifo-depth = <0x40>; 421 status = "disabled"; 422 }; 423 424 i2c_0: i2c@13830000 { 425 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 426 reg = <0x13830000 0x100>; 427 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&i2c0_pins>; 432 clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; 433 clock-names = "i2c"; 434 status = "disabled"; 435 }; 436 437 i2c_1: i2c@13840000 { 438 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 439 reg = <0x13840000 0x100>; 440 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&i2c1_pins>; 445 clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; 446 clock-names = "i2c"; 447 status = "disabled"; 448 }; 449 450 i2c_2: i2c@13850000 { 451 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 452 reg = <0x13850000 0x100>; 453 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&i2c2_pins>; 458 clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; 459 clock-names = "i2c"; 460 status = "disabled"; 461 }; 462 463 i2c_3: i2c@13860000 { 464 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 465 reg = <0x13860000 0x100>; 466 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&i2c3_pins>; 471 clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; 472 clock-names = "i2c"; 473 status = "disabled"; 474 }; 475 476 i2c_4: i2c@13870000 { 477 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 478 reg = <0x13870000 0x100>; 479 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&i2c4_pins>; 484 clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; 485 clock-names = "i2c"; 486 status = "disabled"; 487 }; 488 489 /* I2C_5 (also called CAM_PMIC_I2C in TRM) */ 490 i2c_5: i2c@13880000 { 491 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 492 reg = <0x13880000 0x100>; 493 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 pinctrl-names = "default"; 497 pinctrl-0 = <&i2c5_pins>; 498 clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; 499 clock-names = "i2c"; 500 status = "disabled"; 501 }; 502 503 /* I2C_6 (also called MOTOR_I2C in TRM) */ 504 i2c_6: i2c@13890000 { 505 compatible = "samsung,exynos850-i2c", "samsung,s3c2440-i2c"; 506 reg = <0x13890000 0x100>; 507 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&i2c6_pins>; 512 clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; 513 clock-names = "i2c"; 514 status = "disabled"; 515 }; 516 517 sysmmu_mfcmscl: sysmmu@12c50000 { 518 compatible = "samsung,exynos-sysmmu"; 519 reg = <0x12c50000 0x9000>; 520 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 521 clock-names = "sysmmu"; 522 clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>; 523 #iommu-cells = <0>; 524 }; 525 526 sysmmu_dpu: sysmmu@130c0000 { 527 compatible = "samsung,exynos-sysmmu"; 528 reg = <0x130c0000 0x9000>; 529 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 530 clock-names = "sysmmu"; 531 clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>; 532 #iommu-cells = <0>; 533 }; 534 535 sysmmu_is0: sysmmu@14550000 { 536 compatible = "samsung,exynos-sysmmu"; 537 reg = <0x14550000 0x9000>; 538 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 539 clock-names = "sysmmu"; 540 clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>; 541 #iommu-cells = <0>; 542 }; 543 544 sysmmu_is1: sysmmu@14570000 { 545 compatible = "samsung,exynos-sysmmu"; 546 reg = <0x14570000 0x9000>; 547 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 548 clock-names = "sysmmu"; 549 clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>; 550 #iommu-cells = <0>; 551 }; 552 553 sysmmu_aud: sysmmu@14850000 { 554 compatible = "samsung,exynos-sysmmu"; 555 reg = <0x14850000 0x9000>; 556 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 557 clock-names = "sysmmu"; 558 clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>; 559 #iommu-cells = <0>; 560 }; 561 562 sysreg_peri: syscon@10020000 { 563 compatible = "samsung,exynos850-peri-sysreg", 564 "samsung,exynos850-sysreg", "syscon"; 565 reg = <0x10020000 0x10000>; 566 clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; 567 }; 568 569 sysreg_cmgp: syscon@11c20000 { 570 compatible = "samsung,exynos850-cmgp-sysreg", 571 "samsung,exynos850-sysreg", "syscon"; 572 reg = <0x11c20000 0x10000>; 573 clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; 574 }; 575 576 usbdrd: usb@13600000 { 577 compatible = "samsung,exynos850-dwusb3"; 578 ranges = <0x0 0x13600000 0x10000>; 579 clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>, 580 <&cmu_hsi CLK_GOUT_USB_REF_CLK>; 581 clock-names = "bus_early", "ref"; 582 #address-cells = <1>; 583 #size-cells = <1>; 584 status = "disabled"; 585 586 usbdrd_dwc3: usb@0 { 587 compatible = "snps,dwc3"; 588 reg = <0x0 0x10000>; 589 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 590 phys = <&usbdrd_phy 0>; 591 phy-names = "usb2-phy"; 592 }; 593 }; 594 595 usbdrd_phy: phy@135d0000 { 596 compatible = "samsung,exynos850-usbdrd-phy"; 597 reg = <0x135d0000 0x100>; 598 clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>, 599 <&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>; 600 clock-names = "phy", "ref"; 601 samsung,pmu-syscon = <&pmu_system_controller>; 602 #phy-cells = <1>; 603 status = "disabled"; 604 }; 605 606 usi_uart: usi@138200c0 { 607 compatible = "samsung,exynos850-usi"; 608 reg = <0x138200c0 0x20>; 609 samsung,sysreg = <&sysreg_peri 0x1010>; 610 samsung,mode = <USI_V2_UART>; 611 #address-cells = <1>; 612 #size-cells = <1>; 613 ranges; 614 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 615 <&cmu_peri CLK_GOUT_UART_IPCLK>; 616 clock-names = "pclk", "ipclk"; 617 status = "disabled"; 618 619 serial_0: serial@13820000 { 620 compatible = "samsung,exynos850-uart"; 621 reg = <0x13820000 0xc0>; 622 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 623 pinctrl-names = "default"; 624 pinctrl-0 = <&uart0_pins>; 625 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 626 <&cmu_peri CLK_GOUT_UART_IPCLK>; 627 clock-names = "uart", "clk_uart_baud0"; 628 status = "disabled"; 629 }; 630 }; 631 632 usi_hsi2c_0: usi@138a00c0 { 633 compatible = "samsung,exynos850-usi"; 634 reg = <0x138a00c0 0x20>; 635 samsung,sysreg = <&sysreg_peri 0x1020>; 636 samsung,mode = <USI_V2_I2C>; 637 #address-cells = <1>; 638 #size-cells = <1>; 639 ranges; 640 clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, 641 <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; 642 clock-names = "pclk", "ipclk"; 643 status = "disabled"; 644 645 hsi2c_0: i2c@138a0000 { 646 compatible = "samsung,exynos850-hsi2c", 647 "samsung,exynosautov9-hsi2c"; 648 reg = <0x138a0000 0xc0>; 649 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 pinctrl-names = "default"; 653 pinctrl-0 = <&hsi2c0_pins>; 654 clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, 655 <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; 656 clock-names = "hsi2c", "hsi2c_pclk"; 657 status = "disabled"; 658 }; 659 }; 660 661 usi_hsi2c_1: usi@138b00c0 { 662 compatible = "samsung,exynos850-usi"; 663 reg = <0x138b00c0 0x20>; 664 samsung,sysreg = <&sysreg_peri 0x1030>; 665 samsung,mode = <USI_V2_I2C>; 666 #address-cells = <1>; 667 #size-cells = <1>; 668 ranges; 669 clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, 670 <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; 671 clock-names = "pclk", "ipclk"; 672 status = "disabled"; 673 674 hsi2c_1: i2c@138b0000 { 675 compatible = "samsung,exynos850-hsi2c", 676 "samsung,exynosautov9-hsi2c"; 677 reg = <0x138b0000 0xc0>; 678 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&hsi2c1_pins>; 683 clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, 684 <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; 685 clock-names = "hsi2c", "hsi2c_pclk"; 686 status = "disabled"; 687 }; 688 }; 689 690 usi_hsi2c_2: usi@138c00c0 { 691 compatible = "samsung,exynos850-usi"; 692 reg = <0x138c00c0 0x20>; 693 samsung,sysreg = <&sysreg_peri 0x1040>; 694 samsung,mode = <USI_V2_I2C>; 695 #address-cells = <1>; 696 #size-cells = <1>; 697 ranges; 698 clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, 699 <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; 700 clock-names = "pclk", "ipclk"; 701 status = "disabled"; 702 703 hsi2c_2: i2c@138c0000 { 704 compatible = "samsung,exynos850-hsi2c", 705 "samsung,exynosautov9-hsi2c"; 706 reg = <0x138c0000 0xc0>; 707 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 pinctrl-names = "default"; 711 pinctrl-0 = <&hsi2c2_pins>; 712 clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, 713 <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; 714 clock-names = "hsi2c", "hsi2c_pclk"; 715 status = "disabled"; 716 }; 717 }; 718 719 usi_spi_0: usi@139400c0 { 720 compatible = "samsung,exynos850-usi"; 721 reg = <0x139400c0 0x20>; 722 samsung,sysreg = <&sysreg_peri 0x1050>; 723 samsung,mode = <USI_V2_SPI>; 724 #address-cells = <1>; 725 #size-cells = <1>; 726 ranges; 727 clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, 728 <&cmu_peri CLK_GOUT_SPI0_IPCLK>; 729 clock-names = "pclk", "ipclk"; 730 status = "disabled"; 731 }; 732 733 usi_cmgp0: usi@11d000c0 { 734 compatible = "samsung,exynos850-usi"; 735 reg = <0x11d000c0 0x20>; 736 samsung,sysreg = <&sysreg_cmgp 0x2000>; 737 samsung,mode = <USI_V2_I2C>; 738 #address-cells = <1>; 739 #size-cells = <1>; 740 ranges; 741 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 742 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 743 clock-names = "pclk", "ipclk"; 744 status = "disabled"; 745 746 hsi2c_3: i2c@11d00000 { 747 compatible = "samsung,exynos850-hsi2c", 748 "samsung,exynosautov9-hsi2c"; 749 reg = <0x11d00000 0xc0>; 750 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 pinctrl-names = "default"; 754 pinctrl-0 = <&hsi2c3_pins>; 755 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, 756 <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; 757 clock-names = "hsi2c", "hsi2c_pclk"; 758 status = "disabled"; 759 }; 760 761 serial_1: serial@11d00000 { 762 compatible = "samsung,exynos850-uart"; 763 reg = <0x11d00000 0xc0>; 764 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 765 pinctrl-names = "default"; 766 pinctrl-0 = <&uart1_single_pins>; 767 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 768 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 769 clock-names = "uart", "clk_uart_baud0"; 770 status = "disabled"; 771 }; 772 }; 773 774 usi_cmgp1: usi@11d200c0 { 775 compatible = "samsung,exynos850-usi"; 776 reg = <0x11d200c0 0x20>; 777 samsung,sysreg = <&sysreg_cmgp 0x2010>; 778 samsung,mode = <USI_V2_I2C>; 779 #address-cells = <1>; 780 #size-cells = <1>; 781 ranges; 782 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 783 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 784 clock-names = "pclk", "ipclk"; 785 status = "disabled"; 786 787 hsi2c_4: i2c@11d20000 { 788 compatible = "samsung,exynos850-hsi2c", 789 "samsung,exynosautov9-hsi2c"; 790 reg = <0x11d20000 0xc0>; 791 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 792 #address-cells = <1>; 793 #size-cells = <0>; 794 pinctrl-names = "default"; 795 pinctrl-0 = <&hsi2c4_pins>; 796 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, 797 <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; 798 clock-names = "hsi2c", "hsi2c_pclk"; 799 status = "disabled"; 800 }; 801 802 serial_2: serial@11d20000 { 803 compatible = "samsung,exynos850-uart"; 804 reg = <0x11d20000 0xc0>; 805 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 806 pinctrl-names = "default"; 807 pinctrl-0 = <&uart2_single_pins>; 808 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 809 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 810 clock-names = "uart", "clk_uart_baud0"; 811 status = "disabled"; 812 }; 813 }; 814 }; 815}; 816 817#include "exynos850-pinctrl.dtsi" 818