1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Samsung Exynos850 SoC device tree source 4 * 5 * Copyright (C) 2018 Samsung Electronics Co., Ltd. 6 * Copyright (C) 2021 Linaro Ltd. 7 * 8 * Samsung Exynos850 SoC device nodes are listed in this file. 9 * Exynos850 based board files can include this file and provide 10 * values for board specific bindings. 11 */ 12 13#include <dt-bindings/clock/exynos850.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/samsung,exynos-usi.h> 16 17/ { 18 /* Also known under engineering name Exynos3830 */ 19 compatible = "samsung,exynos850"; 20 #address-cells = <2>; 21 #size-cells = <1>; 22 23 interrupt-parent = <&gic>; 24 25 aliases { 26 pinctrl0 = &pinctrl_alive; 27 pinctrl1 = &pinctrl_cmgp; 28 pinctrl2 = &pinctrl_aud; 29 pinctrl3 = &pinctrl_hsi; 30 pinctrl4 = &pinctrl_core; 31 pinctrl5 = &pinctrl_peri; 32 }; 33 34 arm-pmu { 35 compatible = "arm,cortex-a55-pmu"; 36 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 44 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 45 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 46 }; 47 48 /* Main system clock (XTCXO); external, must be 26 MHz */ 49 oscclk: clock-oscclk { 50 compatible = "fixed-clock"; 51 clock-output-names = "oscclk"; 52 #clock-cells = <0>; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 cpu-map { 60 cluster0 { 61 core0 { 62 cpu = <&cpu0>; 63 }; 64 core1 { 65 cpu = <&cpu1>; 66 }; 67 core2 { 68 cpu = <&cpu2>; 69 }; 70 core3 { 71 cpu = <&cpu3>; 72 }; 73 }; 74 75 cluster1 { 76 core0 { 77 cpu = <&cpu4>; 78 }; 79 core1 { 80 cpu = <&cpu5>; 81 }; 82 core2 { 83 cpu = <&cpu6>; 84 }; 85 core3 { 86 cpu = <&cpu7>; 87 }; 88 }; 89 }; 90 91 cpu0: cpu@0 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x0>; 95 enable-method = "psci"; 96 }; 97 cpu1: cpu@1 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a55"; 100 reg = <0x1>; 101 enable-method = "psci"; 102 }; 103 cpu2: cpu@2 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a55"; 106 reg = <0x2>; 107 enable-method = "psci"; 108 }; 109 cpu3: cpu@3 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a55"; 112 reg = <0x3>; 113 enable-method = "psci"; 114 }; 115 cpu4: cpu@100 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x100>; 119 enable-method = "psci"; 120 }; 121 cpu5: cpu@101 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a55"; 124 reg = <0x101>; 125 enable-method = "psci"; 126 }; 127 cpu6: cpu@102 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a55"; 130 reg = <0x102>; 131 enable-method = "psci"; 132 }; 133 cpu7: cpu@103 { 134 device_type = "cpu"; 135 compatible = "arm,cortex-a55"; 136 reg = <0x103>; 137 enable-method = "psci"; 138 }; 139 }; 140 141 psci { 142 compatible = "arm,psci-1.0"; 143 method = "smc"; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 /* Hypervisor Virtual Timer interrupt is not wired to GIC */ 149 interrupts = 150 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 151 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 152 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 153 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 154 }; 155 156 soc: soc@0 { 157 compatible = "simple-bus"; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 ranges = <0x0 0x0 0x0 0x20000000>; 161 162 chipid@10000000 { 163 compatible = "samsung,exynos850-chipid"; 164 reg = <0x10000000 0x100>; 165 }; 166 167 timer@10040000 { 168 compatible = "samsung,exynos850-mct", 169 "samsung,exynos4210-mct"; 170 reg = <0x10040000 0x800>; 171 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 183 clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>; 184 clock-names = "fin_pll", "mct"; 185 }; 186 187 gic: interrupt-controller@12a01000 { 188 compatible = "arm,gic-400"; 189 #interrupt-cells = <3>; 190 #address-cells = <0>; 191 reg = <0x12a01000 0x1000>, 192 <0x12a02000 0x2000>, 193 <0x12a04000 0x2000>, 194 <0x12a06000 0x2000>; 195 interrupt-controller; 196 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 197 IRQ_TYPE_LEVEL_HIGH)>; 198 }; 199 200 pmu_system_controller: system-controller@11860000 { 201 compatible = "samsung,exynos850-pmu", "syscon"; 202 reg = <0x11860000 0x10000>; 203 clocks = <&cmu_apm CLK_GOUT_PMU_ALIVE_PCLK>; 204 205 reboot: syscon-reboot { 206 compatible = "syscon-reboot"; 207 regmap = <&pmu_system_controller>; 208 offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ 209 mask = <0x2>; /* SWRESET_SYSTEM */ 210 value = <0x2>; /* reset value */ 211 }; 212 }; 213 214 watchdog_cl0: watchdog@10050000 { 215 compatible = "samsung,exynos850-wdt"; 216 reg = <0x10050000 0x100>; 217 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; 219 clock-names = "watchdog", "watchdog_src"; 220 samsung,syscon-phandle = <&pmu_system_controller>; 221 samsung,cluster-index = <0>; 222 status = "disabled"; 223 }; 224 225 watchdog_cl1: watchdog@10060000 { 226 compatible = "samsung,exynos850-wdt"; 227 reg = <0x10060000 0x100>; 228 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; 230 clock-names = "watchdog", "watchdog_src"; 231 samsung,syscon-phandle = <&pmu_system_controller>; 232 samsung,cluster-index = <1>; 233 status = "disabled"; 234 }; 235 236 cmu_peri: clock-controller@10030000 { 237 compatible = "samsung,exynos850-cmu-peri"; 238 reg = <0x10030000 0x8000>; 239 #clock-cells = <1>; 240 241 clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, 242 <&cmu_top CLK_DOUT_PERI_UART>, 243 <&cmu_top CLK_DOUT_PERI_IP>; 244 clock-names = "oscclk", "dout_peri_bus", 245 "dout_peri_uart", "dout_peri_ip"; 246 }; 247 248 cmu_g3d: clock-controller@11400000 { 249 compatible = "samsung,exynos850-cmu-g3d"; 250 reg = <0x11400000 0x8000>; 251 #clock-cells = <1>; 252 253 clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>; 254 clock-names = "oscclk", "dout_g3d_switch"; 255 }; 256 257 cmu_apm: clock-controller@11800000 { 258 compatible = "samsung,exynos850-cmu-apm"; 259 reg = <0x11800000 0x8000>; 260 #clock-cells = <1>; 261 262 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>; 263 clock-names = "oscclk", "dout_clkcmu_apm_bus"; 264 }; 265 266 cmu_cmgp: clock-controller@11c00000 { 267 compatible = "samsung,exynos850-cmu-cmgp"; 268 reg = <0x11c00000 0x8000>; 269 #clock-cells = <1>; 270 271 clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>; 272 clock-names = "oscclk", "gout_clkcmu_cmgp_bus"; 273 }; 274 275 cmu_core: clock-controller@12000000 { 276 compatible = "samsung,exynos850-cmu-core"; 277 reg = <0x12000000 0x8000>; 278 #clock-cells = <1>; 279 280 clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>, 281 <&cmu_top CLK_DOUT_CORE_CCI>, 282 <&cmu_top CLK_DOUT_CORE_MMC_EMBD>, 283 <&cmu_top CLK_DOUT_CORE_SSS>; 284 clock-names = "oscclk", "dout_core_bus", 285 "dout_core_cci", "dout_core_mmc_embd", 286 "dout_core_sss"; 287 }; 288 289 cmu_top: clock-controller@120e0000 { 290 compatible = "samsung,exynos850-cmu-top"; 291 reg = <0x120e0000 0x8000>; 292 #clock-cells = <1>; 293 294 clocks = <&oscclk>; 295 clock-names = "oscclk"; 296 }; 297 298 cmu_mfcmscl: clock-controller@12c00000 { 299 compatible = "samsung,exynos850-cmu-mfcmscl"; 300 reg = <0x12c00000 0x8000>; 301 #clock-cells = <1>; 302 303 clocks = <&oscclk>, 304 <&cmu_top CLK_DOUT_MFCMSCL_MFC>, 305 <&cmu_top CLK_DOUT_MFCMSCL_M2M>, 306 <&cmu_top CLK_DOUT_MFCMSCL_MCSC>, 307 <&cmu_top CLK_DOUT_MFCMSCL_JPEG>; 308 clock-names = "oscclk", "dout_mfcmscl_mfc", 309 "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc", 310 "dout_mfcmscl_jpeg"; 311 }; 312 313 cmu_dpu: clock-controller@13000000 { 314 compatible = "samsung,exynos850-cmu-dpu"; 315 reg = <0x13000000 0x8000>; 316 #clock-cells = <1>; 317 318 clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>; 319 clock-names = "oscclk", "dout_dpu"; 320 }; 321 322 cmu_hsi: clock-controller@13400000 { 323 compatible = "samsung,exynos850-cmu-hsi"; 324 reg = <0x13400000 0x8000>; 325 #clock-cells = <1>; 326 327 clocks = <&oscclk>, 328 <&cmu_top CLK_DOUT_HSI_BUS>, 329 <&cmu_top CLK_DOUT_HSI_MMC_CARD>, 330 <&cmu_top CLK_DOUT_HSI_USB20DRD>; 331 clock-names = "oscclk", "dout_hsi_bus", 332 "dout_hsi_mmc_card", "dout_hsi_usb20drd"; 333 }; 334 335 cmu_is: clock-controller@14500000 { 336 compatible = "samsung,exynos850-cmu-is"; 337 reg = <0x14500000 0x8000>; 338 #clock-cells = <1>; 339 340 clocks = <&oscclk>, 341 <&cmu_top CLK_DOUT_IS_BUS>, 342 <&cmu_top CLK_DOUT_IS_ITP>, 343 <&cmu_top CLK_DOUT_IS_VRA>, 344 <&cmu_top CLK_DOUT_IS_GDC>; 345 clock-names = "oscclk", "dout_is_bus", "dout_is_itp", 346 "dout_is_vra", "dout_is_gdc"; 347 }; 348 349 cmu_aud: clock-controller@14a00000 { 350 compatible = "samsung,exynos850-cmu-aud"; 351 reg = <0x14a00000 0x8000>; 352 #clock-cells = <1>; 353 354 clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>; 355 clock-names = "oscclk", "dout_aud"; 356 }; 357 358 pinctrl_alive: pinctrl@11850000 { 359 compatible = "samsung,exynos850-pinctrl"; 360 reg = <0x11850000 0x1000>; 361 362 wakeup-interrupt-controller { 363 compatible = "samsung,exynos850-wakeup-eint"; 364 }; 365 }; 366 367 pinctrl_cmgp: pinctrl@11c30000 { 368 compatible = "samsung,exynos850-pinctrl"; 369 reg = <0x11c30000 0x1000>; 370 371 wakeup-interrupt-controller { 372 compatible = "samsung,exynos850-wakeup-eint"; 373 }; 374 }; 375 376 pinctrl_core: pinctrl@12070000 { 377 compatible = "samsung,exynos850-pinctrl"; 378 reg = <0x12070000 0x1000>; 379 interrupts = <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>; 380 }; 381 382 pinctrl_hsi: pinctrl@13430000 { 383 compatible = "samsung,exynos850-pinctrl"; 384 reg = <0x13430000 0x1000>; 385 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 386 }; 387 388 pinctrl_peri: pinctrl@139b0000 { 389 compatible = "samsung,exynos850-pinctrl"; 390 reg = <0x139b0000 0x1000>; 391 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 392 }; 393 394 pinctrl_aud: pinctrl@14a60000 { 395 compatible = "samsung,exynos850-pinctrl"; 396 reg = <0x14a60000 0x1000>; 397 }; 398 399 rtc: rtc@11a30000 { 400 compatible = "samsung,s3c6410-rtc"; 401 reg = <0x11a30000 0x100>; 402 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>; 405 clock-names = "rtc"; 406 status = "disabled"; 407 }; 408 409 mmc_0: mmc@12100000 { 410 compatible = "samsung,exynos7-dw-mshc-smu"; 411 reg = <0x12100000 0x2000>; 412 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>, 416 <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; 417 clock-names = "biu", "ciu"; 418 fifo-depth = <0x40>; 419 status = "disabled"; 420 }; 421 422 i2c_0: i2c@13830000 { 423 compatible = "samsung,s3c2440-i2c"; 424 reg = <0x13830000 0x100>; 425 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&i2c0_pins>; 430 clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; 431 clock-names = "i2c"; 432 status = "disabled"; 433 }; 434 435 i2c_1: i2c@13840000 { 436 compatible = "samsung,s3c2440-i2c"; 437 reg = <0x13840000 0x100>; 438 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&i2c1_pins>; 443 clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; 444 clock-names = "i2c"; 445 status = "disabled"; 446 }; 447 448 i2c_2: i2c@13850000 { 449 compatible = "samsung,s3c2440-i2c"; 450 reg = <0x13850000 0x100>; 451 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&i2c2_pins>; 456 clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; 457 clock-names = "i2c"; 458 status = "disabled"; 459 }; 460 461 i2c_3: i2c@13860000 { 462 compatible = "samsung,s3c2440-i2c"; 463 reg = <0x13860000 0x100>; 464 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&i2c3_pins>; 469 clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; 470 clock-names = "i2c"; 471 status = "disabled"; 472 }; 473 474 i2c_4: i2c@13870000 { 475 compatible = "samsung,s3c2440-i2c"; 476 reg = <0x13870000 0x100>; 477 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&i2c4_pins>; 482 clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; 483 clock-names = "i2c"; 484 status = "disabled"; 485 }; 486 487 /* I2C_5 (also called CAM_PMIC_I2C in TRM) */ 488 i2c_5: i2c@13880000 { 489 compatible = "samsung,s3c2440-i2c"; 490 reg = <0x13880000 0x100>; 491 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&i2c5_pins>; 496 clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; 497 clock-names = "i2c"; 498 status = "disabled"; 499 }; 500 501 /* I2C_6 (also called MOTOR_I2C in TRM) */ 502 i2c_6: i2c@13890000 { 503 compatible = "samsung,s3c2440-i2c"; 504 reg = <0x13890000 0x100>; 505 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 pinctrl-names = "default"; 509 pinctrl-0 = <&i2c6_pins>; 510 clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; 511 clock-names = "i2c"; 512 status = "disabled"; 513 }; 514 515 sysmmu_mfcmscl: sysmmu@12c50000 { 516 compatible = "samsung,exynos-sysmmu"; 517 reg = <0x12c50000 0x9000>; 518 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 519 clock-names = "sysmmu"; 520 clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>; 521 #iommu-cells = <0>; 522 }; 523 524 sysmmu_dpu: sysmmu@130c0000 { 525 compatible = "samsung,exynos-sysmmu"; 526 reg = <0x130c0000 0x9000>; 527 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 528 clock-names = "sysmmu"; 529 clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>; 530 #iommu-cells = <0>; 531 }; 532 533 sysmmu_is0: sysmmu@14550000 { 534 compatible = "samsung,exynos-sysmmu"; 535 reg = <0x14550000 0x9000>; 536 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 537 clock-names = "sysmmu"; 538 clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>; 539 #iommu-cells = <0>; 540 }; 541 542 sysmmu_is1: sysmmu@14570000 { 543 compatible = "samsung,exynos-sysmmu"; 544 reg = <0x14570000 0x9000>; 545 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 546 clock-names = "sysmmu"; 547 clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>; 548 #iommu-cells = <0>; 549 }; 550 551 sysmmu_aud: sysmmu@14850000 { 552 compatible = "samsung,exynos-sysmmu"; 553 reg = <0x14850000 0x9000>; 554 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 555 clock-names = "sysmmu"; 556 clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>; 557 #iommu-cells = <0>; 558 }; 559 560 sysreg_peri: syscon@10020000 { 561 compatible = "samsung,exynos850-peri-sysreg", 562 "samsung,exynos850-sysreg", "syscon"; 563 reg = <0x10020000 0x10000>; 564 clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; 565 }; 566 567 sysreg_cmgp: syscon@11c20000 { 568 compatible = "samsung,exynos850-cmgp-sysreg", 569 "samsung,exynos850-sysreg", "syscon"; 570 reg = <0x11c20000 0x10000>; 571 clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; 572 }; 573 574 usi_uart: usi@138200c0 { 575 compatible = "samsung,exynos850-usi"; 576 reg = <0x138200c0 0x20>; 577 samsung,sysreg = <&sysreg_peri 0x1010>; 578 samsung,mode = <USI_V2_UART>; 579 #address-cells = <1>; 580 #size-cells = <1>; 581 ranges; 582 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 583 <&cmu_peri CLK_GOUT_UART_IPCLK>; 584 clock-names = "pclk", "ipclk"; 585 status = "disabled"; 586 587 serial_0: serial@13820000 { 588 compatible = "samsung,exynos850-uart"; 589 reg = <0x13820000 0xc0>; 590 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 591 pinctrl-names = "default"; 592 pinctrl-0 = <&uart0_pins>; 593 clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, 594 <&cmu_peri CLK_GOUT_UART_IPCLK>; 595 clock-names = "uart", "clk_uart_baud0"; 596 status = "disabled"; 597 }; 598 }; 599 600 usi_hsi2c_0: usi@138a00c0 { 601 compatible = "samsung,exynos850-usi"; 602 reg = <0x138a00c0 0x20>; 603 samsung,sysreg = <&sysreg_peri 0x1020>; 604 samsung,mode = <USI_V2_I2C>; 605 #address-cells = <1>; 606 #size-cells = <1>; 607 ranges; 608 clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, 609 <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; 610 clock-names = "pclk", "ipclk"; 611 status = "disabled"; 612 613 hsi2c_0: i2c@138a0000 { 614 compatible = "samsung,exynosautov9-hsi2c"; 615 reg = <0x138a0000 0xc0>; 616 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&hsi2c0_pins>; 621 clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, 622 <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; 623 clock-names = "hsi2c", "hsi2c_pclk"; 624 status = "disabled"; 625 }; 626 }; 627 628 usi_hsi2c_1: usi@138b00c0 { 629 compatible = "samsung,exynos850-usi"; 630 reg = <0x138b00c0 0x20>; 631 samsung,sysreg = <&sysreg_peri 0x1030>; 632 samsung,mode = <USI_V2_I2C>; 633 #address-cells = <1>; 634 #size-cells = <1>; 635 ranges; 636 clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, 637 <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; 638 clock-names = "pclk", "ipclk"; 639 status = "disabled"; 640 641 hsi2c_1: i2c@138b0000 { 642 compatible = "samsung,exynosautov9-hsi2c"; 643 reg = <0x138b0000 0xc0>; 644 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 pinctrl-names = "default"; 648 pinctrl-0 = <&hsi2c1_pins>; 649 clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, 650 <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; 651 clock-names = "hsi2c", "hsi2c_pclk"; 652 status = "disabled"; 653 }; 654 }; 655 656 usi_hsi2c_2: usi@138c00c0 { 657 compatible = "samsung,exynos850-usi"; 658 reg = <0x138c00c0 0x20>; 659 samsung,sysreg = <&sysreg_peri 0x1040>; 660 samsung,mode = <USI_V2_I2C>; 661 #address-cells = <1>; 662 #size-cells = <1>; 663 ranges; 664 clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, 665 <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; 666 clock-names = "pclk", "ipclk"; 667 status = "disabled"; 668 669 hsi2c_2: i2c@138c0000 { 670 compatible = "samsung,exynosautov9-hsi2c"; 671 reg = <0x138c0000 0xc0>; 672 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 pinctrl-names = "default"; 676 pinctrl-0 = <&hsi2c2_pins>; 677 clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, 678 <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; 679 clock-names = "hsi2c", "hsi2c_pclk"; 680 status = "disabled"; 681 }; 682 }; 683 684 usi_spi_0: usi@139400c0 { 685 compatible = "samsung,exynos850-usi"; 686 reg = <0x139400c0 0x20>; 687 samsung,sysreg = <&sysreg_peri 0x1050>; 688 samsung,mode = <USI_V2_SPI>; 689 #address-cells = <1>; 690 #size-cells = <1>; 691 ranges; 692 clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, 693 <&cmu_peri CLK_GOUT_SPI0_IPCLK>; 694 clock-names = "pclk", "ipclk"; 695 status = "disabled"; 696 }; 697 698 usi_cmgp0: usi@11d000c0 { 699 compatible = "samsung,exynos850-usi"; 700 reg = <0x11d000c0 0x20>; 701 samsung,sysreg = <&sysreg_cmgp 0x2000>; 702 samsung,mode = <USI_V2_I2C>; 703 #address-cells = <1>; 704 #size-cells = <1>; 705 ranges; 706 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 707 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 708 clock-names = "pclk", "ipclk"; 709 status = "disabled"; 710 711 hsi2c_3: i2c@11d00000 { 712 compatible = "samsung,exynosautov9-hsi2c"; 713 reg = <0x11d00000 0xc0>; 714 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 pinctrl-names = "default"; 718 pinctrl-0 = <&hsi2c3_pins>; 719 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, 720 <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; 721 clock-names = "hsi2c", "hsi2c_pclk"; 722 status = "disabled"; 723 }; 724 725 serial_1: serial@11d00000 { 726 compatible = "samsung,exynos850-uart"; 727 reg = <0x11d00000 0xc0>; 728 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 729 pinctrl-names = "default"; 730 pinctrl-0 = <&uart1_single_pins>; 731 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, 732 <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; 733 clock-names = "uart", "clk_uart_baud0"; 734 status = "disabled"; 735 }; 736 }; 737 738 usi_cmgp1: usi@11d200c0 { 739 compatible = "samsung,exynos850-usi"; 740 reg = <0x11d200c0 0x20>; 741 samsung,sysreg = <&sysreg_cmgp 0x2010>; 742 samsung,mode = <USI_V2_I2C>; 743 #address-cells = <1>; 744 #size-cells = <1>; 745 ranges; 746 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 747 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 748 clock-names = "pclk", "ipclk"; 749 status = "disabled"; 750 751 hsi2c_4: i2c@11d20000 { 752 compatible = "samsung,exynosautov9-hsi2c"; 753 reg = <0x11d20000 0xc0>; 754 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 pinctrl-names = "default"; 758 pinctrl-0 = <&hsi2c4_pins>; 759 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, 760 <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; 761 clock-names = "hsi2c", "hsi2c_pclk"; 762 status = "disabled"; 763 }; 764 765 serial_2: serial@11d20000 { 766 compatible = "samsung,exynos850-uart"; 767 reg = <0x11d20000 0xc0>; 768 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 769 pinctrl-names = "default"; 770 pinctrl-0 = <&uart2_single_pins>; 771 clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, 772 <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; 773 clock-names = "uart", "clk_uart_baud0"; 774 status = "disabled"; 775 }; 776 }; 777 }; 778}; 779 780#include "exynos850-pinctrl.dtsi" 781