1*1537cf73SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2*1537cf73SEmmanuel Vadot /* 3*1537cf73SEmmanuel Vadot * Axis ARTPEC-8 SoC device tree pinctrl constants 4*1537cf73SEmmanuel Vadot * 5*1537cf73SEmmanuel Vadot * Copyright (c) 2025 Samsung Electronics Co., Ltd. 6*1537cf73SEmmanuel Vadot * https://www.samsung.com 7*1537cf73SEmmanuel Vadot * Copyright (c) 2025 Axis Communications AB. 8*1537cf73SEmmanuel Vadot * https://www.axis.com 9*1537cf73SEmmanuel Vadot */ 10*1537cf73SEmmanuel Vadot 11*1537cf73SEmmanuel Vadot #ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ 12*1537cf73SEmmanuel Vadot #define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ 13*1537cf73SEmmanuel Vadot 14*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_PULL_NONE 0 15*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_PULL_DOWN 1 16*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_PULL_UP 3 17*1537cf73SEmmanuel Vadot 18*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_FUNC_INPUT 0 19*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_FUNC_OUTPUT 1 20*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_FUNC_2 2 21*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_FUNC_3 3 22*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_FUNC_4 4 23*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_FUNC_5 5 24*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_FUNC_6 6 25*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_FUNC_EINT 0xf 26*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_FUNC_F ARTPEC_PIN_FUNC_EINT 27*1537cf73SEmmanuel Vadot 28*1537cf73SEmmanuel Vadot /* Drive strength for ARTPEC */ 29*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_DRV_SR1 0x8 30*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_DRV_SR2 0x9 31*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_DRV_SR3 0xa 32*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_DRV_SR4 0xb 33*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_DRV_SR5 0xc 34*1537cf73SEmmanuel Vadot #define ARTPEC_PIN_DRV_SR6 0xd 35*1537cf73SEmmanuel Vadot 36*1537cf73SEmmanuel Vadot #endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */ 37