1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Broadcom Ltd. 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9/ { 10 compatible = "brcm,bcm6858", "brcm,bcmbca"; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 interrupt-parent = <&gic>; 15 16 cpus { 17 #address-cells = <2>; 18 #size-cells = <0>; 19 20 B53_0: cpu@0 { 21 compatible = "brcm,brahma-b53"; 22 device_type = "cpu"; 23 reg = <0x0 0x0>; 24 next-level-cache = <&L2_0>; 25 enable-method = "psci"; 26 }; 27 28 B53_1: cpu@1 { 29 compatible = "brcm,brahma-b53"; 30 device_type = "cpu"; 31 reg = <0x0 0x1>; 32 next-level-cache = <&L2_0>; 33 enable-method = "psci"; 34 }; 35 36 B53_2: cpu@2 { 37 compatible = "brcm,brahma-b53"; 38 device_type = "cpu"; 39 reg = <0x0 0x2>; 40 next-level-cache = <&L2_0>; 41 enable-method = "psci"; 42 }; 43 44 B53_3: cpu@3 { 45 compatible = "brcm,brahma-b53"; 46 device_type = "cpu"; 47 reg = <0x0 0x3>; 48 next-level-cache = <&L2_0>; 49 enable-method = "psci"; 50 }; 51 L2_0: l2-cache0 { 52 compatible = "cache"; 53 cache-level = <2>; 54 }; 55 }; 56 57 timer { 58 compatible = "arm,armv8-timer"; 59 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 60 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 61 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 62 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 63 }; 64 65 pmu: pmu { 66 compatible = "arm,armv8-pmuv3"; 67 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 71 interrupt-affinity = <&B53_0>, <&B53_1>, 72 <&B53_2>, <&B53_3>; 73 }; 74 75 clocks: clocks { 76 periph_clk:periph-clk { 77 compatible = "fixed-clock"; 78 #clock-cells = <0>; 79 clock-frequency = <200000000>; 80 }; 81 82 hsspi_pll: hsspi-pll { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 clock-frequency = <400000000>; 86 }; 87 }; 88 89 psci { 90 compatible = "arm,psci-0.2"; 91 method = "smc"; 92 }; 93 94 axi@81000000 { 95 compatible = "simple-bus"; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges = <0x0 0x0 0x81000000 0x8000>; 99 100 gic: interrupt-controller@1000 { 101 compatible = "arm,gic-400"; 102 #interrupt-cells = <3>; 103 interrupt-controller; 104 reg = <0x1000 0x1000>, /* GICD */ 105 <0x2000 0x2000>, /* GICC */ 106 <0x4000 0x2000>, /* GICH */ 107 <0x6000 0x2000>; /* GICV */ 108 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 109 IRQ_TYPE_LEVEL_HIGH)>; 110 }; 111 }; 112 113 bus@ff800000 { 114 compatible = "simple-bus"; 115 #address-cells = <1>; 116 #size-cells = <1>; 117 ranges = <0x0 0x0 0xff800000 0x62000>; 118 119 twd: timer-mfd@400 { 120 compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; 121 reg = <0x400 0x4c>; 122 ranges = <0x0 0x400 0x4c>; 123 124 #address-cells = <1>; 125 #size-cells = <1>; 126 127 timer@0 { 128 compatible = "brcm,bcm63138-timer"; 129 reg = <0x0 0x28>; 130 }; 131 132 watchdog@28 { 133 compatible = "brcm,bcm6345-wdt"; 134 reg = <0x28 0x8>; 135 }; 136 }; 137 138 uart0: serial@640 { 139 compatible = "brcm,bcm6345-uart"; 140 reg = <0x640 0x18>; 141 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&periph_clk>; 143 clock-names = "refclk"; 144 status = "disabled"; 145 }; 146 147 hsspi: spi@1000 { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0"; 151 reg = <0x1000 0x600>; 152 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&hsspi_pll &hsspi_pll>; 154 clock-names = "hsspi", "pll"; 155 num-cs = <8>; 156 status = "disabled"; 157 }; 158 }; 159}; 160