1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Broadcom Ltd. 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9/ { 10 compatible = "brcm,bcm63146", "brcm,bcmbca"; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 interrupt-parent = <&gic>; 15 16 cpus { 17 #address-cells = <2>; 18 #size-cells = <0>; 19 20 B53_0: cpu@0 { 21 compatible = "brcm,brahma-b53"; 22 device_type = "cpu"; 23 reg = <0x0 0x0>; 24 next-level-cache = <&L2_0>; 25 enable-method = "psci"; 26 }; 27 28 B53_1: cpu@1 { 29 compatible = "brcm,brahma-b53"; 30 device_type = "cpu"; 31 reg = <0x0 0x1>; 32 next-level-cache = <&L2_0>; 33 enable-method = "psci"; 34 }; 35 36 L2_0: l2-cache0 { 37 compatible = "cache"; 38 }; 39 }; 40 41 timer { 42 compatible = "arm,armv8-timer"; 43 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 44 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 45 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 46 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 47 }; 48 49 pmu: pmu { 50 compatible = "arm,cortex-a53-pmu"; 51 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 53 interrupt-affinity = <&B53_0>, <&B53_1>; 54 }; 55 56 clocks: clocks { 57 periph_clk: periph-clk { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <200000000>; 61 }; 62 uart_clk: uart-clk { 63 compatible = "fixed-factor-clock"; 64 #clock-cells = <0>; 65 clocks = <&periph_clk>; 66 clock-div = <4>; 67 clock-mult = <1>; 68 }; 69 }; 70 71 psci { 72 compatible = "arm,psci-0.2"; 73 method = "smc"; 74 }; 75 76 axi@81000000 { 77 compatible = "simple-bus"; 78 #address-cells = <1>; 79 #size-cells = <1>; 80 ranges = <0x0 0x0 0x81000000 0x8000>; 81 82 gic: interrupt-controller@1000 { 83 compatible = "arm,gic-400"; 84 #interrupt-cells = <3>; 85 interrupt-controller; 86 reg = <0x1000 0x1000>, 87 <0x2000 0x2000>, 88 <0x4000 0x2000>, 89 <0x6000 0x2000>; 90 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 91 IRQ_TYPE_LEVEL_HIGH)>; 92 }; 93 }; 94 95 bus@ff800000 { 96 compatible = "simple-bus"; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 ranges = <0x0 0x0 0xff800000 0x800000>; 100 101 uart0: serial@12000 { 102 compatible = "arm,pl011", "arm,primecell"; 103 reg = <0x12000 0x1000>; 104 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 105 clocks = <&uart_clk>, <&uart_clk>; 106 clock-names = "uartclk", "apb_pclk"; 107 status = "disabled"; 108 }; 109 }; 110}; 111