1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 3#include <dt-bindings/interrupt-controller/irq.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/phy/phy.h> 6#include <dt-bindings/soc/bcm-pmb.h> 7 8/dts-v1/; 9 10/ { 11 interrupt-parent = <&gic>; 12 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 aliases { 17 serial0 = &uart0; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 device_type = "cpu"; 30 compatible = "brcm,brahma-b53"; 31 reg = <0x0>; 32 enable-method = "spin-table"; 33 cpu-release-addr = <0x0 0xfff8>; 34 next-level-cache = <&l2>; 35 }; 36 37 cpu1: cpu@1 { 38 device_type = "cpu"; 39 compatible = "brcm,brahma-b53"; 40 reg = <0x1>; 41 enable-method = "spin-table"; 42 cpu-release-addr = <0x0 0xfff8>; 43 next-level-cache = <&l2>; 44 }; 45 46 cpu2: cpu@2 { 47 device_type = "cpu"; 48 compatible = "brcm,brahma-b53"; 49 reg = <0x2>; 50 enable-method = "spin-table"; 51 cpu-release-addr = <0x0 0xfff8>; 52 next-level-cache = <&l2>; 53 }; 54 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "brcm,brahma-b53"; 58 reg = <0x3>; 59 enable-method = "spin-table"; 60 cpu-release-addr = <0x0 0xfff8>; 61 next-level-cache = <&l2>; 62 }; 63 64 l2: l2-cache0 { 65 compatible = "cache"; 66 cache-level = <2>; 67 }; 68 }; 69 70 axi@81000000 { 71 compatible = "simple-bus"; 72 #address-cells = <1>; 73 #size-cells = <1>; 74 ranges = <0x00 0x00 0x81000000 0x4000>; 75 76 gic: interrupt-controller@1000 { 77 compatible = "arm,gic-400"; 78 #interrupt-cells = <3>; 79 #address-cells = <0>; 80 interrupt-controller; 81 reg = <0x1000 0x1000>, 82 <0x2000 0x2000>; 83 }; 84 }; 85 86 timer { 87 compatible = "arm,armv8-timer"; 88 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 89 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 90 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 91 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 92 }; 93 94 pmu { 95 compatible = "arm,cortex-a53-pmu"; 96 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 100 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 101 }; 102 103 clocks { 104 periph_clk: periph_clk { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <50000000>; 108 clock-output-names = "periph"; 109 }; 110 111 hsspi_pll: hsspi-pll { 112 compatible = "fixed-clock"; 113 #clock-cells = <0>; 114 clock-frequency = <400000000>; 115 }; 116 }; 117 118 soc { 119 compatible = "simple-bus"; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges = <0x00 0x00 0x80000000 0x281000>; 123 124 enet: ethernet@2000 { 125 compatible = "brcm,bcm4908-enet"; 126 reg = <0x2000 0x1000>; 127 128 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 130 interrupt-names = "rx", "tx"; 131 }; 132 133 usb_phy: usb-phy@c200 { 134 compatible = "brcm,bcm4908-usb-phy"; 135 reg = <0xc200 0x100>; 136 reg-names = "ctrl"; 137 power-domains = <&pmb BCM_PMB_HOST_USB>; 138 dr_mode = "host"; 139 brcm,has-xhci; 140 brcm,has-eohci; 141 #phy-cells = <1>; 142 status = "disabled"; 143 }; 144 145 ehci: usb@c300 { 146 compatible = "generic-ehci"; 147 reg = <0xc300 0x100>; 148 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 149 phys = <&usb_phy PHY_TYPE_USB2>; 150 status = "disabled"; 151 152 #address-cells = <1>; 153 #size-cells = <0>; 154 155 ehci_port1: port@1 { 156 reg = <1>; 157 #trigger-source-cells = <0>; 158 }; 159 160 ehci_port2: port@2 { 161 reg = <2>; 162 #trigger-source-cells = <0>; 163 }; 164 }; 165 166 ohci: usb@c400 { 167 compatible = "generic-ohci"; 168 reg = <0xc400 0x100>; 169 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 170 phys = <&usb_phy PHY_TYPE_USB2>; 171 status = "disabled"; 172 173 #address-cells = <1>; 174 #size-cells = <0>; 175 176 ohci_port1: port@1 { 177 reg = <1>; 178 #trigger-source-cells = <0>; 179 }; 180 181 ohci_port2: port@2 { 182 reg = <2>; 183 #trigger-source-cells = <0>; 184 }; 185 }; 186 187 xhci: usb@d000 { 188 compatible = "generic-xhci"; 189 reg = <0xd000 0x8c8>; 190 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 191 phys = <&usb_phy PHY_TYPE_USB3>; 192 status = "disabled"; 193 194 #address-cells = <1>; 195 #size-cells = <0>; 196 197 xhci_port1: port@1 { 198 reg = <1>; 199 #trigger-source-cells = <0>; 200 }; 201 202 xhci_port2: port@2 { 203 reg = <2>; 204 #trigger-source-cells = <0>; 205 }; 206 }; 207 208 bus@80000 { 209 compatible = "simple-bus"; 210 #size-cells = <1>; 211 #address-cells = <1>; 212 ranges = <0 0x80000 0x50000>; 213 214 ethernet-switch@0 { 215 compatible = "brcm,bcm4908-switch"; 216 reg = <0x0 0x40000>, 217 <0x40000 0x110>, 218 <0x40340 0x30>, 219 <0x40380 0x30>, 220 <0x40600 0x34>, 221 <0x40800 0x208>; 222 reg-names = "core", "reg", "intrl2_0", 223 "intrl2_1", "fcb", "acb"; 224 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 226 brcm,num-gphy = <5>; 227 brcm,num-rgmii-ports = <2>; 228 229 #address-cells = <1>; 230 #size-cells = <0>; 231 232 ports: ports { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 236 port@0 { 237 reg = <0>; 238 phy-mode = "internal"; 239 phy-handle = <&phy8>; 240 }; 241 242 port@1 { 243 reg = <1>; 244 phy-mode = "internal"; 245 phy-handle = <&phy9>; 246 }; 247 248 port@2 { 249 reg = <2>; 250 phy-mode = "internal"; 251 phy-handle = <&phy10>; 252 }; 253 254 port@3 { 255 reg = <3>; 256 phy-mode = "internal"; 257 phy-handle = <&phy11>; 258 }; 259 260 port@8 { 261 reg = <8>; 262 phy-mode = "internal"; 263 ethernet = <&enet>; 264 265 fixed-link { 266 speed = <1000>; 267 full-duplex; 268 }; 269 }; 270 }; 271 }; 272 273 mdio: mdio@405c0 { 274 compatible = "brcm,unimac-mdio"; 275 reg = <0x405c0 0x8>; 276 reg-names = "mdio"; 277 #size-cells = <0>; 278 #address-cells = <1>; 279 280 phy8: ethernet-phy@8 { 281 reg = <8>; 282 }; 283 284 phy9: ethernet-phy@9 { 285 reg = <9>; 286 }; 287 288 phy10: ethernet-phy@a { 289 reg = <10>; 290 }; 291 292 phy11: ethernet-phy@b { 293 reg = <11>; 294 }; 295 296 phy12: ethernet-phy@c { 297 reg = <12>; 298 }; 299 }; 300 }; 301 302 procmon: bus@280000 { 303 compatible = "simple-bus"; 304 reg = <0x280000 0x1000>; 305 ranges; 306 307 #address-cells = <1>; 308 #size-cells = <1>; 309 310 pmb: power-controller@2800c0 { 311 compatible = "brcm,bcm4908-pmb"; 312 reg = <0x2800c0 0x40>; 313 #power-domain-cells = <1>; 314 }; 315 }; 316 }; 317 318 bus@ff800000 { 319 compatible = "simple-bus"; 320 #address-cells = <1>; 321 #size-cells = <1>; 322 ranges = <0x00 0x00 0xff800000 0x3000>; 323 324 twd: timer-mfd@400 { 325 compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; 326 reg = <0x400 0x4c>; 327 ranges = <0x0 0x400 0x4c>; 328 329 #address-cells = <1>; 330 #size-cells = <1>; 331 332 timer@0 { 333 compatible = "brcm,bcm63138-timer"; 334 reg = <0x0 0x28>; 335 }; 336 337 watchdog@28 { 338 compatible = "brcm,bcm6345-wdt"; 339 reg = <0x28 0x8>; 340 }; 341 }; 342 343 gpio0: gpio-controller@500 { 344 compatible = "brcm,bcm6345-gpio"; 345 reg-names = "dirout", "dat"; 346 reg = <0x500 0x28>, <0x528 0x28>; 347 348 #gpio-cells = <2>; 349 gpio-controller; 350 }; 351 352 pinctrl@560 { 353 compatible = "brcm,bcm4908-pinctrl"; 354 reg = <0x560 0x10>; 355 356 pins_led_0_a: led_0-a-pins { 357 function = "led_0"; 358 groups = "led_0_grp_a"; 359 }; 360 361 pins_led_1_a: led_1-a-pins { 362 function = "led_1"; 363 groups = "led_1_grp_a"; 364 }; 365 366 pins_led_2_a: led_2-a-pins { 367 function = "led_2"; 368 groups = "led_2_grp_a"; 369 }; 370 371 pins_led_3_a: led_3-a-pins { 372 function = "led_3"; 373 groups = "led_3_grp_a"; 374 }; 375 376 pins_led_4_a: led_4-a-pins { 377 function = "led_4"; 378 groups = "led_4_grp_a"; 379 }; 380 381 pins_led_5_a: led_5-a-pins { 382 function = "led_5"; 383 groups = "led_5_grp_a"; 384 }; 385 386 pins_led_6_a: led_6-a-pins { 387 function = "led_6"; 388 groups = "led_6_grp_a"; 389 }; 390 391 pins_led_7_a: led_7-a-pins { 392 function = "led_7"; 393 groups = "led_7_grp_a"; 394 }; 395 396 pins_led_8_a: led_8-a-pins { 397 function = "led_8"; 398 groups = "led_8_grp_a"; 399 }; 400 401 pins_led_9_a: led_9-a-pins { 402 function = "led_9"; 403 groups = "led_9_grp_a"; 404 }; 405 406 pins_led_10_a: led_10-a-pins { 407 function = "led_10"; 408 groups = "led_10_grp_a"; 409 }; 410 411 pins_led_11_a: led_11-a-pins { 412 function = "led_11"; 413 groups = "led_11_grp_a"; 414 }; 415 416 pins_led_12_a: led_12-a-pins { 417 function = "led_12"; 418 groups = "led_12_grp_a"; 419 }; 420 421 pins_led_13_a: led_13-a-pins { 422 function = "led_13"; 423 groups = "led_13_grp_a"; 424 }; 425 426 pins_led_14_a: led_14-a-pins { 427 function = "led_14"; 428 groups = "led_14_grp_a"; 429 }; 430 431 pins_led_15_a: led_15-a-pins { 432 function = "led_15"; 433 groups = "led_15_grp_a"; 434 }; 435 436 pins_led_16_a: led_16-a-pins { 437 function = "led_16"; 438 groups = "led_16_grp_a"; 439 }; 440 441 pins_led_17_a: led_17-a-pins { 442 function = "led_17"; 443 groups = "led_17_grp_a"; 444 }; 445 446 pins_led_18_a: led_18-a-pins { 447 function = "led_18"; 448 groups = "led_18_grp_a"; 449 }; 450 451 pins_led_19_a: led_19-a-pins { 452 function = "led_19"; 453 groups = "led_19_grp_a"; 454 }; 455 456 pins_led_20_a: led_20-a-pins { 457 function = "led_20"; 458 groups = "led_20_grp_a"; 459 }; 460 461 pins_led_21_a: led_21-a-pins { 462 function = "led_21"; 463 groups = "led_21_grp_a"; 464 }; 465 466 pins_led_22_a: led_22-a-pins { 467 function = "led_22"; 468 groups = "led_22_grp_a"; 469 }; 470 471 pins_led_23_a: led_23-a-pins { 472 function = "led_23"; 473 groups = "led_23_grp_a"; 474 }; 475 476 pins_led_24_a: led_24-a-pins { 477 function = "led_24"; 478 groups = "led_24_grp_a"; 479 }; 480 481 pins_led_25_a: led_25-a-pins { 482 function = "led_25"; 483 groups = "led_25_grp_a"; 484 }; 485 486 pins_led_26_a: led_26-a-pins { 487 function = "led_26"; 488 groups = "led_26_grp_a"; 489 }; 490 491 pins_led_27_a: led_27-a-pins { 492 function = "led_27"; 493 groups = "led_27_grp_a"; 494 }; 495 496 pins_led_28_a: led_28-a-pins { 497 function = "led_28"; 498 groups = "led_28_grp_a"; 499 }; 500 501 pins_led_29_a: led_29-a-pins { 502 function = "led_29"; 503 groups = "led_29_grp_a"; 504 }; 505 506 pins_led_30_a: led_30-a-pins { 507 function = "led_30"; 508 groups = "led_30_grp_a"; 509 }; 510 511 pins_led_31_a: led_31-a-pins { 512 function = "led_31"; 513 groups = "led_31_grp_a"; 514 }; 515 516 pins_hs_uart: hs_uart-pins { 517 function = "hs_uart"; 518 groups = "hs_uart_grp"; 519 }; 520 521 pins_i2c_a: i2c-a-pins { 522 function = "i2c"; 523 groups = "i2c_grp_a"; 524 }; 525 526 pins_i2c_b: i2c-b-pins { 527 function = "i2c"; 528 groups = "i2c_grp_b"; 529 }; 530 531 pins_i2s: i2s-pins { 532 function = "i2s"; 533 groups = "i2s_grp"; 534 }; 535 536 pins_nand_ctrl: nand_ctrl-pins { 537 function = "nand_ctrl"; 538 groups = "nand_ctrl_grp"; 539 }; 540 541 pins_nand_data: nand_data-pins { 542 function = "nand_data"; 543 groups = "nand_data_grp"; 544 }; 545 546 pins_emmc_ctrl: emmc_ctrl-pins { 547 function = "emmc_ctrl"; 548 groups = "emmc_ctrl_grp"; 549 }; 550 551 pins_usb0_pwr: usb0_pwr-pins { 552 function = "usb0_pwr"; 553 groups = "usb0_pwr_grp"; 554 }; 555 556 pins_usb1_pwr: usb1_pwr-pins { 557 function = "usb1_pwr"; 558 groups = "usb1_pwr_grp"; 559 }; 560 }; 561 562 uart0: serial@640 { 563 compatible = "brcm,bcm6345-uart"; 564 reg = <0x640 0x18>; 565 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&periph_clk>; 567 clock-names = "refclk"; 568 status = "okay"; 569 }; 570 571 leds: leds@800 { 572 compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds"; 573 reg = <0x800 0xdc>; 574 575 #address-cells = <1>; 576 #size-cells = <0>; 577 }; 578 579 hsspi: spi@1000{ 580 #address-cells = <1>; 581 #size-cells = <0>; 582 compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0"; 583 reg = <0x1000 0x600>; 584 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&hsspi_pll &hsspi_pll>; 586 clock-names = "hsspi", "pll"; 587 num-cs = <8>; 588 status = "disabled"; 589 }; 590 591 nand-controller@1800 { 592 #address-cells = <1>; 593 #size-cells = <0>; 594 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; 595 reg = <0x1800 0x600>, <0x2000 0x10>; 596 reg-names = "nand", "nand-int-base"; 597 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 598 interrupt-names = "nand_ctlrdy"; 599 status = "okay"; 600 601 nandcs: nand@0 { 602 compatible = "brcm,nandcs"; 603 reg = <0>; 604 }; 605 }; 606 607 i2c@2100 { 608 compatible = "brcm,brcmper-i2c"; 609 reg = <0x2100 0x58>; 610 clock-frequency = <97500>; 611 pinctrl-names = "default"; 612 pinctrl-0 = <&pins_i2c_a>; 613 status = "disabled"; 614 }; 615 616 misc@2600 { 617 compatible = "brcm,misc", "simple-mfd"; 618 reg = <0x2600 0xe4>; 619 620 #address-cells = <1>; 621 #size-cells = <1>; 622 ranges = <0x00 0x2600 0xe4>; 623 624 reset-controller@2644 { 625 compatible = "brcm,bcm4908-misc-pcie-reset"; 626 reg = <0x44 0x04>; 627 #reset-cells = <1>; 628 }; 629 }; 630 }; 631 632 reboot { 633 compatible = "syscon-reboot"; 634 regmap = <&twd>; 635 offset = <0x34>; 636 mask = <1>; 637 }; 638}; 639