1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 3#include <dt-bindings/interrupt-controller/irq.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/phy/phy.h> 6#include <dt-bindings/soc/bcm-pmb.h> 7 8/dts-v1/; 9 10/ { 11 interrupt-parent = <&gic>; 12 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 aliases { 17 serial0 = &uart0; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 device_type = "cpu"; 30 compatible = "brcm,brahma-b53"; 31 reg = <0x0>; 32 next-level-cache = <&l2>; 33 }; 34 35 cpu1: cpu@1 { 36 device_type = "cpu"; 37 compatible = "brcm,brahma-b53"; 38 reg = <0x1>; 39 enable-method = "spin-table"; 40 cpu-release-addr = <0x0 0xfff8>; 41 next-level-cache = <&l2>; 42 }; 43 44 cpu2: cpu@2 { 45 device_type = "cpu"; 46 compatible = "brcm,brahma-b53"; 47 reg = <0x2>; 48 enable-method = "spin-table"; 49 cpu-release-addr = <0x0 0xfff8>; 50 next-level-cache = <&l2>; 51 }; 52 53 cpu3: cpu@3 { 54 device_type = "cpu"; 55 compatible = "brcm,brahma-b53"; 56 reg = <0x3>; 57 enable-method = "spin-table"; 58 cpu-release-addr = <0x0 0xfff8>; 59 next-level-cache = <&l2>; 60 }; 61 62 l2: l2-cache0 { 63 compatible = "cache"; 64 }; 65 }; 66 67 axi@81000000 { 68 compatible = "simple-bus"; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges = <0x00 0x00 0x81000000 0x4000>; 72 73 gic: interrupt-controller@1000 { 74 compatible = "arm,gic-400"; 75 #interrupt-cells = <3>; 76 #address-cells = <0>; 77 interrupt-controller; 78 reg = <0x1000 0x1000>, 79 <0x2000 0x2000>; 80 }; 81 }; 82 83 timer { 84 compatible = "arm,armv8-timer"; 85 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 86 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 87 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 88 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 89 }; 90 91 pmu { 92 compatible = "arm,cortex-a53-pmu"; 93 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 97 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 98 }; 99 100 clocks { 101 periph_clk: periph_clk { 102 compatible = "fixed-clock"; 103 #clock-cells = <0>; 104 clock-frequency = <50000000>; 105 clock-output-names = "periph"; 106 }; 107 }; 108 109 soc { 110 compatible = "simple-bus"; 111 #address-cells = <1>; 112 #size-cells = <1>; 113 ranges = <0x00 0x00 0x80000000 0x281000>; 114 115 enet: ethernet@2000 { 116 compatible = "brcm,bcm4908-enet"; 117 reg = <0x2000 0x1000>; 118 119 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 121 interrupt-names = "rx", "tx"; 122 }; 123 124 usb_phy: usb-phy@c200 { 125 compatible = "brcm,bcm4908-usb-phy"; 126 reg = <0xc200 0x100>; 127 reg-names = "ctrl"; 128 power-domains = <&pmb BCM_PMB_HOST_USB>; 129 dr_mode = "host"; 130 brcm,has-xhci; 131 brcm,has-eohci; 132 #phy-cells = <1>; 133 status = "disabled"; 134 }; 135 136 ehci: usb@c300 { 137 compatible = "generic-ehci"; 138 reg = <0xc300 0x100>; 139 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 140 phys = <&usb_phy PHY_TYPE_USB2>; 141 status = "disabled"; 142 }; 143 144 ohci: usb@c400 { 145 compatible = "generic-ohci"; 146 reg = <0xc400 0x100>; 147 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 148 phys = <&usb_phy PHY_TYPE_USB2>; 149 status = "disabled"; 150 }; 151 152 xhci: usb@d000 { 153 compatible = "generic-xhci"; 154 reg = <0xd000 0x8c8>; 155 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 156 phys = <&usb_phy PHY_TYPE_USB3>; 157 status = "disabled"; 158 }; 159 160 bus@80000 { 161 compatible = "simple-bus"; 162 #size-cells = <1>; 163 #address-cells = <1>; 164 ranges = <0 0x80000 0x50000>; 165 166 ethernet-switch@0 { 167 compatible = "brcm,bcm4908-switch"; 168 reg = <0x0 0x40000>, 169 <0x40000 0x110>, 170 <0x40340 0x30>, 171 <0x40380 0x30>, 172 <0x40600 0x34>, 173 <0x40800 0x208>; 174 reg-names = "core", "reg", "intrl2_0", 175 "intrl2_1", "fcb", "acb"; 176 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 178 brcm,num-gphy = <5>; 179 brcm,num-rgmii-ports = <2>; 180 181 #address-cells = <1>; 182 #size-cells = <0>; 183 184 ports: ports { 185 #address-cells = <1>; 186 #size-cells = <0>; 187 188 port@0 { 189 reg = <0>; 190 phy-mode = "internal"; 191 phy-handle = <&phy8>; 192 }; 193 194 port@1 { 195 reg = <1>; 196 phy-mode = "internal"; 197 phy-handle = <&phy9>; 198 }; 199 200 port@2 { 201 reg = <2>; 202 phy-mode = "internal"; 203 phy-handle = <&phy10>; 204 }; 205 206 port@3 { 207 reg = <3>; 208 phy-mode = "internal"; 209 phy-handle = <&phy11>; 210 }; 211 212 port@8 { 213 reg = <8>; 214 phy-mode = "internal"; 215 ethernet = <&enet>; 216 217 fixed-link { 218 speed = <1000>; 219 full-duplex; 220 }; 221 }; 222 }; 223 }; 224 225 mdio: mdio@405c0 { 226 compatible = "brcm,unimac-mdio"; 227 reg = <0x405c0 0x8>; 228 reg-names = "mdio"; 229 #size-cells = <0>; 230 #address-cells = <1>; 231 232 phy8: ethernet-phy@8 { 233 reg = <8>; 234 }; 235 236 phy9: ethernet-phy@9 { 237 reg = <9>; 238 }; 239 240 phy10: ethernet-phy@a { 241 reg = <10>; 242 }; 243 244 phy11: ethernet-phy@b { 245 reg = <11>; 246 }; 247 248 phy12: ethernet-phy@c { 249 reg = <12>; 250 }; 251 }; 252 }; 253 254 procmon: syscon@280000 { 255 compatible = "simple-bus"; 256 reg = <0x280000 0x1000>; 257 ranges; 258 259 #address-cells = <1>; 260 #size-cells = <1>; 261 262 pmb: power-controller@2800c0 { 263 compatible = "brcm,bcm4908-pmb"; 264 reg = <0x2800c0 0x40>; 265 #power-domain-cells = <1>; 266 }; 267 }; 268 }; 269 270 bus@ff800000 { 271 compatible = "simple-bus"; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 ranges = <0x00 0x00 0xff800000 0x3000>; 275 276 twd: timer-mfd@400 { 277 compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; 278 reg = <0x400 0x4c>; 279 ranges = <0x0 0x400 0x4c>; 280 281 #address-cells = <1>; 282 #size-cells = <1>; 283 284 watchdog@28 { 285 compatible = "brcm,bcm6345-wdt"; 286 reg = <0x28 0x8>; 287 }; 288 }; 289 290 gpio0: gpio-controller@500 { 291 compatible = "brcm,bcm6345-gpio"; 292 reg-names = "dirout", "dat"; 293 reg = <0x500 0x28>, <0x528 0x28>; 294 295 #gpio-cells = <2>; 296 gpio-controller; 297 }; 298 299 pinctrl@560 { 300 compatible = "brcm,bcm4908-pinctrl"; 301 reg = <0x560 0x10>; 302 303 pins_led_0_a: led_0-a-pins { 304 function = "led_0"; 305 groups = "led_0_grp_a"; 306 }; 307 308 pins_led_1_a: led_1-a-pins { 309 function = "led_1"; 310 groups = "led_1_grp_a"; 311 }; 312 313 pins_led_2_a: led_2-a-pins { 314 function = "led_2"; 315 groups = "led_2_grp_a"; 316 }; 317 318 pins_led_3_a: led_3-a-pins { 319 function = "led_3"; 320 groups = "led_3_grp_a"; 321 }; 322 323 pins_led_4_a: led_4-a-pins { 324 function = "led_4"; 325 groups = "led_4_grp_a"; 326 }; 327 328 pins_led_5_a: led_5-a-pins { 329 function = "led_5"; 330 groups = "led_5_grp_a"; 331 }; 332 333 pins_led_6_a: led_6-a-pins { 334 function = "led_6"; 335 groups = "led_6_grp_a"; 336 }; 337 338 pins_led_7_a: led_7-a-pins { 339 function = "led_7"; 340 groups = "led_7_grp_a"; 341 }; 342 343 pins_led_8_a: led_8-a-pins { 344 function = "led_8"; 345 groups = "led_8_grp_a"; 346 }; 347 348 pins_led_9_a: led_9-a-pins { 349 function = "led_9"; 350 groups = "led_9_grp_a"; 351 }; 352 353 pins_led_21_a: led_21-a-pins { 354 function = "led_21"; 355 groups = "led_21_grp_a"; 356 }; 357 358 pins_led_22_a: led_22-a-pins { 359 function = "led_22"; 360 groups = "led_22_grp_a"; 361 }; 362 363 pins_led_26_a: led_26-a-pins { 364 function = "led_26"; 365 groups = "led_26_grp_a"; 366 }; 367 368 pins_led_27_a: led_27-a-pins { 369 function = "led_27"; 370 groups = "led_27_grp_a"; 371 }; 372 373 pins_led_28_a: led_28-a-pins { 374 function = "led_28"; 375 groups = "led_28_grp_a"; 376 }; 377 378 pins_led_29_a: led_29-a-pins { 379 function = "led_29"; 380 groups = "led_29_grp_a"; 381 }; 382 383 pins_led_30_a: led_30-a-pins { 384 function = "led_30"; 385 groups = "led_30_grp_a"; 386 }; 387 388 pins_hs_uart: hs_uart-pins { 389 function = "hs_uart"; 390 groups = "hs_uart_grp"; 391 }; 392 393 pins_i2c_a: i2c-a-pins { 394 function = "i2c"; 395 groups = "i2c_grp_a"; 396 }; 397 398 pins_i2c_b: i2c-b-pins { 399 function = "i2c"; 400 groups = "i2c_grp_b"; 401 }; 402 403 pins_i2s: i2s-pins { 404 function = "i2s"; 405 groups = "i2s_grp"; 406 }; 407 408 pins_nand_ctrl: nand_ctrl-pins { 409 function = "nand_ctrl"; 410 groups = "nand_ctrl_grp"; 411 }; 412 413 pins_nand_data: nand_data-pins { 414 function = "nand_data"; 415 groups = "nand_data_grp"; 416 }; 417 418 pins_emmc_ctrl: emmc_ctrl-pins { 419 function = "emmc_ctrl"; 420 groups = "emmc_ctrl_grp"; 421 }; 422 423 pins_usb0_pwr: usb0_pwr-pins { 424 function = "usb0_pwr"; 425 groups = "usb0_pwr_grp"; 426 }; 427 428 pins_usb1_pwr: usb1_pwr-pins { 429 function = "usb1_pwr"; 430 groups = "usb1_pwr_grp"; 431 }; 432 }; 433 434 uart0: serial@640 { 435 compatible = "brcm,bcm6345-uart"; 436 reg = <0x640 0x18>; 437 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&periph_clk>; 439 clock-names = "refclk"; 440 status = "okay"; 441 }; 442 443 nand-controller@1800 { 444 #address-cells = <1>; 445 #size-cells = <0>; 446 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; 447 reg = <0x1800 0x600>, <0x2000 0x10>; 448 reg-names = "nand", "nand-int-base"; 449 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 450 interrupt-names = "nand"; 451 status = "okay"; 452 453 nandcs: nand@0 { 454 compatible = "brcm,nandcs"; 455 reg = <0>; 456 }; 457 }; 458 459 i2c@2100 { 460 compatible = "brcm,brcmper-i2c"; 461 reg = <0x2100 0x58>; 462 clock-frequency = <97500>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&pins_i2c_a>; 465 status = "disabled"; 466 }; 467 468 misc@2600 { 469 compatible = "brcm,misc", "simple-mfd"; 470 reg = <0x2600 0xe4>; 471 472 #address-cells = <1>; 473 #size-cells = <1>; 474 ranges = <0x00 0x2600 0xe4>; 475 476 reset-controller@2644 { 477 compatible = "brcm,bcm4908-misc-pcie-reset"; 478 reg = <0x44 0x04>; 479 #reset-cells = <1>; 480 }; 481 }; 482 }; 483 484 reboot { 485 compatible = "syscon-reboot"; 486 regmap = <&twd>; 487 offset = <0x34>; 488 mask = <1>; 489 }; 490}; 491