xref: /freebsd/sys/contrib/device-tree/src/arm64/broadcom/bcm4908/bcm4908.dtsi (revision 5def4c47d4bd90b209b9b4a4ba9faec15846d8fd) 
1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3#include <dt-bindings/interrupt-controller/irq.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5
6/dts-v1/;
7
8/ {
9	interrupt-parent = <&gic>;
10
11	#address-cells = <2>;
12	#size-cells = <2>;
13
14	aliases {
15		serial0 = &uart0;
16	};
17
18	chosen {
19		stdout-path = "serial0:115200n8";
20	};
21
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25
26		cpu0: cpu@0 {
27			device_type = "cpu";
28			compatible = "brcm,brahma-b53";
29			reg = <0x0>;
30			next-level-cache = <&l2>;
31		};
32
33		cpu1: cpu@1 {
34			device_type = "cpu";
35			compatible = "brcm,brahma-b53";
36			reg = <0x1>;
37			enable-method = "spin-table";
38			cpu-release-addr = <0x0 0xfff8>;
39			next-level-cache = <&l2>;
40		};
41
42		cpu2: cpu@2 {
43			device_type = "cpu";
44			compatible = "brcm,brahma-b53";
45			reg = <0x2>;
46			enable-method = "spin-table";
47			cpu-release-addr = <0x0 0xfff8>;
48			next-level-cache = <&l2>;
49		};
50
51		cpu3: cpu@3 {
52			device_type = "cpu";
53			compatible = "brcm,brahma-b53";
54			reg = <0x3>;
55			enable-method = "spin-table";
56			cpu-release-addr = <0x0 0xfff8>;
57			next-level-cache = <&l2>;
58		};
59
60		l2: l2-cache0 {
61			compatible = "cache";
62		};
63	};
64
65	axi@81000000 {
66		compatible = "simple-bus";
67		#address-cells = <1>;
68		#size-cells = <1>;
69		ranges = <0x00 0x00 0x81000000 0x4000>;
70
71		gic: interrupt-controller@1000 {
72			compatible = "arm,gic-400";
73			#interrupt-cells = <3>;
74			#address-cells = <0>;
75			interrupt-controller;
76			reg = <0x1000 0x1000>,
77			      <0x2000 0x2000>;
78		};
79	};
80
81	timer {
82		compatible = "arm,armv8-timer";
83		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
84			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
85			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
86			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
87	};
88
89	pmu {
90		compatible = "arm,cortex-a53-pmu";
91		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
92			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
93			     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
94			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
95		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
96	};
97
98	clocks {
99		periph_clk: periph_clk {
100			compatible = "fixed-clock";
101			#clock-cells = <0>;
102			clock-frequency = <50000000>;
103			clock-output-names = "periph";
104		};
105	};
106
107	soc {
108		compatible = "simple-bus";
109		#address-cells = <1>;
110		#size-cells = <1>;
111		ranges = <0x00 0x00 0x80000000 0x281000>;
112
113		usb@c300 {
114			compatible = "generic-ehci";
115			reg = <0xc300 0x100>;
116			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
117			status = "disabled";
118		};
119
120		usb@c400 {
121			compatible = "generic-ohci";
122			reg = <0xc400 0x100>;
123			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
124			status = "disabled";
125		};
126
127		usb@d000 {
128			compatible = "generic-xhci";
129			reg = <0xd000 0x8c8>;
130			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
131			status = "disabled";
132		};
133
134		ethernet-switch@80000 {
135			compatible = "simple-bus";
136			#size-cells = <1>;
137			#address-cells = <1>;
138			ranges = <0 0x80000 0x50000>;
139
140			ethernet-switch@0 {
141				compatible = "brcm,bcm4908-switch";
142				reg = <0x0 0x40000>,
143				      <0x40000 0x110>,
144				      <0x40340 0x30>,
145				      <0x40380 0x30>,
146				      <0x40600 0x34>,
147				      <0x40800 0x208>;
148				reg-names = "core", "reg", "intrl2_0",
149					    "intrl2_1", "fcb", "acb";
150				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
151					     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
152				brcm,num-gphy = <5>;
153				brcm,num-rgmii-ports = <2>;
154
155				#address-cells = <1>;
156				#size-cells = <0>;
157
158				ports: ports {
159					#address-cells = <1>;
160					#size-cells = <0>;
161
162					port@0 {
163						reg = <0>;
164						phy-mode = "internal";
165						phy-handle = <&phy8>;
166					};
167
168					port@1 {
169						reg = <1>;
170						phy-mode = "internal";
171						phy-handle = <&phy9>;
172					};
173
174					port@2 {
175						reg = <2>;
176						phy-mode = "internal";
177						phy-handle = <&phy10>;
178					};
179
180					port@3 {
181						reg = <3>;
182						phy-mode = "internal";
183						phy-handle = <&phy11>;
184					};
185				};
186			};
187
188			mdio: mdio@405c0 {
189				compatible = "brcm,unimac-mdio";
190				reg = <0x405c0 0x8>;
191				reg-names = "mdio";
192				#size-cells = <0>;
193				#address-cells = <1>;
194
195				phy8: ethernet-phy@8 {
196					reg = <8>;
197				};
198
199				phy9: ethernet-phy@9 {
200					reg = <9>;
201				};
202
203				phy10: ethernet-phy@a {
204					reg = <10>;
205				};
206
207				phy11: ethernet-phy@b {
208					reg = <11>;
209				};
210
211				phy12: ethernet-phy@c {
212					reg = <12>;
213				};
214			};
215		};
216
217		procmon: syscon@280000 {
218			compatible = "simple-bus";
219			reg = <0x280000 0x1000>;
220			ranges;
221
222			#address-cells = <1>;
223			#size-cells = <1>;
224
225			power-controller@2800c0 {
226				compatible = "brcm,bcm4908-pmb";
227				reg = <0x2800c0 0x40>;
228				#power-domain-cells = <1>;
229			};
230		};
231	};
232
233	bus@ff800000 {
234		compatible = "simple-bus";
235		#address-cells = <1>;
236		#size-cells = <1>;
237		ranges = <0x00 0x00 0xff800000 0x3000>;
238
239		timer: timer@400 {
240			compatible = "brcm,bcm6328-timer", "syscon";
241			reg = <0x400 0x3c>;
242		};
243
244		gpio0: gpio-controller@500 {
245			compatible = "brcm,bcm6345-gpio";
246			reg-names = "dirout", "dat";
247			reg = <0x500 0x28>, <0x528 0x28>;
248
249			#gpio-cells = <2>;
250			gpio-controller;
251		};
252
253		uart0: serial@640 {
254			compatible = "brcm,bcm6345-uart";
255			reg = <0x640 0x18>;
256			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
257			clocks = <&periph_clk>;
258			clock-names = "periph";
259			status = "okay";
260		};
261
262		nand@1800 {
263			#address-cells = <1>;
264			#size-cells = <0>;
265			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
266			reg = <0x1800 0x600>, <0x2000 0x10>;
267			reg-names = "nand", "nand-int-base";
268			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
269			interrupt-names = "nand";
270			status = "okay";
271
272			nandcs: nandcs@0 {
273				compatible = "brcm,nandcs";
274				reg = <0>;
275			};
276		};
277
278		misc@2600 {
279			compatible = "brcm,misc", "simple-mfd";
280			reg = <0x2600 0xe4>;
281
282			#address-cells = <1>;
283			#size-cells = <1>;
284			ranges = <0x00 0x2600 0xe4>;
285
286			reset-controller@2644 {
287				compatible = "brcm,bcm4908-misc-pcie-reset";
288				reg = <0x44 0x04>;
289				#reset-cells = <1>;
290			};
291		};
292
293		reboot {
294			compatible = "syscon-reboot";
295			regmap = <&timer>;
296			offset = <0x34>;
297			mask = <1>;
298		};
299	};
300};
301