1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 3#include <dt-bindings/interrupt-controller/irq.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/phy/phy.h> 6#include <dt-bindings/soc/bcm-pmb.h> 7 8/dts-v1/; 9 10/ { 11 interrupt-parent = <&gic>; 12 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 aliases { 17 serial0 = &uart0; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 device_type = "cpu"; 30 compatible = "brcm,brahma-b53"; 31 reg = <0x0>; 32 enable-method = "spin-table"; 33 cpu-release-addr = <0x0 0xfff8>; 34 next-level-cache = <&l2>; 35 }; 36 37 cpu1: cpu@1 { 38 device_type = "cpu"; 39 compatible = "brcm,brahma-b53"; 40 reg = <0x1>; 41 enable-method = "spin-table"; 42 cpu-release-addr = <0x0 0xfff8>; 43 next-level-cache = <&l2>; 44 }; 45 46 cpu2: cpu@2 { 47 device_type = "cpu"; 48 compatible = "brcm,brahma-b53"; 49 reg = <0x2>; 50 enable-method = "spin-table"; 51 cpu-release-addr = <0x0 0xfff8>; 52 next-level-cache = <&l2>; 53 }; 54 55 cpu3: cpu@3 { 56 device_type = "cpu"; 57 compatible = "brcm,brahma-b53"; 58 reg = <0x3>; 59 enable-method = "spin-table"; 60 cpu-release-addr = <0x0 0xfff8>; 61 next-level-cache = <&l2>; 62 }; 63 64 l2: l2-cache0 { 65 compatible = "cache"; 66 }; 67 }; 68 69 axi@81000000 { 70 compatible = "simple-bus"; 71 #address-cells = <1>; 72 #size-cells = <1>; 73 ranges = <0x00 0x00 0x81000000 0x4000>; 74 75 gic: interrupt-controller@1000 { 76 compatible = "arm,gic-400"; 77 #interrupt-cells = <3>; 78 #address-cells = <0>; 79 interrupt-controller; 80 reg = <0x1000 0x1000>, 81 <0x2000 0x2000>; 82 }; 83 }; 84 85 timer { 86 compatible = "arm,armv8-timer"; 87 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 88 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 89 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 90 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 91 }; 92 93 pmu { 94 compatible = "arm,cortex-a53-pmu"; 95 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 99 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 100 }; 101 102 clocks { 103 periph_clk: periph_clk { 104 compatible = "fixed-clock"; 105 #clock-cells = <0>; 106 clock-frequency = <50000000>; 107 clock-output-names = "periph"; 108 }; 109 }; 110 111 soc { 112 compatible = "simple-bus"; 113 #address-cells = <1>; 114 #size-cells = <1>; 115 ranges = <0x00 0x00 0x80000000 0x281000>; 116 117 enet: ethernet@2000 { 118 compatible = "brcm,bcm4908-enet"; 119 reg = <0x2000 0x1000>; 120 121 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 123 interrupt-names = "rx", "tx"; 124 }; 125 126 usb_phy: usb-phy@c200 { 127 compatible = "brcm,bcm4908-usb-phy"; 128 reg = <0xc200 0x100>; 129 reg-names = "ctrl"; 130 power-domains = <&pmb BCM_PMB_HOST_USB>; 131 dr_mode = "host"; 132 brcm,has-xhci; 133 brcm,has-eohci; 134 #phy-cells = <1>; 135 status = "disabled"; 136 }; 137 138 ehci: usb@c300 { 139 compatible = "generic-ehci"; 140 reg = <0xc300 0x100>; 141 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 142 phys = <&usb_phy PHY_TYPE_USB2>; 143 status = "disabled"; 144 }; 145 146 ohci: usb@c400 { 147 compatible = "generic-ohci"; 148 reg = <0xc400 0x100>; 149 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 150 phys = <&usb_phy PHY_TYPE_USB2>; 151 status = "disabled"; 152 }; 153 154 xhci: usb@d000 { 155 compatible = "generic-xhci"; 156 reg = <0xd000 0x8c8>; 157 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 158 phys = <&usb_phy PHY_TYPE_USB3>; 159 status = "disabled"; 160 }; 161 162 bus@80000 { 163 compatible = "simple-bus"; 164 #size-cells = <1>; 165 #address-cells = <1>; 166 ranges = <0 0x80000 0x50000>; 167 168 ethernet-switch@0 { 169 compatible = "brcm,bcm4908-switch"; 170 reg = <0x0 0x40000>, 171 <0x40000 0x110>, 172 <0x40340 0x30>, 173 <0x40380 0x30>, 174 <0x40600 0x34>, 175 <0x40800 0x208>; 176 reg-names = "core", "reg", "intrl2_0", 177 "intrl2_1", "fcb", "acb"; 178 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 180 brcm,num-gphy = <5>; 181 brcm,num-rgmii-ports = <2>; 182 183 #address-cells = <1>; 184 #size-cells = <0>; 185 186 ports: ports { 187 #address-cells = <1>; 188 #size-cells = <0>; 189 190 port@0 { 191 reg = <0>; 192 phy-mode = "internal"; 193 phy-handle = <&phy8>; 194 }; 195 196 port@1 { 197 reg = <1>; 198 phy-mode = "internal"; 199 phy-handle = <&phy9>; 200 }; 201 202 port@2 { 203 reg = <2>; 204 phy-mode = "internal"; 205 phy-handle = <&phy10>; 206 }; 207 208 port@3 { 209 reg = <3>; 210 phy-mode = "internal"; 211 phy-handle = <&phy11>; 212 }; 213 214 port@8 { 215 reg = <8>; 216 phy-mode = "internal"; 217 ethernet = <&enet>; 218 219 fixed-link { 220 speed = <1000>; 221 full-duplex; 222 }; 223 }; 224 }; 225 }; 226 227 mdio: mdio@405c0 { 228 compatible = "brcm,unimac-mdio"; 229 reg = <0x405c0 0x8>; 230 reg-names = "mdio"; 231 #size-cells = <0>; 232 #address-cells = <1>; 233 234 phy8: ethernet-phy@8 { 235 reg = <8>; 236 }; 237 238 phy9: ethernet-phy@9 { 239 reg = <9>; 240 }; 241 242 phy10: ethernet-phy@a { 243 reg = <10>; 244 }; 245 246 phy11: ethernet-phy@b { 247 reg = <11>; 248 }; 249 250 phy12: ethernet-phy@c { 251 reg = <12>; 252 }; 253 }; 254 }; 255 256 procmon: syscon@280000 { 257 compatible = "simple-bus"; 258 reg = <0x280000 0x1000>; 259 ranges; 260 261 #address-cells = <1>; 262 #size-cells = <1>; 263 264 pmb: power-controller@2800c0 { 265 compatible = "brcm,bcm4908-pmb"; 266 reg = <0x2800c0 0x40>; 267 #power-domain-cells = <1>; 268 }; 269 }; 270 }; 271 272 bus@ff800000 { 273 compatible = "simple-bus"; 274 #address-cells = <1>; 275 #size-cells = <1>; 276 ranges = <0x00 0x00 0xff800000 0x3000>; 277 278 twd: timer-mfd@400 { 279 compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; 280 reg = <0x400 0x4c>; 281 ranges = <0x0 0x400 0x4c>; 282 283 #address-cells = <1>; 284 #size-cells = <1>; 285 286 watchdog@28 { 287 compatible = "brcm,bcm6345-wdt"; 288 reg = <0x28 0x8>; 289 }; 290 }; 291 292 gpio0: gpio-controller@500 { 293 compatible = "brcm,bcm6345-gpio"; 294 reg-names = "dirout", "dat"; 295 reg = <0x500 0x28>, <0x528 0x28>; 296 297 #gpio-cells = <2>; 298 gpio-controller; 299 }; 300 301 pinctrl@560 { 302 compatible = "brcm,bcm4908-pinctrl"; 303 reg = <0x560 0x10>; 304 305 pins_led_0_a: led_0-a-pins { 306 function = "led_0"; 307 groups = "led_0_grp_a"; 308 }; 309 310 pins_led_1_a: led_1-a-pins { 311 function = "led_1"; 312 groups = "led_1_grp_a"; 313 }; 314 315 pins_led_2_a: led_2-a-pins { 316 function = "led_2"; 317 groups = "led_2_grp_a"; 318 }; 319 320 pins_led_3_a: led_3-a-pins { 321 function = "led_3"; 322 groups = "led_3_grp_a"; 323 }; 324 325 pins_led_4_a: led_4-a-pins { 326 function = "led_4"; 327 groups = "led_4_grp_a"; 328 }; 329 330 pins_led_5_a: led_5-a-pins { 331 function = "led_5"; 332 groups = "led_5_grp_a"; 333 }; 334 335 pins_led_6_a: led_6-a-pins { 336 function = "led_6"; 337 groups = "led_6_grp_a"; 338 }; 339 340 pins_led_7_a: led_7-a-pins { 341 function = "led_7"; 342 groups = "led_7_grp_a"; 343 }; 344 345 pins_led_8_a: led_8-a-pins { 346 function = "led_8"; 347 groups = "led_8_grp_a"; 348 }; 349 350 pins_led_9_a: led_9-a-pins { 351 function = "led_9"; 352 groups = "led_9_grp_a"; 353 }; 354 355 pins_led_21_a: led_21-a-pins { 356 function = "led_21"; 357 groups = "led_21_grp_a"; 358 }; 359 360 pins_led_22_a: led_22-a-pins { 361 function = "led_22"; 362 groups = "led_22_grp_a"; 363 }; 364 365 pins_led_26_a: led_26-a-pins { 366 function = "led_26"; 367 groups = "led_26_grp_a"; 368 }; 369 370 pins_led_27_a: led_27-a-pins { 371 function = "led_27"; 372 groups = "led_27_grp_a"; 373 }; 374 375 pins_led_28_a: led_28-a-pins { 376 function = "led_28"; 377 groups = "led_28_grp_a"; 378 }; 379 380 pins_led_29_a: led_29-a-pins { 381 function = "led_29"; 382 groups = "led_29_grp_a"; 383 }; 384 385 pins_led_30_a: led_30-a-pins { 386 function = "led_30"; 387 groups = "led_30_grp_a"; 388 }; 389 390 pins_hs_uart: hs_uart-pins { 391 function = "hs_uart"; 392 groups = "hs_uart_grp"; 393 }; 394 395 pins_i2c_a: i2c-a-pins { 396 function = "i2c"; 397 groups = "i2c_grp_a"; 398 }; 399 400 pins_i2c_b: i2c-b-pins { 401 function = "i2c"; 402 groups = "i2c_grp_b"; 403 }; 404 405 pins_i2s: i2s-pins { 406 function = "i2s"; 407 groups = "i2s_grp"; 408 }; 409 410 pins_nand_ctrl: nand_ctrl-pins { 411 function = "nand_ctrl"; 412 groups = "nand_ctrl_grp"; 413 }; 414 415 pins_nand_data: nand_data-pins { 416 function = "nand_data"; 417 groups = "nand_data_grp"; 418 }; 419 420 pins_emmc_ctrl: emmc_ctrl-pins { 421 function = "emmc_ctrl"; 422 groups = "emmc_ctrl_grp"; 423 }; 424 425 pins_usb0_pwr: usb0_pwr-pins { 426 function = "usb0_pwr"; 427 groups = "usb0_pwr_grp"; 428 }; 429 430 pins_usb1_pwr: usb1_pwr-pins { 431 function = "usb1_pwr"; 432 groups = "usb1_pwr_grp"; 433 }; 434 }; 435 436 uart0: serial@640 { 437 compatible = "brcm,bcm6345-uart"; 438 reg = <0x640 0x18>; 439 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&periph_clk>; 441 clock-names = "refclk"; 442 status = "okay"; 443 }; 444 445 nand-controller@1800 { 446 #address-cells = <1>; 447 #size-cells = <0>; 448 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; 449 reg = <0x1800 0x600>, <0x2000 0x10>; 450 reg-names = "nand", "nand-int-base"; 451 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 452 interrupt-names = "nand"; 453 status = "okay"; 454 455 nandcs: nand@0 { 456 compatible = "brcm,nandcs"; 457 reg = <0>; 458 }; 459 }; 460 461 i2c@2100 { 462 compatible = "brcm,brcmper-i2c"; 463 reg = <0x2100 0x58>; 464 clock-frequency = <97500>; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&pins_i2c_a>; 467 status = "disabled"; 468 }; 469 470 misc@2600 { 471 compatible = "brcm,misc", "simple-mfd"; 472 reg = <0x2600 0xe4>; 473 474 #address-cells = <1>; 475 #size-cells = <1>; 476 ranges = <0x00 0x2600 0xe4>; 477 478 reset-controller@2644 { 479 compatible = "brcm,bcm4908-misc-pcie-reset"; 480 reg = <0x44 0x04>; 481 #reset-cells = <1>; 482 }; 483 }; 484 }; 485 486 reboot { 487 compatible = "syscon-reboot"; 488 regmap = <&twd>; 489 offset = <0x34>; 490 mask = <1>; 491 }; 492}; 493