1*2846c905SEmmanuel Vadot// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*2846c905SEmmanuel Vadot/dts-v1/; 3*2846c905SEmmanuel Vadot 4*2846c905SEmmanuel Vadot#include "bcm2712-rpi-5-b.dts" 5*2846c905SEmmanuel Vadot 6*2846c905SEmmanuel Vadot&gio_aon { 7*2846c905SEmmanuel Vadot brcm,gpio-bank-widths = <15 6>; 8*2846c905SEmmanuel Vadot 9*2846c905SEmmanuel Vadot gpio-line-names = 10*2846c905SEmmanuel Vadot "RP1_SDA", // AON_GPIO_00 11*2846c905SEmmanuel Vadot "RP1_SCL", // AON_GPIO_01 12*2846c905SEmmanuel Vadot "RP1_RUN", // AON_GPIO_02 13*2846c905SEmmanuel Vadot "SD_IOVDD_SEL", // AON_GPIO_03 14*2846c905SEmmanuel Vadot "SD_PWR_ON", // AON_GPIO_04 15*2846c905SEmmanuel Vadot "SD_CDET_N", // AON_GPIO_05 16*2846c905SEmmanuel Vadot "SD_FLG_N", // AON_GPIO_06 17*2846c905SEmmanuel Vadot "", // AON_GPIO_07 18*2846c905SEmmanuel Vadot "2712_WAKE", // AON_GPIO_08 19*2846c905SEmmanuel Vadot "2712_STAT_LED", // AON_GPIO_09 20*2846c905SEmmanuel Vadot "", // AON_GPIO_10 21*2846c905SEmmanuel Vadot "", // AON_GPIO_11 22*2846c905SEmmanuel Vadot "PMIC_INT", // AON_GPIO_12 23*2846c905SEmmanuel Vadot "UART_TX_FS", // AON_GPIO_13 24*2846c905SEmmanuel Vadot "UART_RX_FS", // AON_GPIO_14 25*2846c905SEmmanuel Vadot "", // AON_GPIO_15 26*2846c905SEmmanuel Vadot "", // AON_GPIO_16 27*2846c905SEmmanuel Vadot 28*2846c905SEmmanuel Vadot // Pad bank0 out to 32 entries 29*2846c905SEmmanuel Vadot "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", 30*2846c905SEmmanuel Vadot 31*2846c905SEmmanuel Vadot "HDMI0_SCL", // AON_SGPIO_00 32*2846c905SEmmanuel Vadot "HDMI0_SDA", // AON_SGPIO_01 33*2846c905SEmmanuel Vadot "HDMI1_SCL", // AON_SGPIO_02 34*2846c905SEmmanuel Vadot "HDMI1_SDA", // AON_SGPIO_03 35*2846c905SEmmanuel Vadot "PMIC_SCL", // AON_SGPIO_04 36*2846c905SEmmanuel Vadot "PMIC_SDA"; // AON_SGPIO_05 37*2846c905SEmmanuel Vadot}; 38