1/* 2 * ARM Juno Platform motherboard peripherals 3 * 4 * Copyright (c) 2013-2014 ARM Ltd 5 * 6 * This file is licensed under a dual GPLv2 or BSD license. 7 * 8 */ 9 10/ { 11 mb_clk24mhz: clk24mhz { 12 compatible = "fixed-clock"; 13 #clock-cells = <0>; 14 clock-frequency = <24000000>; 15 clock-output-names = "juno_mb:clk24mhz"; 16 }; 17 18 mb_clk25mhz: clk25mhz { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 clock-frequency = <25000000>; 22 clock-output-names = "juno_mb:clk25mhz"; 23 }; 24 25 v2m_refclk1mhz: refclk1mhz { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <1000000>; 29 clock-output-names = "juno_mb:refclk1mhz"; 30 }; 31 32 v2m_refclk32khz: refclk32khz { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32768>; 36 clock-output-names = "juno_mb:refclk32khz"; 37 }; 38 39 mb_fixed_3v3: mcc-sb-3v3 { 40 compatible = "regulator-fixed"; 41 regulator-name = "MCC_SB_3V3"; 42 regulator-min-microvolt = <3300000>; 43 regulator-max-microvolt = <3300000>; 44 regulator-always-on; 45 }; 46 47 gpio-keys { 48 compatible = "gpio-keys"; 49 50 power-button { 51 debounce-interval = <50>; 52 wakeup-source; 53 linux,code = <116>; 54 label = "POWER"; 55 gpios = <&iofpga_gpio0 0 0x4>; 56 }; 57 home-button { 58 debounce-interval = <50>; 59 wakeup-source; 60 linux,code = <102>; 61 label = "HOME"; 62 gpios = <&iofpga_gpio0 1 0x4>; 63 }; 64 rlock-button { 65 debounce-interval = <50>; 66 wakeup-source; 67 linux,code = <152>; 68 label = "RLOCK"; 69 gpios = <&iofpga_gpio0 2 0x4>; 70 }; 71 vol-up-button { 72 debounce-interval = <50>; 73 wakeup-source; 74 linux,code = <115>; 75 label = "VOL+"; 76 gpios = <&iofpga_gpio0 3 0x4>; 77 }; 78 vol-down-button { 79 debounce-interval = <50>; 80 wakeup-source; 81 linux,code = <114>; 82 label = "VOL-"; 83 gpios = <&iofpga_gpio0 4 0x4>; 84 }; 85 nmi-button { 86 debounce-interval = <50>; 87 wakeup-source; 88 linux,code = <99>; 89 label = "NMI"; 90 gpios = <&iofpga_gpio0 5 0x4>; 91 }; 92 }; 93 94 bus@8000000 { 95 compatible = "simple-bus"; 96 #address-cells = <2>; 97 #size-cells = <1>; 98 ranges = <0 0x8000000 0 0x8000000 0x18000000>; 99 100 motherboard-bus@8000000 { 101 compatible = "arm,vexpress,v2p-p1", "simple-bus"; 102 #address-cells = <2>; /* SMB chipselect number and offset */ 103 #size-cells = <1>; 104 ranges = <0 0 0 0x08000000 0x04000000>, 105 <1 0 0 0x14000000 0x04000000>, 106 <2 0 0 0x18000000 0x04000000>, 107 <3 0 0 0x1c000000 0x04000000>, 108 <4 0 0 0x0c000000 0x04000000>, 109 <5 0 0 0x10000000 0x04000000>; 110 arm,hbi = <0x252>; 111 arm,vexpress,site = <0>; 112 113 flash@0 { 114 /* 2 * 32MiB NOR Flash memory mounted on CS0 */ 115 compatible = "arm,vexpress-flash", "cfi-flash"; 116 reg = <0 0x00000000 0x04000000>; 117 bank-width = <4>; 118 /* 119 * Unfortunately, accessing the flash disturbs 120 * the CPU idle states (suspend) and CPU 121 * hotplug of the platform. For this reason, 122 * flash hardware access is disabled by default. 123 */ 124 status = "disabled"; 125 partitions { 126 compatible = "arm,arm-firmware-suite"; 127 }; 128 }; 129 130 ethernet@200000000 { 131 compatible = "smsc,lan9118", "smsc,lan9115"; 132 reg = <2 0x00000000 0x10000>; 133 interrupts = <3>; 134 phy-mode = "mii"; 135 reg-io-width = <4>; 136 smsc,irq-active-high; 137 smsc,irq-push-pull; 138 clocks = <&mb_clk25mhz>; 139 vdd33a-supply = <&mb_fixed_3v3>; 140 vddvario-supply = <&mb_fixed_3v3>; 141 }; 142 143 iofpga-bus@300000000 { 144 compatible = "simple-bus"; 145 #address-cells = <1>; 146 #size-cells = <1>; 147 ranges = <0 3 0 0x200000>; 148 149 v2m_sysctl: sysctl@20000 { 150 compatible = "arm,sp810", "arm,primecell"; 151 reg = <0x020000 0x1000>; 152 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>; 153 clock-names = "refclk", "timclk", "apb_pclk"; 154 #clock-cells = <1>; 155 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; 156 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; 157 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; 158 }; 159 160 apbregs@10000 { 161 compatible = "syscon", "simple-mfd"; 162 reg = <0x010000 0x1000>; 163 ranges = <0x0 0x10000 0x1000>; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 167 led@8,0 { 168 compatible = "register-bit-led"; 169 reg = <0x08 0x04>; 170 offset = <0x08>; 171 mask = <0x01>; 172 label = "vexpress:0"; 173 linux,default-trigger = "heartbeat"; 174 default-state = "on"; 175 }; 176 led@8,1 { 177 compatible = "register-bit-led"; 178 reg = <0x08 0x04>; 179 offset = <0x08>; 180 mask = <0x02>; 181 label = "vexpress:1"; 182 linux,default-trigger = "mmc0"; 183 default-state = "off"; 184 }; 185 led@8,2 { 186 compatible = "register-bit-led"; 187 reg = <0x08 0x04>; 188 offset = <0x08>; 189 mask = <0x04>; 190 label = "vexpress:2"; 191 linux,default-trigger = "cpu0"; 192 default-state = "off"; 193 }; 194 led@8,3 { 195 compatible = "register-bit-led"; 196 reg = <0x08 0x04>; 197 offset = <0x08>; 198 mask = <0x08>; 199 label = "vexpress:3"; 200 linux,default-trigger = "cpu1"; 201 default-state = "off"; 202 }; 203 led@8,4 { 204 compatible = "register-bit-led"; 205 reg = <0x08 0x04>; 206 offset = <0x08>; 207 mask = <0x10>; 208 label = "vexpress:4"; 209 linux,default-trigger = "cpu2"; 210 default-state = "off"; 211 }; 212 led@8,5 { 213 compatible = "register-bit-led"; 214 reg = <0x08 0x04>; 215 offset = <0x08>; 216 mask = <0x20>; 217 label = "vexpress:5"; 218 linux,default-trigger = "cpu3"; 219 default-state = "off"; 220 }; 221 led@8,6 { 222 compatible = "register-bit-led"; 223 reg = <0x08 0x04>; 224 offset = <0x08>; 225 mask = <0x40>; 226 label = "vexpress:6"; 227 default-state = "off"; 228 }; 229 led@8,7 { 230 compatible = "register-bit-led"; 231 reg = <0x08 0x04>; 232 offset = <0x08>; 233 mask = <0x80>; 234 label = "vexpress:7"; 235 default-state = "off"; 236 }; 237 }; 238 239 mmc@50000 { 240 compatible = "arm,pl180", "arm,primecell"; 241 reg = <0x050000 0x1000>; 242 interrupts = <5>; 243 /* cd-gpios = <&v2m_mmc_gpios 0 0>; 244 wp-gpios = <&v2m_mmc_gpios 1 0>; */ 245 max-frequency = <12000000>; 246 vmmc-supply = <&mb_fixed_3v3>; 247 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 248 clock-names = "mclk", "apb_pclk"; 249 }; 250 251 kmi@60000 { 252 compatible = "arm,pl050", "arm,primecell"; 253 reg = <0x060000 0x1000>; 254 interrupts = <8>; 255 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 256 clock-names = "KMIREFCLK", "apb_pclk"; 257 }; 258 259 kmi@70000 { 260 compatible = "arm,pl050", "arm,primecell"; 261 reg = <0x070000 0x1000>; 262 interrupts = <8>; 263 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 264 clock-names = "KMIREFCLK", "apb_pclk"; 265 }; 266 267 watchdog@f0000 { 268 compatible = "arm,sp805", "arm,primecell"; 269 reg = <0x0f0000 0x10000>; 270 interrupts = <7>; 271 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; 272 clock-names = "wdog_clk", "apb_pclk"; 273 }; 274 275 v2m_timer01: timer@110000 { 276 compatible = "arm,sp804", "arm,primecell"; 277 reg = <0x110000 0x10000>; 278 interrupts = <9>; 279 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>; 280 clock-names = "timclken1", "timclken2", "apb_pclk"; 281 }; 282 283 v2m_timer23: timer@120000 { 284 compatible = "arm,sp804", "arm,primecell"; 285 reg = <0x120000 0x10000>; 286 interrupts = <9>; 287 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>; 288 clock-names = "timclken1", "timclken2", "apb_pclk"; 289 }; 290 291 rtc@170000 { 292 compatible = "arm,pl031", "arm,primecell"; 293 reg = <0x170000 0x10000>; 294 interrupts = <0>; 295 clocks = <&soc_smc50mhz>; 296 clock-names = "apb_pclk"; 297 }; 298 299 iofpga_gpio0: gpio@1d0000 { 300 compatible = "arm,pl061", "arm,primecell"; 301 reg = <0x1d0000 0x1000>; 302 interrupts = <6>; 303 clocks = <&soc_smc50mhz>; 304 clock-names = "apb_pclk"; 305 gpio-controller; 306 #gpio-cells = <2>; 307 interrupt-controller; 308 #interrupt-cells = <2>; 309 }; 310 }; 311 }; 312 }; 313}; 314