1// SPDX-License-Identifier: GPL-2.0 2#include "juno-clocks.dtsi" 3#include "juno-motherboard.dtsi" 4 5/ { 6 /* 7 * Devices shared by all Juno boards 8 */ 9 10 memtimer: timer@2a810000 { 11 compatible = "arm,armv7-timer-mem"; 12 reg = <0x0 0x2a810000 0x0 0x10000>; 13 clock-frequency = <50000000>; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 ranges = <0 0x0 0x2a820000 0x20000>; 17 status = "disabled"; 18 frame@2a830000 { 19 frame-number = <1>; 20 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 21 reg = <0x10000 0x10000>; 22 }; 23 }; 24 25 mailbox: mhu@2b1f0000 { 26 compatible = "arm,mhu", "arm,primecell"; 27 reg = <0x0 0x2b1f0000 0x0 0x1000>; 28 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 30 interrupt-names = "mhu_lpri_rx", 31 "mhu_hpri_rx"; 32 #mbox-cells = <1>; 33 clocks = <&soc_refclk100mhz>; 34 clock-names = "apb_pclk"; 35 }; 36 37 smmu_gpu: iommu@2b400000 { 38 compatible = "arm,mmu-400", "arm,smmu-v1"; 39 reg = <0x0 0x2b400000 0x0 0x10000>; 40 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 42 #iommu-cells = <1>; 43 #global-interrupts = <1>; 44 power-domains = <&scpi_devpd 1>; 45 dma-coherent; 46 status = "disabled"; 47 }; 48 49 smmu_pcie: iommu@2b500000 { 50 compatible = "arm,mmu-401", "arm,smmu-v1"; 51 reg = <0x0 0x2b500000 0x0 0x10000>; 52 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 54 #iommu-cells = <1>; 55 #global-interrupts = <1>; 56 dma-coherent; 57 status = "disabled"; 58 }; 59 60 smmu_etr: iommu@2b600000 { 61 compatible = "arm,mmu-401", "arm,smmu-v1"; 62 reg = <0x0 0x2b600000 0x0 0x10000>; 63 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 65 #iommu-cells = <1>; 66 #global-interrupts = <1>; 67 dma-coherent; 68 power-domains = <&scpi_devpd 0>; 69 }; 70 71 gic: interrupt-controller@2c010000 { 72 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 73 reg = <0x0 0x2c010000 0 0x1000>, 74 <0x0 0x2c02f000 0 0x2000>, 75 <0x0 0x2c04f000 0 0x2000>, 76 <0x0 0x2c06f000 0 0x2000>; 77 #address-cells = <1>; 78 #interrupt-cells = <3>; 79 #size-cells = <1>; 80 interrupt-controller; 81 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 82 ranges = <0 0 0x2c1c0000 0x40000>; 83 84 v2m_0: v2m@0 { 85 compatible = "arm,gic-v2m-frame"; 86 msi-controller; 87 reg = <0 0x10000>; 88 }; 89 90 v2m@10000 { 91 compatible = "arm,gic-v2m-frame"; 92 msi-controller; 93 reg = <0x10000 0x10000>; 94 }; 95 96 v2m@20000 { 97 compatible = "arm,gic-v2m-frame"; 98 msi-controller; 99 reg = <0x20000 0x10000>; 100 }; 101 102 v2m@30000 { 103 compatible = "arm,gic-v2m-frame"; 104 msi-controller; 105 reg = <0x30000 0x10000>; 106 }; 107 }; 108 109 timer { 110 compatible = "arm,armv8-timer"; 111 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 112 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 113 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 114 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 115 }; 116 117 /* 118 * Juno TRMs specify the size for these coresight components as 64K. 119 * The actual size is just 4K though 64K is reserved. Access to the 120 * unmapped reserved region results in a DECERR response. 121 */ 122 etf@20010000 { /* etf0 */ 123 compatible = "arm,coresight-tmc", "arm,primecell"; 124 reg = <0 0x20010000 0 0x1000>; 125 126 clocks = <&soc_smc50mhz>; 127 clock-names = "apb_pclk"; 128 power-domains = <&scpi_devpd 0>; 129 130 in-ports { 131 port { 132 etf0_in_port: endpoint { 133 remote-endpoint = <&main_funnel_out_port>; 134 }; 135 }; 136 }; 137 138 out-ports { 139 port { 140 etf0_out_port: endpoint { 141 }; 142 }; 143 }; 144 }; 145 146 tpiu@20030000 { 147 compatible = "arm,coresight-tpiu", "arm,primecell"; 148 reg = <0 0x20030000 0 0x1000>; 149 150 clocks = <&soc_smc50mhz>; 151 clock-names = "apb_pclk"; 152 power-domains = <&scpi_devpd 0>; 153 in-ports { 154 port { 155 tpiu_in_port: endpoint { 156 remote-endpoint = <&replicator_out_port0>; 157 }; 158 }; 159 }; 160 }; 161 162 /* main funnel on Juno r0, cssys0 funnel on Juno r1/r2 as per TRM*/ 163 main_funnel: funnel@20040000 { 164 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 165 reg = <0 0x20040000 0 0x1000>; 166 167 clocks = <&soc_smc50mhz>; 168 clock-names = "apb_pclk"; 169 power-domains = <&scpi_devpd 0>; 170 171 out-ports { 172 port { 173 main_funnel_out_port: endpoint { 174 remote-endpoint = <&etf0_in_port>; 175 }; 176 }; 177 }; 178 179 main_funnel_in_ports: in-ports { 180 #address-cells = <1>; 181 #size-cells = <0>; 182 183 port@0 { 184 reg = <0>; 185 main_funnel_in_port0: endpoint { 186 remote-endpoint = <&cluster0_funnel_out_port>; 187 }; 188 }; 189 190 port@1 { 191 reg = <1>; 192 main_funnel_in_port1: endpoint { 193 remote-endpoint = <&cluster1_funnel_out_port>; 194 }; 195 }; 196 }; 197 }; 198 199 etr@20070000 { 200 compatible = "arm,coresight-tmc", "arm,primecell"; 201 reg = <0 0x20070000 0 0x1000>; 202 iommus = <&smmu_etr 0>; 203 204 clocks = <&soc_smc50mhz>; 205 clock-names = "apb_pclk"; 206 power-domains = <&scpi_devpd 0>; 207 arm,scatter-gather; 208 in-ports { 209 port { 210 etr_in_port: endpoint { 211 remote-endpoint = <&replicator_out_port1>; 212 }; 213 }; 214 }; 215 }; 216 217 stm@20100000 { 218 compatible = "arm,coresight-stm", "arm,primecell"; 219 reg = <0 0x20100000 0 0x1000>, 220 <0 0x28000000 0 0x1000000>; 221 reg-names = "stm-base", "stm-stimulus-base"; 222 223 clocks = <&soc_smc50mhz>; 224 clock-names = "apb_pclk"; 225 power-domains = <&scpi_devpd 0>; 226 out-ports { 227 port { 228 stm_out_port: endpoint { 229 }; 230 }; 231 }; 232 }; 233 234 replicator@20120000 { 235 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 236 reg = <0 0x20120000 0 0x1000>; 237 238 clocks = <&soc_smc50mhz>; 239 clock-names = "apb_pclk"; 240 power-domains = <&scpi_devpd 0>; 241 242 out-ports { 243 #address-cells = <1>; 244 #size-cells = <0>; 245 246 /* replicator output ports */ 247 port@0 { 248 reg = <0>; 249 replicator_out_port0: endpoint { 250 remote-endpoint = <&tpiu_in_port>; 251 }; 252 }; 253 254 port@1 { 255 reg = <1>; 256 replicator_out_port1: endpoint { 257 remote-endpoint = <&etr_in_port>; 258 }; 259 }; 260 }; 261 in-ports { 262 port { 263 replicator_in_port0: endpoint { 264 }; 265 }; 266 }; 267 }; 268 269 cpu_debug0: cpu-debug@22010000 { 270 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 271 reg = <0x0 0x22010000 0x0 0x1000>; 272 273 clocks = <&soc_smc50mhz>; 274 clock-names = "apb_pclk"; 275 power-domains = <&scpi_devpd 0>; 276 }; 277 278 etm0: etm@22040000 { 279 compatible = "arm,coresight-etm4x", "arm,primecell"; 280 reg = <0 0x22040000 0 0x1000>; 281 282 clocks = <&soc_smc50mhz>; 283 clock-names = "apb_pclk"; 284 power-domains = <&scpi_devpd 0>; 285 out-ports { 286 port { 287 cluster0_etm0_out_port: endpoint { 288 remote-endpoint = <&cluster0_funnel_in_port0>; 289 }; 290 }; 291 }; 292 }; 293 294 funnel@220c0000 { /* cluster0 funnel */ 295 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 296 reg = <0 0x220c0000 0 0x1000>; 297 298 clocks = <&soc_smc50mhz>; 299 clock-names = "apb_pclk"; 300 power-domains = <&scpi_devpd 0>; 301 out-ports { 302 port { 303 cluster0_funnel_out_port: endpoint { 304 remote-endpoint = <&main_funnel_in_port0>; 305 }; 306 }; 307 }; 308 309 in-ports { 310 #address-cells = <1>; 311 #size-cells = <0>; 312 313 port@0 { 314 reg = <0>; 315 cluster0_funnel_in_port0: endpoint { 316 remote-endpoint = <&cluster0_etm0_out_port>; 317 }; 318 }; 319 320 port@1 { 321 reg = <1>; 322 cluster0_funnel_in_port1: endpoint { 323 remote-endpoint = <&cluster0_etm1_out_port>; 324 }; 325 }; 326 }; 327 }; 328 329 cpu_debug1: cpu-debug@22110000 { 330 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 331 reg = <0x0 0x22110000 0x0 0x1000>; 332 333 clocks = <&soc_smc50mhz>; 334 clock-names = "apb_pclk"; 335 power-domains = <&scpi_devpd 0>; 336 }; 337 338 etm1: etm@22140000 { 339 compatible = "arm,coresight-etm4x", "arm,primecell"; 340 reg = <0 0x22140000 0 0x1000>; 341 342 clocks = <&soc_smc50mhz>; 343 clock-names = "apb_pclk"; 344 power-domains = <&scpi_devpd 0>; 345 out-ports { 346 port { 347 cluster0_etm1_out_port: endpoint { 348 remote-endpoint = <&cluster0_funnel_in_port1>; 349 }; 350 }; 351 }; 352 }; 353 354 cpu_debug2: cpu-debug@23010000 { 355 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 356 reg = <0x0 0x23010000 0x0 0x1000>; 357 358 clocks = <&soc_smc50mhz>; 359 clock-names = "apb_pclk"; 360 power-domains = <&scpi_devpd 0>; 361 }; 362 363 etm2: etm@23040000 { 364 compatible = "arm,coresight-etm4x", "arm,primecell"; 365 reg = <0 0x23040000 0 0x1000>; 366 367 clocks = <&soc_smc50mhz>; 368 clock-names = "apb_pclk"; 369 power-domains = <&scpi_devpd 0>; 370 out-ports { 371 port { 372 cluster1_etm0_out_port: endpoint { 373 remote-endpoint = <&cluster1_funnel_in_port0>; 374 }; 375 }; 376 }; 377 }; 378 379 funnel@230c0000 { /* cluster1 funnel */ 380 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 381 reg = <0 0x230c0000 0 0x1000>; 382 383 clocks = <&soc_smc50mhz>; 384 clock-names = "apb_pclk"; 385 power-domains = <&scpi_devpd 0>; 386 out-ports { 387 port { 388 cluster1_funnel_out_port: endpoint { 389 remote-endpoint = <&main_funnel_in_port1>; 390 }; 391 }; 392 }; 393 394 in-ports { 395 #address-cells = <1>; 396 #size-cells = <0>; 397 398 port@0 { 399 reg = <0>; 400 cluster1_funnel_in_port0: endpoint { 401 remote-endpoint = <&cluster1_etm0_out_port>; 402 }; 403 }; 404 405 port@1 { 406 reg = <1>; 407 cluster1_funnel_in_port1: endpoint { 408 remote-endpoint = <&cluster1_etm1_out_port>; 409 }; 410 }; 411 port@2 { 412 reg = <2>; 413 cluster1_funnel_in_port2: endpoint { 414 remote-endpoint = <&cluster1_etm2_out_port>; 415 }; 416 }; 417 port@3 { 418 reg = <3>; 419 cluster1_funnel_in_port3: endpoint { 420 remote-endpoint = <&cluster1_etm3_out_port>; 421 }; 422 }; 423 }; 424 }; 425 426 cpu_debug3: cpu-debug@23110000 { 427 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 428 reg = <0x0 0x23110000 0x0 0x1000>; 429 430 clocks = <&soc_smc50mhz>; 431 clock-names = "apb_pclk"; 432 power-domains = <&scpi_devpd 0>; 433 }; 434 435 etm3: etm@23140000 { 436 compatible = "arm,coresight-etm4x", "arm,primecell"; 437 reg = <0 0x23140000 0 0x1000>; 438 439 clocks = <&soc_smc50mhz>; 440 clock-names = "apb_pclk"; 441 power-domains = <&scpi_devpd 0>; 442 out-ports { 443 port { 444 cluster1_etm1_out_port: endpoint { 445 remote-endpoint = <&cluster1_funnel_in_port1>; 446 }; 447 }; 448 }; 449 }; 450 451 cpu_debug4: cpu-debug@23210000 { 452 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 453 reg = <0x0 0x23210000 0x0 0x1000>; 454 455 clocks = <&soc_smc50mhz>; 456 clock-names = "apb_pclk"; 457 power-domains = <&scpi_devpd 0>; 458 }; 459 460 etm4: etm@23240000 { 461 compatible = "arm,coresight-etm4x", "arm,primecell"; 462 reg = <0 0x23240000 0 0x1000>; 463 464 clocks = <&soc_smc50mhz>; 465 clock-names = "apb_pclk"; 466 power-domains = <&scpi_devpd 0>; 467 out-ports { 468 port { 469 cluster1_etm2_out_port: endpoint { 470 remote-endpoint = <&cluster1_funnel_in_port2>; 471 }; 472 }; 473 }; 474 }; 475 476 cpu_debug5: cpu-debug@23310000 { 477 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 478 reg = <0x0 0x23310000 0x0 0x1000>; 479 480 clocks = <&soc_smc50mhz>; 481 clock-names = "apb_pclk"; 482 power-domains = <&scpi_devpd 0>; 483 }; 484 485 etm5: etm@23340000 { 486 compatible = "arm,coresight-etm4x", "arm,primecell"; 487 reg = <0 0x23340000 0 0x1000>; 488 489 clocks = <&soc_smc50mhz>; 490 clock-names = "apb_pclk"; 491 power-domains = <&scpi_devpd 0>; 492 out-ports { 493 port { 494 cluster1_etm3_out_port: endpoint { 495 remote-endpoint = <&cluster1_funnel_in_port3>; 496 }; 497 }; 498 }; 499 }; 500 501 gpu: gpu@2d000000 { 502 compatible = "arm,juno-mali", "arm,mali-t624"; 503 reg = <0 0x2d000000 0 0x10000>; 504 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 507 interrupt-names = "job", "mmu", "gpu"; 508 clocks = <&scpi_dvfs 2>; 509 power-domains = <&scpi_devpd 1>; 510 dma-coherent; 511 /* The SMMU is only really of interest to bare-metal hypervisors */ 512 /* iommus = <&smmu_gpu 0>; */ 513 status = "disabled"; 514 }; 515 516 sram: sram@2e000000 { 517 compatible = "arm,juno-sram-ns", "mmio-sram"; 518 reg = <0x0 0x2e000000 0x0 0x8000>; 519 520 #address-cells = <1>; 521 #size-cells = <1>; 522 ranges = <0 0x0 0x2e000000 0x8000>; 523 524 cpu_scp_lpri: scp-sram@0 { 525 compatible = "arm,juno-scp-shmem"; 526 reg = <0x0 0x200>; 527 }; 528 529 cpu_scp_hpri: scp-sram@200 { 530 compatible = "arm,juno-scp-shmem"; 531 reg = <0x200 0x200>; 532 }; 533 }; 534 535 pcie_ctlr: pcie@40000000 { 536 compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic"; 537 device_type = "pci"; 538 reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */ 539 bus-range = <0 255>; 540 linux,pci-domain = <0>; 541 #address-cells = <3>; 542 #size-cells = <2>; 543 dma-coherent; 544 ranges = <0x01000000 0x00 0x00000000 0x00 0x5f800000 0x0 0x00800000>, 545 <0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>, 546 <0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>; 547 /* Standard AXI Translation entries as programmed by EDK2 */ 548 dma-ranges = <0x02000000 0x0 0x2c1c0000 0x0 0x2c1c0000 0x0 0x00040000>, 549 <0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x80000000>, 550 <0x43000000 0x8 0x00000000 0x8 0x00000000 0x2 0x00000000>; 551 #interrupt-cells = <1>; 552 interrupt-map-mask = <0 0 0 7>; 553 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 554 <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 555 <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 556 <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 557 msi-parent = <&v2m_0>; 558 status = "disabled"; 559 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */ 560 iommu-map = <0x0 &smmu_pcie 0x0 0x1>; 561 }; 562 563 scpi { 564 compatible = "arm,scpi"; 565 mboxes = <&mailbox 1>; 566 shmem = <&cpu_scp_hpri>; 567 568 clocks { 569 compatible = "arm,scpi-clocks"; 570 571 scpi_dvfs: scpi-dvfs { 572 compatible = "arm,scpi-dvfs-clocks"; 573 #clock-cells = <1>; 574 clock-indices = <0>, <1>, <2>; 575 clock-output-names = "atlclk", "aplclk","gpuclk"; 576 }; 577 scpi_clk: scpi-clk { 578 compatible = "arm,scpi-variable-clocks"; 579 #clock-cells = <1>; 580 clock-indices = <3>; 581 clock-output-names = "pxlclk"; 582 }; 583 }; 584 585 scpi_devpd: scpi-power-domains { 586 compatible = "arm,scpi-power-domains"; 587 num-domains = <2>; 588 #power-domain-cells = <1>; 589 }; 590 591 scpi_sensors0: sensors { 592 compatible = "arm,scpi-sensors"; 593 #thermal-sensor-cells = <1>; 594 }; 595 }; 596 597 thermal-zones { 598 pmic { 599 polling-delay = <1000>; 600 polling-delay-passive = <100>; 601 thermal-sensors = <&scpi_sensors0 0>; 602 }; 603 604 soc { 605 polling-delay = <1000>; 606 polling-delay-passive = <100>; 607 thermal-sensors = <&scpi_sensors0 3>; 608 }; 609 610 big_cluster_thermal_zone: big-cluster { 611 polling-delay = <1000>; 612 polling-delay-passive = <100>; 613 thermal-sensors = <&scpi_sensors0 21>; 614 status = "disabled"; 615 }; 616 617 little_cluster_thermal_zone: little-cluster { 618 polling-delay = <1000>; 619 polling-delay-passive = <100>; 620 thermal-sensors = <&scpi_sensors0 22>; 621 status = "disabled"; 622 }; 623 624 gpu0_thermal_zone: gpu0 { 625 polling-delay = <1000>; 626 polling-delay-passive = <100>; 627 thermal-sensors = <&scpi_sensors0 23>; 628 status = "disabled"; 629 }; 630 631 gpu1_thermal_zone: gpu1 { 632 polling-delay = <1000>; 633 polling-delay-passive = <100>; 634 thermal-sensors = <&scpi_sensors0 24>; 635 status = "disabled"; 636 }; 637 }; 638 639 smmu_dma: iommu@7fb00000 { 640 compatible = "arm,mmu-401", "arm,smmu-v1"; 641 reg = <0x0 0x7fb00000 0x0 0x10000>; 642 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 644 #iommu-cells = <1>; 645 #global-interrupts = <1>; 646 dma-coherent; 647 }; 648 649 smmu_hdlcd1: iommu@7fb10000 { 650 compatible = "arm,mmu-401", "arm,smmu-v1"; 651 reg = <0x0 0x7fb10000 0x0 0x10000>; 652 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 654 #iommu-cells = <1>; 655 #global-interrupts = <1>; 656 }; 657 658 smmu_hdlcd0: iommu@7fb20000 { 659 compatible = "arm,mmu-401", "arm,smmu-v1"; 660 reg = <0x0 0x7fb20000 0x0 0x10000>; 661 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 663 #iommu-cells = <1>; 664 #global-interrupts = <1>; 665 }; 666 667 smmu_usb: iommu@7fb30000 { 668 compatible = "arm,mmu-401", "arm,smmu-v1"; 669 reg = <0x0 0x7fb30000 0x0 0x10000>; 670 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 672 #iommu-cells = <1>; 673 #global-interrupts = <1>; 674 dma-coherent; 675 }; 676 677 dma@7ff00000 { 678 compatible = "arm,pl330", "arm,primecell"; 679 reg = <0x0 0x7ff00000 0 0x1000>; 680 #dma-cells = <1>; 681 #dma-channels = <8>; 682 #dma-requests = <32>; 683 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 692 iommus = <&smmu_dma 0>, 693 <&smmu_dma 1>, 694 <&smmu_dma 2>, 695 <&smmu_dma 3>, 696 <&smmu_dma 4>, 697 <&smmu_dma 5>, 698 <&smmu_dma 6>, 699 <&smmu_dma 7>, 700 <&smmu_dma 8>; 701 clocks = <&soc_faxiclk>; 702 clock-names = "apb_pclk"; 703 }; 704 705 hdlcd@7ff50000 { 706 compatible = "arm,hdlcd"; 707 reg = <0 0x7ff50000 0 0x1000>; 708 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 709 iommus = <&smmu_hdlcd1 0>; 710 clocks = <&scpi_clk 3>; 711 clock-names = "pxlclk"; 712 713 port { 714 hdlcd1_output: endpoint { 715 remote-endpoint = <&tda998x_1_input>; 716 }; 717 }; 718 }; 719 720 hdlcd@7ff60000 { 721 compatible = "arm,hdlcd"; 722 reg = <0 0x7ff60000 0 0x1000>; 723 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 724 iommus = <&smmu_hdlcd0 0>; 725 clocks = <&scpi_clk 3>; 726 clock-names = "pxlclk"; 727 728 port { 729 hdlcd0_output: endpoint { 730 remote-endpoint = <&tda998x_0_input>; 731 }; 732 }; 733 }; 734 735 soc_uart0: serial@7ff80000 { 736 compatible = "arm,pl011", "arm,primecell"; 737 reg = <0x0 0x7ff80000 0x0 0x1000>; 738 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&soc_uartclk>, <&soc_refclk100mhz>; 740 clock-names = "uartclk", "apb_pclk"; 741 }; 742 743 i2c@7ffa0000 { 744 compatible = "snps,designware-i2c"; 745 reg = <0x0 0x7ffa0000 0x0 0x1000>; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 749 clock-frequency = <400000>; 750 i2c-sda-hold-time-ns = <500>; 751 clocks = <&soc_smc50mhz>; 752 753 hdmi-transmitter@70 { 754 compatible = "nxp,tda998x"; 755 reg = <0x70>; 756 port { 757 tda998x_0_input: endpoint { 758 remote-endpoint = <&hdlcd0_output>; 759 }; 760 }; 761 }; 762 763 hdmi-transmitter@71 { 764 compatible = "nxp,tda998x"; 765 reg = <0x71>; 766 port { 767 tda998x_1_input: endpoint { 768 remote-endpoint = <&hdlcd1_output>; 769 }; 770 }; 771 }; 772 }; 773 774 usb@7ffb0000 { 775 compatible = "generic-ohci"; 776 reg = <0x0 0x7ffb0000 0x0 0x10000>; 777 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 778 iommus = <&smmu_usb 0>; 779 clocks = <&soc_usb48mhz>; 780 }; 781 782 usb@7ffc0000 { 783 compatible = "generic-ehci"; 784 reg = <0x0 0x7ffc0000 0x0 0x10000>; 785 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 786 iommus = <&smmu_usb 0>; 787 clocks = <&soc_usb48mhz>; 788 }; 789 790 memory-controller@7ffd0000 { 791 compatible = "arm,pl354", "arm,primecell"; 792 reg = <0 0x7ffd0000 0 0x1000>; 793 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&soc_smc50mhz>; 796 clock-names = "apb_pclk"; 797 }; 798 799 memory@80000000 { 800 device_type = "memory"; 801 /* last 16MB of the first memory area is reserved for secure world use by firmware */ 802 reg = <0x00000000 0x80000000 0x0 0x7f000000>, 803 <0x00000008 0x80000000 0x1 0x80000000>; 804 }; 805 806 bus@8000000 { 807 compatible = "simple-bus"; 808 #address-cells = <2>; 809 #size-cells = <1>; 810 ranges = <0 0 0 0x08000000 0x04000000>, 811 <1 0 0 0x14000000 0x04000000>, 812 <2 0 0 0x18000000 0x04000000>, 813 <3 0 0 0x1c000000 0x04000000>, 814 <4 0 0 0x0c000000 0x04000000>, 815 <5 0 0 0x10000000 0x04000000>; 816 817 #interrupt-cells = <1>; 818 interrupt-map-mask = <0 0 15>; 819 interrupt-map = <0 0 0 &gic 0 GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 820 <0 0 1 &gic 0 GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 821 <0 0 2 &gic 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 822 <0 0 3 &gic 0 GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 823 <0 0 4 &gic 0 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 824 <0 0 5 &gic 0 GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 825 <0 0 6 &gic 0 GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 826 <0 0 7 &gic 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 827 <0 0 8 &gic 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 828 <0 0 9 &gic 0 GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 829 <0 0 10 &gic 0 GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 830 <0 0 11 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 831 <0 0 12 &gic 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 832 }; 833 834 site2: tlx-bus@60000000 { 835 compatible = "simple-bus"; 836 #address-cells = <1>; 837 #size-cells = <1>; 838 ranges = <0 0 0x60000000 0x10000000>; 839 #interrupt-cells = <1>; 840 interrupt-map-mask = <0 0>; 841 interrupt-map = <0 0 &gic 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 842 }; 843}; 844