1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ARM Ltd. Fast Models 4 * 5 * Architecture Envelope Model (AEM) ARMv8-A 6 * ARMAEMv8AMPCT 7 * 8 * FVP Base RevC 9 */ 10 11/dts-v1/; 12 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14 15/memreserve/ 0x80000000 0x00010000; 16 17#include "rtsm_ve-motherboard.dtsi" 18#include "rtsm_ve-motherboard-rs2.dtsi" 19 20/ { 21 model = "FVP Base RevC"; 22 compatible = "arm,fvp-base-revc", "arm,vexpress"; 23 interrupt-parent = <&gic>; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 chosen { }; 28 29 aliases { 30 serial0 = &v2m_serial0; 31 serial1 = &v2m_serial1; 32 serial2 = &v2m_serial2; 33 serial3 = &v2m_serial3; 34 }; 35 36 psci { 37 compatible = "arm,psci-0.2"; 38 method = "smc"; 39 }; 40 41 cpus { 42 #address-cells = <2>; 43 #size-cells = <0>; 44 45 cpu0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,armv8"; 48 reg = <0x0 0x000>; 49 enable-method = "psci"; 50 i-cache-size = <0x8000>; 51 i-cache-line-size = <64>; 52 i-cache-sets = <256>; 53 d-cache-size = <0x8000>; 54 d-cache-line-size = <64>; 55 d-cache-sets = <256>; 56 next-level-cache = <&C0_L2>; 57 }; 58 cpu1: cpu@100 { 59 device_type = "cpu"; 60 compatible = "arm,armv8"; 61 reg = <0x0 0x100>; 62 enable-method = "psci"; 63 i-cache-size = <0x8000>; 64 i-cache-line-size = <64>; 65 i-cache-sets = <256>; 66 d-cache-size = <0x8000>; 67 d-cache-line-size = <64>; 68 d-cache-sets = <256>; 69 next-level-cache = <&C0_L2>; 70 }; 71 cpu2: cpu@200 { 72 device_type = "cpu"; 73 compatible = "arm,armv8"; 74 reg = <0x0 0x200>; 75 enable-method = "psci"; 76 i-cache-size = <0x8000>; 77 i-cache-line-size = <64>; 78 i-cache-sets = <256>; 79 d-cache-size = <0x8000>; 80 d-cache-line-size = <64>; 81 d-cache-sets = <256>; 82 next-level-cache = <&C0_L2>; 83 }; 84 cpu3: cpu@300 { 85 device_type = "cpu"; 86 compatible = "arm,armv8"; 87 reg = <0x0 0x300>; 88 enable-method = "psci"; 89 i-cache-size = <0x8000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <256>; 92 d-cache-size = <0x8000>; 93 d-cache-line-size = <64>; 94 d-cache-sets = <256>; 95 next-level-cache = <&C0_L2>; 96 }; 97 cpu4: cpu@10000 { 98 device_type = "cpu"; 99 compatible = "arm,armv8"; 100 reg = <0x0 0x10000>; 101 enable-method = "psci"; 102 i-cache-size = <0x8000>; 103 i-cache-line-size = <64>; 104 i-cache-sets = <256>; 105 d-cache-size = <0x8000>; 106 d-cache-line-size = <64>; 107 d-cache-sets = <256>; 108 next-level-cache = <&C1_L2>; 109 }; 110 cpu5: cpu@10100 { 111 device_type = "cpu"; 112 compatible = "arm,armv8"; 113 reg = <0x0 0x10100>; 114 enable-method = "psci"; 115 i-cache-size = <0x8000>; 116 i-cache-line-size = <64>; 117 i-cache-sets = <256>; 118 d-cache-size = <0x8000>; 119 d-cache-line-size = <64>; 120 d-cache-sets = <256>; 121 next-level-cache = <&C1_L2>; 122 }; 123 cpu6: cpu@10200 { 124 device_type = "cpu"; 125 compatible = "arm,armv8"; 126 reg = <0x0 0x10200>; 127 enable-method = "psci"; 128 i-cache-size = <0x8000>; 129 i-cache-line-size = <64>; 130 i-cache-sets = <256>; 131 d-cache-size = <0x8000>; 132 d-cache-line-size = <64>; 133 d-cache-sets = <256>; 134 next-level-cache = <&C1_L2>; 135 }; 136 cpu7: cpu@10300 { 137 device_type = "cpu"; 138 compatible = "arm,armv8"; 139 reg = <0x0 0x10300>; 140 enable-method = "psci"; 141 i-cache-size = <0x8000>; 142 i-cache-line-size = <64>; 143 i-cache-sets = <256>; 144 d-cache-size = <0x8000>; 145 d-cache-line-size = <64>; 146 d-cache-sets = <256>; 147 next-level-cache = <&C1_L2>; 148 }; 149 C0_L2: l2-cache0 { 150 compatible = "cache"; 151 cache-size = <0x80000>; 152 cache-line-size = <64>; 153 cache-sets = <512>; 154 cache-level = <2>; 155 cache-unified; 156 }; 157 158 C1_L2: l2-cache1 { 159 compatible = "cache"; 160 cache-size = <0x80000>; 161 cache-line-size = <64>; 162 cache-sets = <512>; 163 cache-level = <2>; 164 cache-unified; 165 }; 166 }; 167 168 memory@80000000 { 169 device_type = "memory"; 170 reg = <0x00000000 0x80000000 0 0x80000000>, 171 <0x00000008 0x80000000 0 0x80000000>; 172 }; 173 174 reserved-memory { 175 #address-cells = <2>; 176 #size-cells = <2>; 177 ranges; 178 179 /* Chipselect 2,00000000 is physically at 0x18000000 */ 180 vram: vram@18000000 { 181 /* 8 MB of designated video RAM */ 182 compatible = "shared-dma-pool"; 183 reg = <0x00000000 0x18000000 0 0x00800000>; 184 no-map; 185 }; 186 }; 187 188 gic: interrupt-controller@2f000000 { 189 compatible = "arm,gic-v3"; 190 #interrupt-cells = <3>; 191 #address-cells = <2>; 192 #size-cells = <2>; 193 ranges; 194 interrupt-controller; 195 reg = <0x0 0x2f000000 0 0x10000>, // GICD 196 <0x0 0x2f100000 0 0x200000>, // GICR 197 <0x0 0x2c000000 0 0x2000>, // GICC 198 <0x0 0x2c010000 0 0x2000>, // GICH 199 <0x0 0x2c02f000 0 0x2000>; // GICV 200 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 201 202 its: msi-controller@2f020000 { 203 #msi-cells = <1>; 204 compatible = "arm,gic-v3-its"; 205 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS 206 msi-controller; 207 }; 208 }; 209 210 timer { 211 compatible = "arm,armv8-timer"; 212 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 213 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 214 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 215 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 216 }; 217 218 pmu { 219 compatible = "arm,armv8-pmuv3"; 220 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 221 }; 222 223 spe-pmu { 224 compatible = "arm,statistical-profiling-extension-v1"; 225 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 226 }; 227 228 pci: pci@40000000 { 229 #address-cells = <0x3>; 230 #size-cells = <0x2>; 231 #interrupt-cells = <0x1>; 232 compatible = "pci-host-ecam-generic"; 233 device_type = "pci"; 234 bus-range = <0x0 0x1>; 235 reg = <0x0 0x40000000 0x0 0x10000000>; 236 ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>; 237 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 238 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 239 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 240 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 241 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 242 msi-map = <0x0 &its 0x0 0x10000>; 243 iommu-map = <0x0 &smmu 0x0 0x10000>; 244 245 dma-coherent; 246 }; 247 248 smmu: iommu@2b400000 { 249 compatible = "arm,smmu-v3"; 250 reg = <0x0 0x2b400000 0x0 0x100000>; 251 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 252 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 253 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 254 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; 255 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 256 dma-coherent; 257 #iommu-cells = <1>; 258 msi-parent = <&its 0x10000>; 259 }; 260 261 panel { 262 compatible = "arm,rtsm-display"; 263 port { 264 panel_in: endpoint { 265 remote-endpoint = <&clcd_pads>; 266 }; 267 }; 268 }; 269 270 bus@8000000 { 271 #interrupt-cells = <1>; 272 interrupt-map-mask = <0 0 63>; 273 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 274 <0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 275 <0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 276 <0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 277 <0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 278 <0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 279 <0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 280 <0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 281 <0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 282 <0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 283 <0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 284 <0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 285 <0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 286 <0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 287 <0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 288 <0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 289 <0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 290 <0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 291 <0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 292 <0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 293 <0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 294 <0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 295 <0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 296 <0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 297 <0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 298 <0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 299 <0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 300 <0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 301 <0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 302 <0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 303 <0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 304 <0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 305 <0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 306 <0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 307 <0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 308 <0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 309 <0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 310 <0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 311 <0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 312 <0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 313 <0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 314 <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 315 <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 316 <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 317 <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 318 <0 0 46 &gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 319 }; 320}; 321