1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC 4 * 5 * Copyright (C) 2015, Applied Micro Circuits Corporation 6 */ 7 8/ { 9 compatible = "apm,xgene-shadowcat"; 10 interrupt-parent = <&gic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 cpus { 15 #address-cells = <2>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 device_type = "cpu"; 20 compatible = "apm,strega"; 21 reg = <0x0 0x000>; 22 enable-method = "spin-table"; 23 cpu-release-addr = <0x1 0x0000fff8>; 24 next-level-cache = <&xgene_L2_0>; 25 #clock-cells = <1>; 26 clocks = <&pmd0clk 0>; 27 }; 28 cpu@1 { 29 device_type = "cpu"; 30 compatible = "apm,strega"; 31 reg = <0x0 0x001>; 32 enable-method = "spin-table"; 33 cpu-release-addr = <0x1 0x0000fff8>; 34 next-level-cache = <&xgene_L2_0>; 35 #clock-cells = <1>; 36 clocks = <&pmd0clk 0>; 37 }; 38 cpu@100 { 39 device_type = "cpu"; 40 compatible = "apm,strega"; 41 reg = <0x0 0x100>; 42 enable-method = "spin-table"; 43 cpu-release-addr = <0x1 0x0000fff8>; 44 next-level-cache = <&xgene_L2_1>; 45 #clock-cells = <1>; 46 clocks = <&pmd1clk 0>; 47 }; 48 cpu@101 { 49 device_type = "cpu"; 50 compatible = "apm,strega"; 51 reg = <0x0 0x101>; 52 enable-method = "spin-table"; 53 cpu-release-addr = <0x1 0x0000fff8>; 54 next-level-cache = <&xgene_L2_1>; 55 #clock-cells = <1>; 56 clocks = <&pmd1clk 0>; 57 }; 58 cpu@200 { 59 device_type = "cpu"; 60 compatible = "apm,strega"; 61 reg = <0x0 0x200>; 62 enable-method = "spin-table"; 63 cpu-release-addr = <0x1 0x0000fff8>; 64 next-level-cache = <&xgene_L2_2>; 65 #clock-cells = <1>; 66 clocks = <&pmd2clk 0>; 67 }; 68 cpu@201 { 69 device_type = "cpu"; 70 compatible = "apm,strega"; 71 reg = <0x0 0x201>; 72 enable-method = "spin-table"; 73 cpu-release-addr = <0x1 0x0000fff8>; 74 next-level-cache = <&xgene_L2_2>; 75 #clock-cells = <1>; 76 clocks = <&pmd2clk 0>; 77 }; 78 cpu@300 { 79 device_type = "cpu"; 80 compatible = "apm,strega"; 81 reg = <0x0 0x300>; 82 enable-method = "spin-table"; 83 cpu-release-addr = <0x1 0x0000fff8>; 84 next-level-cache = <&xgene_L2_3>; 85 #clock-cells = <1>; 86 clocks = <&pmd3clk 0>; 87 }; 88 cpu@301 { 89 device_type = "cpu"; 90 compatible = "apm,strega"; 91 reg = <0x0 0x301>; 92 enable-method = "spin-table"; 93 cpu-release-addr = <0x1 0x0000fff8>; 94 next-level-cache = <&xgene_L2_3>; 95 #clock-cells = <1>; 96 clocks = <&pmd3clk 0>; 97 }; 98 xgene_L2_0: l2-cache-0 { 99 compatible = "cache"; 100 }; 101 xgene_L2_1: l2-cache-1 { 102 compatible = "cache"; 103 }; 104 xgene_L2_2: l2-cache-2 { 105 compatible = "cache"; 106 }; 107 xgene_L2_3: l2-cache-3 { 108 compatible = "cache"; 109 }; 110 }; 111 112 gic: interrupt-controller@78090000 { 113 compatible = "arm,cortex-a15-gic"; 114 #interrupt-cells = <3>; 115 #address-cells = <2>; 116 #size-cells = <2>; 117 interrupt-controller; 118 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ 119 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */ 120 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */ 121 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */ 122 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */ 123 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */ 124 v2m0: v2m@0 { 125 compatible = "arm,gic-v2m-frame"; 126 msi-controller; 127 reg = <0x0 0x0 0x0 0x1000>; 128 }; 129 v2m1: v2m@10000 { 130 compatible = "arm,gic-v2m-frame"; 131 msi-controller; 132 reg = <0x0 0x10000 0x0 0x1000>; 133 }; 134 v2m2: v2m@20000 { 135 compatible = "arm,gic-v2m-frame"; 136 msi-controller; 137 reg = <0x0 0x20000 0x0 0x1000>; 138 }; 139 v2m3: v2m@30000 { 140 compatible = "arm,gic-v2m-frame"; 141 msi-controller; 142 reg = <0x0 0x30000 0x0 0x1000>; 143 }; 144 v2m4: v2m@40000 { 145 compatible = "arm,gic-v2m-frame"; 146 msi-controller; 147 reg = <0x0 0x40000 0x0 0x1000>; 148 }; 149 v2m5: v2m@50000 { 150 compatible = "arm,gic-v2m-frame"; 151 msi-controller; 152 reg = <0x0 0x50000 0x0 0x1000>; 153 }; 154 v2m6: v2m@60000 { 155 compatible = "arm,gic-v2m-frame"; 156 msi-controller; 157 reg = <0x0 0x60000 0x0 0x1000>; 158 }; 159 v2m7: v2m@70000 { 160 compatible = "arm,gic-v2m-frame"; 161 msi-controller; 162 reg = <0x0 0x70000 0x0 0x1000>; 163 }; 164 v2m8: v2m@80000 { 165 compatible = "arm,gic-v2m-frame"; 166 msi-controller; 167 reg = <0x0 0x80000 0x0 0x1000>; 168 }; 169 v2m9: v2m@90000 { 170 compatible = "arm,gic-v2m-frame"; 171 msi-controller; 172 reg = <0x0 0x90000 0x0 0x1000>; 173 }; 174 v2m10: v2m@a0000 { 175 compatible = "arm,gic-v2m-frame"; 176 msi-controller; 177 reg = <0x0 0xa0000 0x0 0x1000>; 178 }; 179 v2m11: v2m@b0000 { 180 compatible = "arm,gic-v2m-frame"; 181 msi-controller; 182 reg = <0x0 0xb0000 0x0 0x1000>; 183 }; 184 v2m12: v2m@c0000 { 185 compatible = "arm,gic-v2m-frame"; 186 msi-controller; 187 reg = <0x0 0xc0000 0x0 0x1000>; 188 }; 189 v2m13: v2m@d0000 { 190 compatible = "arm,gic-v2m-frame"; 191 msi-controller; 192 reg = <0x0 0xd0000 0x0 0x1000>; 193 }; 194 v2m14: v2m@e0000 { 195 compatible = "arm,gic-v2m-frame"; 196 msi-controller; 197 reg = <0x0 0xe0000 0x0 0x1000>; 198 }; 199 v2m15: v2m@f0000 { 200 compatible = "arm,gic-v2m-frame"; 201 msi-controller; 202 reg = <0x0 0xf0000 0x0 0x1000>; 203 }; 204 }; 205 206 pmu { 207 compatible = "arm,armv8-pmuv3"; 208 interrupts = <1 12 0xff04>; 209 }; 210 211 timer { 212 compatible = "arm,armv8-timer"; 213 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ 214 <1 13 0xff08>, /* Non-secure Phys IRQ */ 215 <1 14 0xff08>, /* Virt IRQ */ 216 <1 15 0xff08>; /* Hyp IRQ */ 217 clock-frequency = <50000000>; 218 }; 219 220 soc { 221 compatible = "simple-bus"; 222 #address-cells = <2>; 223 #size-cells = <2>; 224 ranges; 225 226 clocks { 227 #address-cells = <2>; 228 #size-cells = <2>; 229 ranges; 230 231 refclk: refclk { 232 compatible = "fixed-clock"; 233 #clock-cells = <1>; 234 clock-frequency = <100000000>; 235 clock-output-names = "refclk"; 236 }; 237 238 pmdpll: pmdpll@170000f0 { 239 compatible = "apm,xgene-pcppll-v2-clock"; 240 #clock-cells = <1>; 241 clocks = <&refclk 0>; 242 reg = <0x0 0x170000f0 0x0 0x10>; 243 clock-output-names = "pmdpll"; 244 }; 245 246 pmd0clk: pmd0clk@7e200200 { 247 compatible = "apm,xgene-pmd-clock"; 248 #clock-cells = <1>; 249 clocks = <&pmdpll 0>; 250 reg = <0x0 0x7e200200 0x0 0x10>; 251 clock-output-names = "pmd0clk"; 252 }; 253 254 pmd1clk: pmd1clk@7e200210 { 255 compatible = "apm,xgene-pmd-clock"; 256 #clock-cells = <1>; 257 clocks = <&pmdpll 0>; 258 reg = <0x0 0x7e200210 0x0 0x10>; 259 clock-output-names = "pmd1clk"; 260 }; 261 262 pmd2clk: pmd2clk@7e200220 { 263 compatible = "apm,xgene-pmd-clock"; 264 #clock-cells = <1>; 265 clocks = <&pmdpll 0>; 266 reg = <0x0 0x7e200220 0x0 0x10>; 267 clock-output-names = "pmd2clk"; 268 }; 269 270 pmd3clk: pmd3clk@7e200230 { 271 compatible = "apm,xgene-pmd-clock"; 272 #clock-cells = <1>; 273 clocks = <&pmdpll 0>; 274 reg = <0x0 0x7e200230 0x0 0x10>; 275 clock-output-names = "pmd3clk"; 276 }; 277 278 socpll: socpll@17000120 { 279 compatible = "apm,xgene-socpll-v2-clock"; 280 #clock-cells = <1>; 281 clocks = <&refclk 0>; 282 reg = <0x0 0x17000120 0x0 0x1000>; 283 clock-output-names = "socpll"; 284 }; 285 286 socplldiv2: socplldiv2 { 287 compatible = "fixed-factor-clock"; 288 #clock-cells = <1>; 289 clocks = <&socpll 0>; 290 clock-mult = <1>; 291 clock-div = <2>; 292 clock-output-names = "socplldiv2"; 293 }; 294 295 ahbclk: ahbclk@17000000 { 296 compatible = "apm,xgene-device-clock"; 297 #clock-cells = <1>; 298 clocks = <&socplldiv2 0>; 299 reg = <0x0 0x17000000 0x0 0x2000>; 300 reg-names = "div-reg"; 301 divider-offset = <0x164>; 302 divider-width = <0x5>; 303 divider-shift = <0x0>; 304 clock-output-names = "ahbclk"; 305 }; 306 307 sbapbclk: sbapbclk@1704c000 { 308 compatible = "apm,xgene-device-clock"; 309 #clock-cells = <1>; 310 clocks = <&ahbclk 0>; 311 reg = <0x0 0x1704c000 0x0 0x2000>; 312 reg-names = "div-reg"; 313 divider-offset = <0x10>; 314 divider-width = <0x2>; 315 divider-shift = <0x0>; 316 clock-output-names = "sbapbclk"; 317 }; 318 319 sdioclk: sdioclk@1f2ac000 { 320 compatible = "apm,xgene-device-clock"; 321 #clock-cells = <1>; 322 clocks = <&socplldiv2 0>; 323 reg = <0x0 0x1f2ac000 0x0 0x1000 324 0x0 0x17000000 0x0 0x2000>; 325 reg-names = "csr-reg", "div-reg"; 326 csr-offset = <0x0>; 327 csr-mask = <0x2>; 328 enable-offset = <0x8>; 329 enable-mask = <0x2>; 330 divider-offset = <0x178>; 331 divider-width = <0x8>; 332 divider-shift = <0x0>; 333 clock-output-names = "sdioclk"; 334 }; 335 336 pcie0clk: pcie0clk@1f2bc000 { 337 compatible = "apm,xgene-device-clock"; 338 #clock-cells = <1>; 339 clocks = <&socplldiv2 0>; 340 reg = <0x0 0x1f2bc000 0x0 0x1000>; 341 reg-names = "csr-reg"; 342 clock-output-names = "pcie0clk"; 343 }; 344 345 pcie1clk: pcie1clk@1f2cc000 { 346 compatible = "apm,xgene-device-clock"; 347 #clock-cells = <1>; 348 clocks = <&socplldiv2 0>; 349 reg = <0x0 0x1f2cc000 0x0 0x1000>; 350 reg-names = "csr-reg"; 351 clock-output-names = "pcie1clk"; 352 }; 353 354 xge0clk: xge0clk@1f61c000 { 355 compatible = "apm,xgene-device-clock"; 356 #clock-cells = <1>; 357 clocks = <&socplldiv2 0>; 358 reg = <0x0 0x1f61c000 0x0 0x1000>; 359 reg-names = "csr-reg"; 360 enable-mask = <0x3>; 361 csr-mask = <0x3>; 362 clock-output-names = "xge0clk"; 363 }; 364 365 xge1clk: xge1clk@1f62c000 { 366 compatible = "apm,xgene-device-clock"; 367 #clock-cells = <1>; 368 clocks = <&socplldiv2 0>; 369 reg = <0x0 0x1f62c000 0x0 0x1000>; 370 reg-names = "csr-reg"; 371 enable-mask = <0x3>; 372 csr-mask = <0x3>; 373 clock-output-names = "xge1clk"; 374 }; 375 376 rngpkaclk: rngpkaclk@17000000 { 377 compatible = "apm,xgene-device-clock"; 378 #clock-cells = <1>; 379 clocks = <&socplldiv2 0>; 380 reg = <0x0 0x17000000 0x0 0x2000>; 381 reg-names = "csr-reg"; 382 csr-offset = <0xc>; 383 csr-mask = <0x10>; 384 enable-offset = <0x10>; 385 enable-mask = <0x10>; 386 clock-output-names = "rngpkaclk"; 387 }; 388 389 i2c4clk: i2c4clk@1704c000 { 390 compatible = "apm,xgene-device-clock"; 391 #clock-cells = <1>; 392 clocks = <&sbapbclk 0>; 393 reg = <0x0 0x1704c000 0x0 0x1000>; 394 reg-names = "csr-reg"; 395 csr-offset = <0x0>; 396 csr-mask = <0x40>; 397 enable-offset = <0x8>; 398 enable-mask = <0x40>; 399 clock-output-names = "i2c4clk"; 400 }; 401 }; 402 403 scu: system-clk-controller@17000000 { 404 compatible = "apm,xgene-scu","syscon"; 405 reg = <0x0 0x17000000 0x0 0x400>; 406 }; 407 408 reboot: reboot@17000014 { 409 compatible = "syscon-reboot"; 410 regmap = <&scu>; 411 offset = <0x14>; 412 mask = <0x1>; 413 }; 414 415 csw: csw@7e200000 { 416 compatible = "apm,xgene-csw", "syscon"; 417 reg = <0x0 0x7e200000 0x0 0x1000>; 418 }; 419 420 mcba: mcba@7e700000 { 421 compatible = "apm,xgene-mcb", "syscon"; 422 reg = <0x0 0x7e700000 0x0 0x1000>; 423 }; 424 425 mcbb: mcbb@7e720000 { 426 compatible = "apm,xgene-mcb", "syscon"; 427 reg = <0x0 0x7e720000 0x0 0x1000>; 428 }; 429 430 efuse: efuse@1054a000 { 431 compatible = "apm,xgene-efuse", "syscon"; 432 reg = <0x0 0x1054a000 0x0 0x20>; 433 }; 434 435 edac@78800000 { 436 compatible = "apm,xgene-edac"; 437 #address-cells = <2>; 438 #size-cells = <2>; 439 ranges; 440 regmap-csw = <&csw>; 441 regmap-mcba = <&mcba>; 442 regmap-mcbb = <&mcbb>; 443 regmap-efuse = <&efuse>; 444 reg = <0x0 0x78800000 0x0 0x100>; 445 interrupts = <0x0 0x20 0x4>, 446 <0x0 0x21 0x4>, 447 <0x0 0x27 0x4>; 448 449 edacmc@7e800000 { 450 compatible = "apm,xgene-edac-mc"; 451 reg = <0x0 0x7e800000 0x0 0x1000>; 452 memory-controller = <0>; 453 }; 454 455 edacmc@7e840000 { 456 compatible = "apm,xgene-edac-mc"; 457 reg = <0x0 0x7e840000 0x0 0x1000>; 458 memory-controller = <1>; 459 }; 460 461 edacmc@7e880000 { 462 compatible = "apm,xgene-edac-mc"; 463 reg = <0x0 0x7e880000 0x0 0x1000>; 464 memory-controller = <2>; 465 }; 466 467 edacmc@7e8c0000 { 468 compatible = "apm,xgene-edac-mc"; 469 reg = <0x0 0x7e8c0000 0x0 0x1000>; 470 memory-controller = <3>; 471 }; 472 473 edacpmd@7c000000 { 474 compatible = "apm,xgene-edac-pmd"; 475 reg = <0x0 0x7c000000 0x0 0x200000>; 476 pmd-controller = <0>; 477 }; 478 479 edacpmd@7c200000 { 480 compatible = "apm,xgene-edac-pmd"; 481 reg = <0x0 0x7c200000 0x0 0x200000>; 482 pmd-controller = <1>; 483 }; 484 485 edacpmd@7c400000 { 486 compatible = "apm,xgene-edac-pmd"; 487 reg = <0x0 0x7c400000 0x0 0x200000>; 488 pmd-controller = <2>; 489 }; 490 491 edacpmd@7c600000 { 492 compatible = "apm,xgene-edac-pmd"; 493 reg = <0x0 0x7c600000 0x0 0x200000>; 494 pmd-controller = <3>; 495 }; 496 497 edacl3@7e600000 { 498 compatible = "apm,xgene-edac-l3-v2"; 499 reg = <0x0 0x7e600000 0x0 0x1000>; 500 }; 501 502 edacsoc@7e930000 { 503 compatible = "apm,xgene-edac-soc"; 504 reg = <0x0 0x7e930000 0x0 0x1000>; 505 }; 506 }; 507 508 pmu: pmu@78810000 { 509 compatible = "apm,xgene-pmu-v2"; 510 #address-cells = <2>; 511 #size-cells = <2>; 512 ranges; 513 regmap-csw = <&csw>; 514 regmap-mcba = <&mcba>; 515 regmap-mcbb = <&mcbb>; 516 reg = <0x0 0x78810000 0x0 0x1000>; 517 interrupts = <0x0 0x22 0x4>; 518 519 pmul3c@7e610000 { 520 compatible = "apm,xgene-pmu-l3c"; 521 reg = <0x0 0x7e610000 0x0 0x1000>; 522 }; 523 524 pmuiob@7e940000 { 525 compatible = "apm,xgene-pmu-iob"; 526 reg = <0x0 0x7e940000 0x0 0x1000>; 527 }; 528 529 pmucmcb@7e710000 { 530 compatible = "apm,xgene-pmu-mcb"; 531 reg = <0x0 0x7e710000 0x0 0x1000>; 532 enable-bit-index = <0>; 533 }; 534 535 pmucmcb@7e730000 { 536 compatible = "apm,xgene-pmu-mcb"; 537 reg = <0x0 0x7e730000 0x0 0x1000>; 538 enable-bit-index = <1>; 539 }; 540 541 pmucmc@7e810000 { 542 compatible = "apm,xgene-pmu-mc"; 543 reg = <0x0 0x7e810000 0x0 0x1000>; 544 enable-bit-index = <0>; 545 }; 546 547 pmucmc@7e850000 { 548 compatible = "apm,xgene-pmu-mc"; 549 reg = <0x0 0x7e850000 0x0 0x1000>; 550 enable-bit-index = <1>; 551 }; 552 553 pmucmc@7e890000 { 554 compatible = "apm,xgene-pmu-mc"; 555 reg = <0x0 0x7e890000 0x0 0x1000>; 556 enable-bit-index = <2>; 557 }; 558 559 pmucmc@7e8d0000 { 560 compatible = "apm,xgene-pmu-mc"; 561 reg = <0x0 0x7e8d0000 0x0 0x1000>; 562 enable-bit-index = <3>; 563 }; 564 }; 565 566 mailbox: mailbox@10540000 { 567 compatible = "apm,xgene-slimpro-mbox"; 568 reg = <0x0 0x10540000 0x0 0x8000>; 569 #mbox-cells = <1>; 570 interrupts = <0x0 0x0 0x4 571 0x0 0x1 0x4 572 0x0 0x2 0x4 573 0x0 0x3 0x4 574 0x0 0x4 0x4 575 0x0 0x5 0x4 576 0x0 0x6 0x4 577 0x0 0x7 0x4>; 578 }; 579 580 i2cslimpro { 581 compatible = "apm,xgene-slimpro-i2c"; 582 mboxes = <&mailbox 0>; 583 }; 584 585 hwmonslimpro { 586 compatible = "apm,xgene-slimpro-hwmon"; 587 mboxes = <&mailbox 7>; 588 }; 589 590 serial0: serial@10600000 { 591 device_type = "serial"; 592 compatible = "ns16550"; 593 reg = <0 0x10600000 0x0 0x1000>; 594 reg-shift = <2>; 595 clock-frequency = <10000000>; 596 interrupt-parent = <&gic>; 597 interrupts = <0x0 0x4c 0x4>; 598 }; 599 600 /* Do not change dwusb name, coded for backward compatibility */ 601 usb0: dwusb@19000000 { 602 status = "disabled"; 603 compatible = "snps,dwc3"; 604 reg = <0x0 0x19000000 0x0 0x100000>; 605 interrupts = <0x0 0x5d 0x4>; 606 dma-coherent; 607 dr_mode = "host"; 608 }; 609 610 pcie0: pcie@1f2b0000 { 611 status = "disabled"; 612 device_type = "pci"; 613 compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; 614 #interrupt-cells = <1>; 615 #size-cells = <2>; 616 #address-cells = <3>; 617 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ 618 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 619 reg-names = "csr", "cfg"; 620 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ 621 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */ 622 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */ 623 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 624 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 625 bus-range = <0x00 0xff>; 626 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 627 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4 628 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4 629 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4 630 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>; 631 dma-coherent; 632 clocks = <&pcie0clk 0>; 633 msi-parent = <&v2m0>; 634 }; 635 636 pcie1: pcie@1f2c0000 { 637 status = "disabled"; 638 device_type = "pci"; 639 compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; 640 #interrupt-cells = <1>; 641 #size-cells = <2>; 642 #address-cells = <3>; 643 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ 644 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 645 reg-names = "csr", "cfg"; 646 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ 647 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */ 648 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ 649 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 650 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 651 bus-range = <0x00 0xff>; 652 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 653 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4 654 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4 655 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4 656 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>; 657 dma-coherent; 658 clocks = <&pcie1clk 0>; 659 msi-parent = <&v2m0>; 660 }; 661 662 sata1: sata@1a000000 { 663 compatible = "apm,xgene-ahci-v2"; 664 reg = <0x0 0x1a000000 0x0 0x1000>, 665 <0x0 0x1f200000 0x0 0x1000>, 666 <0x0 0x1f20d000 0x0 0x1000>, 667 <0x0 0x1f20e000 0x0 0x1000>; 668 interrupts = <0x0 0x5a 0x4>; 669 dma-coherent; 670 }; 671 672 sata2: sata@1a200000 { 673 compatible = "apm,xgene-ahci-v2"; 674 reg = <0x0 0x1a200000 0x0 0x1000>, 675 <0x0 0x1f210000 0x0 0x1000>, 676 <0x0 0x1f21d000 0x0 0x1000>, 677 <0x0 0x1f21e000 0x0 0x1000>; 678 interrupts = <0x0 0x5b 0x4>; 679 dma-coherent; 680 }; 681 682 sata3: sata@1a400000 { 683 compatible = "apm,xgene-ahci-v2"; 684 reg = <0x0 0x1a400000 0x0 0x1000>, 685 <0x0 0x1f220000 0x0 0x1000>, 686 <0x0 0x1f22d000 0x0 0x1000>, 687 <0x0 0x1f22e000 0x0 0x1000>; 688 interrupts = <0x0 0x5c 0x4>; 689 dma-coherent; 690 }; 691 692 mmc0: mmc@1c000000 { 693 compatible = "arasan,sdhci-4.9a"; 694 reg = <0x0 0x1c000000 0x0 0x100>; 695 interrupts = <0x0 0x49 0x4>; 696 dma-coherent; 697 no-1-8-v; 698 clock-names = "clk_xin", "clk_ahb"; 699 clocks = <&sdioclk 0>, <&ahbclk 0>; 700 }; 701 702 gfcgpio: gpio@1f63c000 { 703 compatible = "apm,xgene-gpio"; 704 reg = <0x0 0x1f63c000 0x0 0x40>; 705 gpio-controller; 706 #gpio-cells = <2>; 707 }; 708 709 dwgpio: gpio@1c024000 { 710 compatible = "snps,dw-apb-gpio"; 711 reg = <0x0 0x1c024000 0x0 0x1000>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 715 porta: gpio-controller@0 { 716 compatible = "snps,dw-apb-gpio-port"; 717 gpio-controller; 718 #gpio-cells = <2>; 719 snps,nr-gpios = <32>; 720 reg = <0>; 721 }; 722 }; 723 724 sbgpio: gpio@17001000{ 725 compatible = "apm,xgene-gpio-sb"; 726 reg = <0x0 0x17001000 0x0 0x400>; 727 #gpio-cells = <2>; 728 gpio-controller; 729 interrupts = <0x0 0x28 0x1>, 730 <0x0 0x29 0x1>, 731 <0x0 0x2a 0x1>, 732 <0x0 0x2b 0x1>, 733 <0x0 0x2c 0x1>, 734 <0x0 0x2d 0x1>, 735 <0x0 0x2e 0x1>, 736 <0x0 0x2f 0x1>; 737 interrupt-parent = <&gic>; 738 #interrupt-cells = <2>; 739 interrupt-controller; 740 apm,nr-gpios = <22>; 741 apm,nr-irqs = <8>; 742 apm,irq-start = <8>; 743 }; 744 745 mdio: mdio@1f610000 { 746 compatible = "apm,xgene-mdio-xfi"; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 reg = <0x0 0x1f610000 0x0 0xd100>; 750 clocks = <&xge0clk 0>; 751 }; 752 753 sgenet0: ethernet@1f610000 { 754 compatible = "apm,xgene2-sgenet"; 755 status = "disabled"; 756 reg = <0x0 0x1f610000 0x0 0xd100>, 757 <0x0 0x1f600000 0x0 0xd100>, 758 <0x0 0x20000000 0x0 0x20000>; 759 interrupts = <0 96 4>, 760 <0 97 4>; 761 dma-coherent; 762 clocks = <&xge0clk 0>; 763 local-mac-address = [00 01 73 00 00 01]; 764 phy-connection-type = "sgmii"; 765 phy-handle = <&sgenet0phy>; 766 }; 767 768 xgenet1: ethernet@1f620000 { 769 compatible = "apm,xgene2-xgenet"; 770 status = "disabled"; 771 reg = <0x0 0x1f620000 0x0 0x10000>, 772 <0x0 0x1f600000 0x0 0xd100>, 773 <0x0 0x20000000 0x0 0x220000>; 774 interrupts = <0 108 4>, 775 <0 109 4>, 776 <0 110 4>, 777 <0 111 4>, 778 <0 112 4>, 779 <0 113 4>, 780 <0 114 4>, 781 <0 115 4>; 782 channel = <12>; 783 port-id = <1>; 784 dma-coherent; 785 clocks = <&xge1clk 0>; 786 local-mac-address = [00 01 73 00 00 02]; 787 phy-connection-type = "xgmii"; 788 }; 789 790 rng: rng@10520000 { 791 compatible = "apm,xgene-rng"; 792 reg = <0x0 0x10520000 0x0 0x100>; 793 interrupts = <0x0 0x41 0x4>; 794 clocks = <&rngpkaclk 0>; 795 }; 796 797 i2c1: i2c@10511000 { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 compatible = "snps,designware-i2c"; 801 reg = <0x0 0x10511000 0x0 0x1000>; 802 interrupts = <0 0x45 0x4>; 803 #clock-cells = <1>; 804 clocks = <&sbapbclk 0>; 805 bus_num = <1>; 806 }; 807 808 i2c4: i2c@10640000 { 809 #address-cells = <1>; 810 #size-cells = <0>; 811 compatible = "snps,designware-i2c"; 812 reg = <0x0 0x10640000 0x0 0x1000>; 813 interrupts = <0 0x3a 0x4>; 814 clocks = <&i2c4clk 0>; 815 bus_num = <4>; 816 }; 817 }; 818}; 819