1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Andreas Färber 4 * 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Neil Armstrong <narmstrong@baylibre.com> 7 * 8 * Copyright (c) 2016 Endless Computers, Inc. 9 * Author: Carlo Caione <carlo@endlessm.com> 10 */ 11 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/power/meson-gxbb-power.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 reserved-memory { 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 28 /* 16 MiB reserved for Hardware ROM Firmware */ 29 hwrom_reserved: hwrom@0 { 30 reg = <0x0 0x0 0x0 0x1000000>; 31 no-map; 32 }; 33 34 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ 35 secmon_reserved: secmon@10000000 { 36 reg = <0x0 0x10000000 0x0 0x200000>; 37 no-map; 38 }; 39 40 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 41 secmon_reserved_alt: secmon@5000000 { 42 reg = <0x0 0x05000000 0x0 0x300000>; 43 no-map; 44 }; 45 46 linux,cma { 47 compatible = "shared-dma-pool"; 48 reusable; 49 size = <0x0 0x10000000>; 50 alignment = <0x0 0x400000>; 51 linux,cma-default; 52 }; 53 }; 54 55 chosen { 56 #address-cells = <2>; 57 #size-cells = <2>; 58 ranges; 59 60 simplefb_cvbs: framebuffer-cvbs { 61 compatible = "amlogic,simple-framebuffer", 62 "simple-framebuffer"; 63 amlogic,pipeline = "vpu-cvbs"; 64 power-domains = <&pwrc PWRC_GXBB_VPU_ID>; 65 status = "disabled"; 66 }; 67 68 simplefb_hdmi: framebuffer-hdmi { 69 compatible = "amlogic,simple-framebuffer", 70 "simple-framebuffer"; 71 amlogic,pipeline = "vpu-hdmi"; 72 power-domains = <&pwrc PWRC_GXBB_VPU_ID>; 73 status = "disabled"; 74 }; 75 }; 76 77 cpus { 78 #address-cells = <0x2>; 79 #size-cells = <0x0>; 80 81 cpu0: cpu@0 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x0>; 85 enable-method = "psci"; 86 next-level-cache = <&l2>; 87 clocks = <&scpi_dvfs 0>; 88 #cooling-cells = <2>; 89 }; 90 91 cpu1: cpu@1 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a53"; 94 reg = <0x0 0x1>; 95 enable-method = "psci"; 96 next-level-cache = <&l2>; 97 clocks = <&scpi_dvfs 0>; 98 #cooling-cells = <2>; 99 }; 100 101 cpu2: cpu@2 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x0 0x2>; 105 enable-method = "psci"; 106 next-level-cache = <&l2>; 107 clocks = <&scpi_dvfs 0>; 108 #cooling-cells = <2>; 109 }; 110 111 cpu3: cpu@3 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a53"; 114 reg = <0x0 0x3>; 115 enable-method = "psci"; 116 next-level-cache = <&l2>; 117 clocks = <&scpi_dvfs 0>; 118 #cooling-cells = <2>; 119 }; 120 121 l2: l2-cache0 { 122 compatible = "cache"; 123 }; 124 }; 125 126 thermal-zones { 127 cpu-thermal { 128 polling-delay-passive = <250>; /* milliseconds */ 129 polling-delay = <1000>; /* milliseconds */ 130 131 thermal-sensors = <&scpi_sensors 0>; 132 133 trips { 134 cpu_passive: cpu-passive { 135 temperature = <80000>; /* millicelsius */ 136 hysteresis = <2000>; /* millicelsius */ 137 type = "passive"; 138 }; 139 140 cpu_hot: cpu-hot { 141 temperature = <90000>; /* millicelsius */ 142 hysteresis = <2000>; /* millicelsius */ 143 type = "hot"; 144 }; 145 146 cpu_critical: cpu-critical { 147 temperature = <110000>; /* millicelsius */ 148 hysteresis = <2000>; /* millicelsius */ 149 type = "critical"; 150 }; 151 }; 152 153 cpu_cooling_maps: cooling-maps { 154 map0 { 155 trip = <&cpu_passive>; 156 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 157 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 158 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 159 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 160 }; 161 162 map1 { 163 trip = <&cpu_hot>; 164 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 165 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 166 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 167 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 168 }; 169 }; 170 }; 171 }; 172 173 arm-pmu { 174 compatible = "arm,cortex-a53-pmu"; 175 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 179 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 180 }; 181 182 psci { 183 compatible = "arm,psci-0.2"; 184 method = "smc"; 185 }; 186 187 timer { 188 compatible = "arm,armv8-timer"; 189 interrupts = <GIC_PPI 13 190 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 191 <GIC_PPI 14 192 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 193 <GIC_PPI 11 194 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 195 <GIC_PPI 10 196 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 197 }; 198 199 xtal: xtal-clk { 200 compatible = "fixed-clock"; 201 clock-frequency = <24000000>; 202 clock-output-names = "xtal"; 203 #clock-cells = <0>; 204 }; 205 206 firmware { 207 sm: secure-monitor { 208 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; 209 }; 210 }; 211 212 efuse: efuse { 213 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 read-only; 217 secure-monitor = <&sm>; 218 219 sn: sn@14 { 220 reg = <0x14 0x10>; 221 }; 222 223 eth_mac: eth_mac@34 { 224 reg = <0x34 0x10>; 225 }; 226 227 bid: bid@46 { 228 reg = <0x46 0x30>; 229 }; 230 }; 231 232 scpi { 233 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; 234 mboxes = <&mailbox 1 &mailbox 2>; 235 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 236 237 scpi_clocks: clocks { 238 compatible = "arm,scpi-clocks"; 239 240 scpi_dvfs: scpi_clocks@0 { 241 compatible = "arm,scpi-dvfs-clocks"; 242 #clock-cells = <1>; 243 clock-indices = <0>; 244 clock-output-names = "vcpu"; 245 }; 246 }; 247 248 scpi_sensors: sensors { 249 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; 250 #thermal-sensor-cells = <1>; 251 }; 252 }; 253 254 soc { 255 compatible = "simple-bus"; 256 #address-cells = <2>; 257 #size-cells = <2>; 258 ranges; 259 260 cbus: bus@c1100000 { 261 compatible = "simple-bus"; 262 reg = <0x0 0xc1100000 0x0 0x100000>; 263 #address-cells = <2>; 264 #size-cells = <2>; 265 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; 266 267 gpio_intc: interrupt-controller@9880 { 268 compatible = "amlogic,meson-gpio-intc"; 269 reg = <0x0 0x9880 0x0 0x10>; 270 interrupt-controller; 271 #interrupt-cells = <2>; 272 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 273 status = "disabled"; 274 }; 275 276 reset: reset-controller@4404 { 277 compatible = "amlogic,meson-gxbb-reset"; 278 reg = <0x0 0x04404 0x0 0x9c>; 279 #reset-cells = <1>; 280 }; 281 282 aiu: audio-controller@5400 { 283 compatible = "amlogic,aiu"; 284 #sound-dai-cells = <2>; 285 sound-name-prefix = "AIU"; 286 reg = <0x0 0x5400 0x0 0x2ac>; 287 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 288 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 289 interrupt-names = "i2s", "spdif"; 290 status = "disabled"; 291 }; 292 293 uart_A: serial@84c0 { 294 compatible = "amlogic,meson-gx-uart"; 295 reg = <0x0 0x84c0 0x0 0x18>; 296 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 297 status = "disabled"; 298 }; 299 300 uart_B: serial@84dc { 301 compatible = "amlogic,meson-gx-uart"; 302 reg = <0x0 0x84dc 0x0 0x18>; 303 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 304 status = "disabled"; 305 }; 306 307 i2c_A: i2c@8500 { 308 compatible = "amlogic,meson-gxbb-i2c"; 309 reg = <0x0 0x08500 0x0 0x20>; 310 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 status = "disabled"; 314 }; 315 316 pwm_ab: pwm@8550 { 317 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 318 reg = <0x0 0x08550 0x0 0x10>; 319 #pwm-cells = <3>; 320 status = "disabled"; 321 }; 322 323 pwm_cd: pwm@8650 { 324 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 325 reg = <0x0 0x08650 0x0 0x10>; 326 #pwm-cells = <3>; 327 status = "disabled"; 328 }; 329 330 saradc: adc@8680 { 331 compatible = "amlogic,meson-saradc"; 332 reg = <0x0 0x8680 0x0 0x34>; 333 #io-channel-cells = <1>; 334 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 335 status = "disabled"; 336 }; 337 338 pwm_ef: pwm@86c0 { 339 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 340 reg = <0x0 0x086c0 0x0 0x10>; 341 #pwm-cells = <3>; 342 status = "disabled"; 343 }; 344 345 uart_C: serial@8700 { 346 compatible = "amlogic,meson-gx-uart"; 347 reg = <0x0 0x8700 0x0 0x18>; 348 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 349 status = "disabled"; 350 }; 351 352 clock-measure@8758 { 353 compatible = "amlogic,meson-gx-clk-measure"; 354 reg = <0x0 0x8758 0x0 0x10>; 355 }; 356 357 i2c_B: i2c@87c0 { 358 compatible = "amlogic,meson-gxbb-i2c"; 359 reg = <0x0 0x087c0 0x0 0x20>; 360 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 status = "disabled"; 364 }; 365 366 i2c_C: i2c@87e0 { 367 compatible = "amlogic,meson-gxbb-i2c"; 368 reg = <0x0 0x087e0 0x0 0x20>; 369 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 status = "disabled"; 373 }; 374 375 spicc: spi@8d80 { 376 compatible = "amlogic,meson-gx-spicc"; 377 reg = <0x0 0x08d80 0x0 0x80>; 378 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 status = "disabled"; 382 }; 383 384 spifc: spi@8c80 { 385 compatible = "amlogic,meson-gxbb-spifc"; 386 reg = <0x0 0x08c80 0x0 0x80>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 status = "disabled"; 390 }; 391 392 watchdog@98d0 { 393 compatible = "amlogic,meson-gxbb-wdt"; 394 reg = <0x0 0x098d0 0x0 0x10>; 395 clocks = <&xtal>; 396 }; 397 }; 398 399 gic: interrupt-controller@c4301000 { 400 compatible = "arm,gic-400"; 401 reg = <0x0 0xc4301000 0 0x1000>, 402 <0x0 0xc4302000 0 0x2000>, 403 <0x0 0xc4304000 0 0x2000>, 404 <0x0 0xc4306000 0 0x2000>; 405 interrupt-controller; 406 interrupts = <GIC_PPI 9 407 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 408 #interrupt-cells = <3>; 409 #address-cells = <0>; 410 }; 411 412 sram: sram@c8000000 { 413 compatible = "mmio-sram"; 414 reg = <0x0 0xc8000000 0x0 0x14000>; 415 416 #address-cells = <1>; 417 #size-cells = <1>; 418 ranges = <0 0x0 0xc8000000 0x14000>; 419 420 cpu_scp_lpri: scp-sram@0 { 421 compatible = "amlogic,meson-gxbb-scp-shmem"; 422 reg = <0x13000 0x400>; 423 }; 424 425 cpu_scp_hpri: scp-sram@200 { 426 compatible = "amlogic,meson-gxbb-scp-shmem"; 427 reg = <0x13400 0x400>; 428 }; 429 }; 430 431 aobus: bus@c8100000 { 432 compatible = "simple-bus"; 433 reg = <0x0 0xc8100000 0x0 0x100000>; 434 #address-cells = <2>; 435 #size-cells = <2>; 436 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; 437 438 sysctrl_AO: sys-ctrl@0 { 439 compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; 440 reg = <0x0 0x0 0x0 0x100>; 441 442 clkc_AO: clock-controller { 443 compatible = "amlogic,meson-gx-aoclkc"; 444 #clock-cells = <1>; 445 #reset-cells = <1>; 446 }; 447 }; 448 449 cec_AO: cec@100 { 450 compatible = "amlogic,meson-gx-ao-cec"; 451 reg = <0x0 0x00100 0x0 0x14>; 452 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 453 status = "disabled"; 454 }; 455 456 sec_AO: ao-secure@140 { 457 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 458 reg = <0x0 0x140 0x0 0x140>; 459 amlogic,has-chip-id; 460 }; 461 462 uart_AO: serial@4c0 { 463 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 464 reg = <0x0 0x004c0 0x0 0x18>; 465 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 466 status = "disabled"; 467 }; 468 469 uart_AO_B: serial@4e0 { 470 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 471 reg = <0x0 0x004e0 0x0 0x18>; 472 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 473 status = "disabled"; 474 }; 475 476 i2c_AO: i2c@500 { 477 compatible = "amlogic,meson-gxbb-i2c"; 478 reg = <0x0 0x500 0x0 0x20>; 479 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 status = "disabled"; 483 }; 484 485 pwm_AO_ab: pwm@550 { 486 compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; 487 reg = <0x0 0x00550 0x0 0x10>; 488 #pwm-cells = <3>; 489 status = "disabled"; 490 }; 491 492 ir: ir@580 { 493 compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; 494 reg = <0x0 0x00580 0x0 0x40>; 495 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 496 status = "disabled"; 497 }; 498 }; 499 500 vdec: video-codec@c8820000 { 501 compatible = "amlogic,gx-vdec"; 502 reg = <0x0 0xc8820000 0x0 0x10000>, 503 <0x0 0xc110a580 0x0 0xe4>; 504 reg-names = "dos", "esparser"; 505 506 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 507 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 508 interrupt-names = "vdec", "esparser"; 509 510 amlogic,ao-sysctrl = <&sysctrl_AO>; 511 amlogic,canvas = <&canvas>; 512 }; 513 514 periphs: bus@c8834000 { 515 compatible = "simple-bus"; 516 reg = <0x0 0xc8834000 0x0 0x2000>; 517 #address-cells = <2>; 518 #size-cells = <2>; 519 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; 520 521 hwrng: rng { 522 compatible = "amlogic,meson-rng"; 523 reg = <0x0 0x0 0x0 0x4>; 524 }; 525 }; 526 527 dmcbus: bus@c8838000 { 528 compatible = "simple-bus"; 529 reg = <0x0 0xc8838000 0x0 0x400>; 530 #address-cells = <2>; 531 #size-cells = <2>; 532 ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>; 533 534 canvas: video-lut@48 { 535 compatible = "amlogic,canvas"; 536 reg = <0x0 0x48 0x0 0x14>; 537 }; 538 }; 539 540 hiubus: bus@c883c000 { 541 compatible = "simple-bus"; 542 reg = <0x0 0xc883c000 0x0 0x2000>; 543 #address-cells = <2>; 544 #size-cells = <2>; 545 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; 546 547 sysctrl: system-controller@0 { 548 compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; 549 reg = <0 0 0 0x400>; 550 551 pwrc: power-controller { 552 compatible = "amlogic,meson-gxbb-pwrc"; 553 #power-domain-cells = <1>; 554 amlogic,ao-sysctrl = <&sysctrl_AO>; 555 }; 556 }; 557 558 mailbox: mailbox@404 { 559 compatible = "amlogic,meson-gxbb-mhu"; 560 reg = <0 0x404 0 0x4c>; 561 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 562 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 563 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 564 #mbox-cells = <1>; 565 }; 566 }; 567 568 ethmac: ethernet@c9410000 { 569 compatible = "amlogic,meson-gxbb-dwmac", 570 "snps,dwmac-3.70a", 571 "snps,dwmac"; 572 reg = <0x0 0xc9410000 0x0 0x10000>, 573 <0x0 0xc8834540 0x0 0x4>; 574 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 575 interrupt-names = "macirq"; 576 rx-fifo-depth = <4096>; 577 tx-fifo-depth = <2048>; 578 power-domains = <&pwrc PWRC_GXBB_ETHERNET_MEM_ID>; 579 status = "disabled"; 580 }; 581 582 apb: apb@d0000000 { 583 compatible = "simple-bus"; 584 reg = <0x0 0xd0000000 0x0 0x200000>; 585 #address-cells = <2>; 586 #size-cells = <2>; 587 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; 588 589 sd_emmc_a: mmc@70000 { 590 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 591 reg = <0x0 0x70000 0x0 0x800>; 592 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; 593 status = "disabled"; 594 }; 595 596 sd_emmc_b: mmc@72000 { 597 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 598 reg = <0x0 0x72000 0x0 0x800>; 599 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 600 status = "disabled"; 601 }; 602 603 sd_emmc_c: mmc@74000 { 604 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 605 reg = <0x0 0x74000 0x0 0x800>; 606 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 607 status = "disabled"; 608 }; 609 }; 610 611 vpu: vpu@d0100000 { 612 compatible = "amlogic,meson-gx-vpu"; 613 reg = <0x0 0xd0100000 0x0 0x100000>, 614 <0x0 0xc883c000 0x0 0x1000>; 615 reg-names = "vpu", "hhi"; 616 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 amlogic,canvas = <&canvas>; 620 621 /* CVBS VDAC output port */ 622 cvbs_vdac_port: port@0 { 623 reg = <0>; 624 }; 625 626 /* HDMI-TX output port */ 627 hdmi_tx_port: port@1 { 628 reg = <1>; 629 630 hdmi_tx_out: endpoint { 631 remote-endpoint = <&hdmi_tx_in>; 632 }; 633 }; 634 }; 635 636 hdmi_tx: hdmi-tx@c883a000 { 637 compatible = "amlogic,meson-gx-dw-hdmi"; 638 reg = <0x0 0xc883a000 0x0 0x1c>; 639 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 #sound-dai-cells = <0>; 643 sound-name-prefix = "HDMITX"; 644 status = "disabled"; 645 646 /* VPU VENC Input */ 647 hdmi_tx_venc_port: port@0 { 648 reg = <0>; 649 650 hdmi_tx_in: endpoint { 651 remote-endpoint = <&hdmi_tx_out>; 652 }; 653 }; 654 655 /* TMDS Output */ 656 hdmi_tx_tmds_port: port@1 { 657 reg = <1>; 658 }; 659 }; 660 }; 661}; 662