1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/power/amlogic,t7-pwrc.h> 8 9/ { 10 interrupt-parent = <&gic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 cpus { 15 #address-cells = <0x2>; 16 #size-cells = <0x0>; 17 18 cpu-map { 19 cluster0 { 20 core0 { 21 cpu = <&cpu100>; 22 }; 23 core1 { 24 cpu = <&cpu101>; 25 }; 26 core2 { 27 cpu = <&cpu102>; 28 }; 29 core3 { 30 cpu = <&cpu103>; 31 }; 32 }; 33 34 cluster1 { 35 core0 { 36 cpu = <&cpu0>; 37 }; 38 core1 { 39 cpu = <&cpu1>; 40 }; 41 core2 { 42 cpu = <&cpu2>; 43 }; 44 core3 { 45 cpu = <&cpu3>; 46 }; 47 }; 48 }; 49 50 cpu100: cpu@100 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x100>; 54 enable-method = "psci"; 55 }; 56 57 cpu101: cpu@101{ 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53"; 60 reg = <0x0 0x101>; 61 enable-method = "psci"; 62 }; 63 64 cpu102: cpu@102 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0 0x102>; 68 enable-method = "psci"; 69 }; 70 71 cpu103: cpu@103 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x0 0x103>; 75 enable-method = "psci"; 76 }; 77 78 cpu0: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a73"; 81 reg = <0x0 0x0>; 82 enable-method = "psci"; 83 }; 84 85 cpu1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a73"; 88 reg = <0x0 0x1>; 89 enable-method = "psci"; 90 }; 91 92 cpu2: cpu@2 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a73"; 95 reg = <0x0 0x2>; 96 enable-method = "psci"; 97 }; 98 99 cpu3: cpu@3 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a73"; 102 reg = <0x0 0x3>; 103 enable-method = "psci"; 104 }; 105 }; 106 107 timer { 108 compatible = "arm,armv8-timer"; 109 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 110 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 111 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 112 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 113 }; 114 115 psci { 116 compatible = "arm,psci-1.0"; 117 method = "smc"; 118 }; 119 120 sm: secure-monitor { 121 compatible = "amlogic,meson-gxbb-sm"; 122 123 pwrc: power-controller { 124 compatible = "amlogic,t7-pwrc"; 125 #power-domain-cells = <1>; 126 }; 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 #address-cells = <2>; 132 #size-cells = <2>; 133 ranges; 134 135 gic: interrupt-controller@fff01000 { 136 compatible = "arm,gic-400"; 137 #interrupt-cells = <3>; 138 #address-cells = <0>; 139 interrupt-controller; 140 reg = <0x0 0xfff01000 0 0x1000>, 141 <0x0 0xfff02000 0 0x0100>; 142 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 143 }; 144 145 apb4: bus@fe000000 { 146 compatible = "simple-bus"; 147 reg = <0x0 0xfe000000 0x0 0x480000>; 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 151 152 watchdog@2100 { 153 compatible = "amlogic,t7-wdt"; 154 reg = <0x0 0x2100 0x0 0x10>; 155 clocks = <&xtal>; 156 }; 157 158 periphs_pinctrl: pinctrl@4000 { 159 compatible = "amlogic,t7-periphs-pinctrl"; 160 #address-cells = <2>; 161 #size-cells = <2>; 162 ranges; 163 164 gpio: bank@4000 { 165 reg = <0x0 0x4000 0x0 0x0064>, 166 <0x0 0x40c0 0x0 0x0220>; 167 reg-names = "mux", "gpio"; 168 gpio-controller; 169 #gpio-cells = <2>; 170 gpio-ranges = <&periphs_pinctrl 0 0 157>; 171 }; 172 }; 173 174 uart_a: serial@78000 { 175 compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart"; 176 reg = <0x0 0x78000 0x0 0x18>; 177 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 178 status = "disabled"; 179 }; 180 }; 181 182 }; 183}; 184