xref: /freebsd/sys/contrib/device-tree/src/arm64/amlogic/amlogic-c3.dtsi (revision 8d13bc63c0e1d50bc9e47ac1f26329c999bfecf0)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11	cpus {
12		#address-cells = <2>;
13		#size-cells = <0>;
14
15		cpu0: cpu@0 {
16			device_type = "cpu";
17			compatible = "arm,cortex-a35";
18			reg = <0x0 0x0>;
19			enable-method = "psci";
20		};
21
22		cpu1: cpu@1 {
23			device_type = "cpu";
24			compatible = "arm,cortex-a35";
25			reg = <0x0 0x1>;
26			enable-method = "psci";
27		};
28	};
29
30	timer {
31		compatible = "arm,armv8-timer";
32		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
33			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
34			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
35			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
36	};
37
38	psci {
39		compatible = "arm,psci-1.0";
40		method = "smc";
41	};
42
43	xtal: xtal-clk {
44		compatible = "fixed-clock";
45		clock-frequency = <24000000>;
46		clock-output-names = "xtal";
47		#clock-cells = <0>;
48	};
49
50	sm: secure-monitor {
51		compatible = "amlogic,meson-gxbb-sm";
52
53		pwrc: power-controller {
54			compatible = "amlogic,c3-pwrc";
55			#power-domain-cells = <1>;
56		};
57	};
58
59	soc {
60		compatible = "simple-bus";
61		#address-cells = <2>;
62		#size-cells = <2>;
63		ranges;
64
65		gic: interrupt-controller@fff01000 {
66			compatible = "arm,gic-400";
67			#interrupt-cells = <3>;
68			#address-cells = <0>;
69			interrupt-controller;
70			reg = <0x0 0xfff01000 0 0x1000>,
71			      <0x0 0xfff02000 0 0x2000>,
72			      <0x0 0xfff04000 0 0x2000>,
73			      <0x0 0xfff06000 0 0x2000>;
74			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
75		};
76
77		apb4: bus@fe000000 {
78			compatible = "simple-bus";
79			reg = <0x0 0xfe000000 0x0 0x480000>;
80			#address-cells = <2>;
81			#size-cells = <2>;
82			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
83
84			watchdog@2100 {
85				compatible = "amlogic,c3-wdt", "amlogic,t7-wdt";
86				reg = <0x0 0x2100 0x0 0x10>;
87				clocks = <&xtal>;
88			};
89
90			periphs_pinctrl: pinctrl@4000 {
91				compatible = "amlogic,c3-periphs-pinctrl";
92				#address-cells = <2>;
93				#size-cells = <2>;
94				ranges;
95
96				gpio: bank@4000 {
97					reg = <0x0 0x4000 0x0 0x004c>,
98					      <0x0 0x4100 0x0 0x01de>;
99					reg-names = "mux", "gpio";
100					gpio-controller;
101					#gpio-cells = <2>;
102					gpio-ranges = <&periphs_pinctrl 0 0 55>;
103				};
104			};
105
106			gpio_intc: interrupt-controller@4080 {
107				compatible = "amlogic,meson-gpio-intc",
108					     "amlogic,c3-gpio-intc";
109				reg = <0x0 0x4080 0x0 0x0020>;
110				interrupt-controller;
111				#interrupt-cells = <2>;
112				amlogic,channel-interrupts =
113					<10 11 12 13 14 15 16 17 18 19 20 21>;
114			};
115
116			uart_b: serial@7a000 {
117				compatible = "amlogic,meson-s4-uart",
118					   "amlogic,meson-ao-uart";
119				reg = <0x0 0x7a000 0x0 0x18>;
120				interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
121				status = "disabled";
122				clocks = <&xtal>, <&xtal>, <&xtal>;
123				clock-names = "xtal", "pclk", "baud";
124			};
125
126		};
127	};
128};
129