1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright Altera Corporation (C) 2015. All rights reserved. 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/clock/stratix10-clock.h> 10 11/ { 12 compatible = "altr,socfpga-stratix10"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 reserved-memory { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 21 service_reserved: svcbuffer@0 { 22 compatible = "shared-dma-pool"; 23 reg = <0x0 0x0 0x0 0x1000000>; 24 alignment = <0x1000>; 25 no-map; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 enable-method = "psci"; 37 reg = <0x0>; 38 }; 39 40 cpu1: cpu@1 { 41 compatible = "arm,cortex-a53"; 42 device_type = "cpu"; 43 enable-method = "psci"; 44 reg = <0x1>; 45 }; 46 47 cpu2: cpu@2 { 48 compatible = "arm,cortex-a53"; 49 device_type = "cpu"; 50 enable-method = "psci"; 51 reg = <0x2>; 52 }; 53 54 cpu3: cpu@3 { 55 compatible = "arm,cortex-a53"; 56 device_type = "cpu"; 57 enable-method = "psci"; 58 reg = <0x3>; 59 }; 60 }; 61 62 firmware { 63 svc { 64 compatible = "intel,stratix10-svc"; 65 method = "smc"; 66 memory-region = <&service_reserved>; 67 68 fpga_mgr: fpga-mgr { 69 compatible = "intel,stratix10-soc-fpga-mgr"; 70 }; 71 }; 72 }; 73 74 fpga-region { 75 compatible = "fpga-region"; 76 #address-cells = <0x2>; 77 #size-cells = <0x2>; 78 fpga-mgr = <&fpga_mgr>; 79 }; 80 81 pmu { 82 compatible = "arm,armv8-pmuv3"; 83 interrupts = <0 170 4>, 84 <0 171 4>, 85 <0 172 4>, 86 <0 173 4>; 87 interrupt-affinity = <&cpu0>, 88 <&cpu1>, 89 <&cpu2>, 90 <&cpu3>; 91 interrupt-parent = <&intc>; 92 }; 93 94 psci { 95 compatible = "arm,psci-0.2"; 96 method = "smc"; 97 }; 98 99 /* Local timer */ 100 timer { 101 compatible = "arm,armv8-timer"; 102 interrupts = <1 13 0xf08>, 103 <1 14 0xf08>, 104 <1 11 0xf08>, 105 <1 10 0xf08>; 106 interrupt-parent = <&intc>; 107 }; 108 109 intc: interrupt-controller@fffc1000 { 110 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 111 #interrupt-cells = <3>; 112 interrupt-controller; 113 reg = <0x0 0xfffc1000 0x0 0x1000>, 114 <0x0 0xfffc2000 0x0 0x2000>, 115 <0x0 0xfffc4000 0x0 0x2000>, 116 <0x0 0xfffc6000 0x0 0x2000>; 117 }; 118 119 clocks { 120 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 121 #clock-cells = <0>; 122 compatible = "fixed-clock"; 123 }; 124 125 cb_intosc_ls_clk: cb-intosc-ls-clk { 126 #clock-cells = <0>; 127 compatible = "fixed-clock"; 128 }; 129 130 f2s_free_clk: f2s-free-clk { 131 #clock-cells = <0>; 132 compatible = "fixed-clock"; 133 }; 134 135 osc1: osc1 { 136 #clock-cells = <0>; 137 compatible = "fixed-clock"; 138 }; 139 140 qspi_clk: qspi-clk { 141 #clock-cells = <0>; 142 compatible = "fixed-clock"; 143 clock-frequency = <200000000>; 144 }; 145 }; 146 147 soc@0 { 148 #address-cells = <1>; 149 #size-cells = <1>; 150 compatible = "simple-bus"; 151 device_type = "soc"; 152 interrupt-parent = <&intc>; 153 ranges = <0 0 0 0xffffffff>; 154 155 clkmgr: clock-controller@ffd10000 { 156 compatible = "intel,stratix10-clkmgr"; 157 reg = <0xffd10000 0x1000>; 158 #clock-cells = <1>; 159 }; 160 161 gmac0: ethernet@ff800000 { 162 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 163 reg = <0xff800000 0x2000>; 164 interrupts = <0 90 4>; 165 interrupt-names = "macirq"; 166 mac-address = [00 00 00 00 00 00]; 167 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 168 reset-names = "stmmaceth", "ahb"; 169 clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; 170 clock-names = "stmmaceth", "ptp_ref"; 171 tx-fifo-depth = <16384>; 172 rx-fifo-depth = <16384>; 173 snps,multicast-filter-bins = <256>; 174 iommus = <&smmu 1>; 175 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 176 status = "disabled"; 177 }; 178 179 gmac1: ethernet@ff802000 { 180 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 181 reg = <0xff802000 0x2000>; 182 interrupts = <0 91 4>; 183 interrupt-names = "macirq"; 184 mac-address = [00 00 00 00 00 00]; 185 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 186 reset-names = "stmmaceth", "ahb"; 187 clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; 188 clock-names = "stmmaceth", "ptp_ref"; 189 tx-fifo-depth = <16384>; 190 rx-fifo-depth = <16384>; 191 snps,multicast-filter-bins = <256>; 192 iommus = <&smmu 2>; 193 altr,sysmgr-syscon = <&sysmgr 0x48 8>; 194 status = "disabled"; 195 }; 196 197 gmac2: ethernet@ff804000 { 198 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 199 reg = <0xff804000 0x2000>; 200 interrupts = <0 92 4>; 201 interrupt-names = "macirq"; 202 mac-address = [00 00 00 00 00 00]; 203 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 204 reset-names = "stmmaceth", "ahb"; 205 clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; 206 clock-names = "stmmaceth", "ptp_ref"; 207 tx-fifo-depth = <16384>; 208 rx-fifo-depth = <16384>; 209 snps,multicast-filter-bins = <256>; 210 iommus = <&smmu 3>; 211 altr,sysmgr-syscon = <&sysmgr 0x4c 16>; 212 status = "disabled"; 213 }; 214 215 gpio0: gpio@ffc03200 { 216 #address-cells = <1>; 217 #size-cells = <0>; 218 compatible = "snps,dw-apb-gpio"; 219 reg = <0xffc03200 0x100>; 220 resets = <&rst GPIO0_RESET>; 221 status = "disabled"; 222 223 porta: gpio-controller@0 { 224 compatible = "snps,dw-apb-gpio-port"; 225 gpio-controller; 226 #gpio-cells = <2>; 227 ngpios = <24>; 228 reg = <0>; 229 interrupt-controller; 230 #interrupt-cells = <2>; 231 interrupts = <0 110 4>; 232 }; 233 }; 234 235 gpio1: gpio@ffc03300 { 236 #address-cells = <1>; 237 #size-cells = <0>; 238 compatible = "snps,dw-apb-gpio"; 239 reg = <0xffc03300 0x100>; 240 resets = <&rst GPIO1_RESET>; 241 status = "disabled"; 242 243 portb: gpio-controller@0 { 244 compatible = "snps,dw-apb-gpio-port"; 245 gpio-controller; 246 #gpio-cells = <2>; 247 ngpios = <24>; 248 reg = <0>; 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 interrupts = <0 111 4>; 252 }; 253 }; 254 255 i2c0: i2c@ffc02800 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 compatible = "snps,designware-i2c"; 259 reg = <0xffc02800 0x100>; 260 interrupts = <0 103 4>; 261 resets = <&rst I2C0_RESET>; 262 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 263 status = "disabled"; 264 }; 265 266 i2c1: i2c@ffc02900 { 267 #address-cells = <1>; 268 #size-cells = <0>; 269 compatible = "snps,designware-i2c"; 270 reg = <0xffc02900 0x100>; 271 interrupts = <0 104 4>; 272 resets = <&rst I2C1_RESET>; 273 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 274 status = "disabled"; 275 }; 276 277 i2c2: i2c@ffc02a00 { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 compatible = "snps,designware-i2c"; 281 reg = <0xffc02a00 0x100>; 282 interrupts = <0 105 4>; 283 resets = <&rst I2C2_RESET>; 284 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 285 status = "disabled"; 286 }; 287 288 i2c3: i2c@ffc02b00 { 289 #address-cells = <1>; 290 #size-cells = <0>; 291 compatible = "snps,designware-i2c"; 292 reg = <0xffc02b00 0x100>; 293 interrupts = <0 106 4>; 294 resets = <&rst I2C3_RESET>; 295 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 296 status = "disabled"; 297 }; 298 299 i2c4: i2c@ffc02c00 { 300 #address-cells = <1>; 301 #size-cells = <0>; 302 compatible = "snps,designware-i2c"; 303 reg = <0xffc02c00 0x100>; 304 interrupts = <0 107 4>; 305 resets = <&rst I2C4_RESET>; 306 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 307 status = "disabled"; 308 }; 309 310 mmc: mmc@ff808000 { 311 #address-cells = <1>; 312 #size-cells = <0>; 313 compatible = "altr,socfpga-dw-mshc"; 314 reg = <0xff808000 0x1000>; 315 interrupts = <0 96 4>; 316 fifo-depth = <0x400>; 317 resets = <&rst SDMMC_RESET>; 318 reset-names = "reset"; 319 clocks = <&clkmgr STRATIX10_L4_MP_CLK>, 320 <&clkmgr STRATIX10_SDMMC_CLK>; 321 clock-names = "biu", "ciu"; 322 iommus = <&smmu 5>; 323 altr,sysmgr-syscon = <&sysmgr 0x28 4>; 324 status = "disabled"; 325 }; 326 327 nand: nand-controller@ffb90000 { 328 #address-cells = <1>; 329 #size-cells = <0>; 330 compatible = "altr,socfpga-denali-nand"; 331 reg = <0xffb90000 0x10000>, 332 <0xffb80000 0x1000>; 333 reg-names = "nand_data", "denali_reg"; 334 interrupts = <0 97 4>; 335 clocks = <&clkmgr STRATIX10_NAND_CLK>, 336 <&clkmgr STRATIX10_NAND_X_CLK>, 337 <&clkmgr STRATIX10_NAND_ECC_CLK>; 338 clock-names = "nand", "nand_x", "ecc"; 339 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; 340 status = "disabled"; 341 }; 342 343 ocram: sram@ffe00000 { 344 compatible = "mmio-sram"; 345 reg = <0xffe00000 0x100000>; 346 #address-cells = <1>; 347 #size-cells = <1>; 348 ranges = <0 0xffe00000 0x100000>; 349 }; 350 351 pdma: dma-controller@ffda0000 { 352 compatible = "arm,pl330", "arm,primecell"; 353 reg = <0xffda0000 0x1000>; 354 interrupts = <0 81 4>, 355 <0 82 4>, 356 <0 83 4>, 357 <0 84 4>, 358 <0 85 4>, 359 <0 86 4>, 360 <0 87 4>, 361 <0 88 4>, 362 <0 89 4>; 363 #dma-cells = <1>; 364 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 365 clock-names = "apb_pclk"; 366 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 367 reset-names = "dma", "dma-ocp"; 368 }; 369 370 pinctrl0: pinctrl@ffd13000 { 371 compatible = "pinctrl-single"; 372 reg = <0xffd13000 0xA0>; 373 #pinctrl-cells = <1>; 374 pinctrl-single,register-width = <32>; 375 pinctrl-single,function-mask = <0x0000000f>; 376 }; 377 378 pinctrl1: pinctrl@ffd13100 { 379 compatible = "pinctrl-single"; 380 reg = <0xffd13100 0x20>; 381 #pinctrl-cells = <1>; 382 pinctrl-single,register-width = <32>; 383 pinctrl-single,function-mask = <0x0000000f>; 384 }; 385 386 rst: rstmgr@ffd11000 { 387 #reset-cells = <1>; 388 compatible = "altr,stratix10-rst-mgr"; 389 reg = <0xffd11000 0x1000>; 390 }; 391 392 smmu: iommu@fa000000 { 393 compatible = "arm,mmu-500", "arm,smmu-v2"; 394 reg = <0xfa000000 0x40000>; 395 #global-interrupts = <2>; 396 #iommu-cells = <1>; 397 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 398 clock-names = "iommu"; 399 interrupt-parent = <&intc>; 400 interrupts = <0 128 4>, /* Global Secure Fault */ 401 <0 129 4>, /* Global Non-secure Fault */ 402 /* Non-secure Context Interrupts (32) */ 403 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, 404 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, 405 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, 406 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, 407 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, 408 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, 409 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, 410 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; 411 stream-match-mask = <0x7ff0>; 412 status = "disabled"; 413 }; 414 415 spi0: spi@ffda4000 { 416 compatible = "snps,dw-apb-ssi"; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 reg = <0xffda4000 0x1000>; 420 interrupts = <0 99 4>; 421 resets = <&rst SPIM0_RESET>; 422 reset-names = "spi"; 423 reg-io-width = <4>; 424 num-cs = <4>; 425 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 426 status = "disabled"; 427 }; 428 429 spi1: spi@ffda5000 { 430 compatible = "snps,dw-apb-ssi"; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 reg = <0xffda5000 0x1000>; 434 interrupts = <0 100 4>; 435 resets = <&rst SPIM1_RESET>; 436 reset-names = "spi"; 437 reg-io-width = <4>; 438 num-cs = <4>; 439 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 440 status = "disabled"; 441 }; 442 443 sysmgr: sysmgr@ffd12000 { 444 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 445 reg = <0xffd12000 0x228>; 446 }; 447 448 timer0: timer0@ffc03000 { 449 compatible = "snps,dw-apb-timer"; 450 interrupts = <0 113 4>; 451 reg = <0xffc03000 0x100>; 452 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 453 clock-names = "timer"; 454 }; 455 456 timer1: timer1@ffc03100 { 457 compatible = "snps,dw-apb-timer"; 458 interrupts = <0 114 4>; 459 reg = <0xffc03100 0x100>; 460 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 461 clock-names = "timer"; 462 }; 463 464 timer2: timer2@ffd00000 { 465 compatible = "snps,dw-apb-timer"; 466 interrupts = <0 115 4>; 467 reg = <0xffd00000 0x100>; 468 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 469 clock-names = "timer"; 470 }; 471 472 timer3: timer3@ffd00100 { 473 compatible = "snps,dw-apb-timer"; 474 interrupts = <0 116 4>; 475 reg = <0xffd00100 0x100>; 476 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 477 clock-names = "timer"; 478 }; 479 480 uart0: serial@ffc02000 { 481 compatible = "snps,dw-apb-uart"; 482 reg = <0xffc02000 0x100>; 483 interrupts = <0 108 4>; 484 reg-shift = <2>; 485 reg-io-width = <4>; 486 resets = <&rst UART0_RESET>; 487 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 488 status = "disabled"; 489 }; 490 491 uart1: serial@ffc02100 { 492 compatible = "snps,dw-apb-uart"; 493 reg = <0xffc02100 0x100>; 494 interrupts = <0 109 4>; 495 reg-shift = <2>; 496 reg-io-width = <4>; 497 resets = <&rst UART1_RESET>; 498 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 499 status = "disabled"; 500 }; 501 502 usb0: usb@ffb00000 { 503 compatible = "snps,dwc2"; 504 reg = <0xffb00000 0x40000>; 505 interrupts = <0 93 4>; 506 phys = <&usbphy0>; 507 phy-names = "usb2-phy"; 508 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 509 reset-names = "dwc2", "dwc2-ecc"; 510 clocks = <&clkmgr STRATIX10_USB_CLK>; 511 clock-names = "otg"; 512 iommus = <&smmu 6>; 513 status = "disabled"; 514 }; 515 516 usb1: usb@ffb40000 { 517 compatible = "snps,dwc2"; 518 reg = <0xffb40000 0x40000>; 519 interrupts = <0 94 4>; 520 phys = <&usbphy0>; 521 phy-names = "usb2-phy"; 522 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 523 reset-names = "dwc2", "dwc2-ecc"; 524 clocks = <&clkmgr STRATIX10_USB_CLK>; 525 clock-names = "otg"; 526 iommus = <&smmu 7>; 527 status = "disabled"; 528 }; 529 530 watchdog0: watchdog@ffd00200 { 531 compatible = "snps,dw-wdt"; 532 reg = <0xffd00200 0x100>; 533 interrupts = <0 117 4>; 534 resets = <&rst WATCHDOG0_RESET>; 535 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 536 status = "disabled"; 537 }; 538 539 watchdog1: watchdog@ffd00300 { 540 compatible = "snps,dw-wdt"; 541 reg = <0xffd00300 0x100>; 542 interrupts = <0 118 4>; 543 resets = <&rst WATCHDOG1_RESET>; 544 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 545 status = "disabled"; 546 }; 547 548 watchdog2: watchdog@ffd00400 { 549 compatible = "snps,dw-wdt"; 550 reg = <0xffd00400 0x100>; 551 interrupts = <0 125 4>; 552 resets = <&rst WATCHDOG2_RESET>; 553 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 554 status = "disabled"; 555 }; 556 557 watchdog3: watchdog@ffd00500 { 558 compatible = "snps,dw-wdt"; 559 reg = <0xffd00500 0x100>; 560 interrupts = <0 126 4>; 561 resets = <&rst WATCHDOG3_RESET>; 562 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 563 status = "disabled"; 564 }; 565 566 sdr: sdr@f8011100 { 567 compatible = "altr,sdr-ctl", "syscon"; 568 reg = <0xf8011100 0xc0>; 569 }; 570 571 eccmgr { 572 compatible = "altr,socfpga-s10-ecc-manager", 573 "altr,socfpga-a10-ecc-manager"; 574 altr,sysmgr-syscon = <&sysmgr>; 575 #address-cells = <1>; 576 #size-cells = <1>; 577 interrupts = <0 15 4>; 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 ranges; 581 582 sdramedac { 583 compatible = "altr,sdram-edac-s10"; 584 altr,sdr-syscon = <&sdr>; 585 interrupts = <16 4>; 586 }; 587 588 ocram-ecc@ff8cc000 { 589 compatible = "altr,socfpga-s10-ocram-ecc", 590 "altr,socfpga-a10-ocram-ecc"; 591 reg = <0xff8cc000 0x100>; 592 altr,ecc-parent = <&ocram>; 593 interrupts = <1 4>; 594 }; 595 596 usb0-ecc@ff8c4000 { 597 compatible = "altr,socfpga-s10-usb-ecc", 598 "altr,socfpga-usb-ecc"; 599 reg = <0xff8c4000 0x100>; 600 altr,ecc-parent = <&usb0>; 601 interrupts = <2 4>; 602 }; 603 604 emac0-rx-ecc@ff8c0000 { 605 compatible = "altr,socfpga-s10-eth-mac-ecc", 606 "altr,socfpga-eth-mac-ecc"; 607 reg = <0xff8c0000 0x100>; 608 altr,ecc-parent = <&gmac0>; 609 interrupts = <4 4>; 610 }; 611 612 emac0-tx-ecc@ff8c0400 { 613 compatible = "altr,socfpga-s10-eth-mac-ecc", 614 "altr,socfpga-eth-mac-ecc"; 615 reg = <0xff8c0400 0x100>; 616 altr,ecc-parent = <&gmac0>; 617 interrupts = <5 4>; 618 }; 619 620 }; 621 622 qspi: spi@ff8d2000 { 623 compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 reg = <0xff8d2000 0x100>, 627 <0xff900000 0x100000>; 628 interrupts = <0 3 4>; 629 cdns,fifo-depth = <128>; 630 cdns,fifo-width = <4>; 631 cdns,trigger-address = <0x00000000>; 632 clocks = <&qspi_clk>; 633 634 status = "disabled"; 635 }; 636 }; 637 638 usbphy0: usbphy0 { 639 compatible = "usb-nop-xceiv"; 640 #phy-cells = <0>; 641 }; 642}; 643