1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2020 Arm Ltd. 3// based on the H6 dtsi, which is: 4// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-h616-ccu.h> 8#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 9#include <dt-bindings/clock/sun6i-rtc.h> 10#include <dt-bindings/reset/sun50i-h616-ccu.h> 11#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 12 13/ { 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 compatible = "arm,cortex-a53"; 24 device_type = "cpu"; 25 reg = <0>; 26 enable-method = "psci"; 27 clocks = <&ccu CLK_CPUX>; 28 }; 29 30 cpu1: cpu@1 { 31 compatible = "arm,cortex-a53"; 32 device_type = "cpu"; 33 reg = <1>; 34 enable-method = "psci"; 35 clocks = <&ccu CLK_CPUX>; 36 }; 37 38 cpu2: cpu@2 { 39 compatible = "arm,cortex-a53"; 40 device_type = "cpu"; 41 reg = <2>; 42 enable-method = "psci"; 43 clocks = <&ccu CLK_CPUX>; 44 }; 45 46 cpu3: cpu@3 { 47 compatible = "arm,cortex-a53"; 48 device_type = "cpu"; 49 reg = <3>; 50 enable-method = "psci"; 51 clocks = <&ccu CLK_CPUX>; 52 }; 53 }; 54 55 reserved-memory { 56 #address-cells = <2>; 57 #size-cells = <2>; 58 ranges; 59 60 /* 61 * 256 KiB reserved for Trusted Firmware-A (BL31). 62 * This is added by BL31 itself, but some bootloaders fail 63 * to propagate this into the DTB handed to kernels. 64 */ 65 secmon@40000000 { 66 reg = <0x0 0x40000000 0x0 0x40000>; 67 no-map; 68 }; 69 }; 70 71 osc24M: osc24M-clk { 72 #clock-cells = <0>; 73 compatible = "fixed-clock"; 74 clock-frequency = <24000000>; 75 clock-output-names = "osc24M"; 76 }; 77 78 pmu { 79 compatible = "arm,cortex-a53-pmu"; 80 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 85 }; 86 87 psci { 88 compatible = "arm,psci-0.2"; 89 method = "smc"; 90 }; 91 92 timer { 93 compatible = "arm,armv8-timer"; 94 arm,no-tick-in-suspend; 95 interrupts = <GIC_PPI 13 96 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 97 <GIC_PPI 14 98 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 99 <GIC_PPI 11 100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 101 <GIC_PPI 10 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 103 }; 104 105 soc { 106 compatible = "simple-bus"; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges = <0x0 0x0 0x0 0x40000000>; 110 111 syscon: syscon@3000000 { 112 compatible = "allwinner,sun50i-h616-system-control"; 113 reg = <0x03000000 0x1000>; 114 #address-cells = <1>; 115 #size-cells = <1>; 116 ranges; 117 118 sram_c: sram@28000 { 119 compatible = "mmio-sram"; 120 reg = <0x00028000 0x30000>; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges = <0 0x00028000 0x30000>; 124 }; 125 }; 126 127 ccu: clock@3001000 { 128 compatible = "allwinner,sun50i-h616-ccu"; 129 reg = <0x03001000 0x1000>; 130 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; 131 clock-names = "hosc", "losc", "iosc"; 132 #clock-cells = <1>; 133 #reset-cells = <1>; 134 }; 135 136 sid: efuse@3006000 { 137 compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; 138 reg = <0x03006000 0x1000>; 139 #address-cells = <1>; 140 #size-cells = <1>; 141 }; 142 143 watchdog: watchdog@30090a0 { 144 compatible = "allwinner,sun50i-h616-wdt", 145 "allwinner,sun6i-a31-wdt"; 146 reg = <0x030090a0 0x20>; 147 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&osc24M>; 149 }; 150 151 pio: pinctrl@300b000 { 152 compatible = "allwinner,sun50i-h616-pinctrl"; 153 reg = <0x0300b000 0x400>; 154 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 163 clock-names = "apb", "hosc", "losc"; 164 gpio-controller; 165 #gpio-cells = <3>; 166 interrupt-controller; 167 #interrupt-cells = <3>; 168 169 ext_rgmii_pins: rgmii-pins { 170 pins = "PI0", "PI1", "PI2", "PI3", "PI4", 171 "PI5", "PI7", "PI8", "PI9", "PI10", 172 "PI11", "PI12", "PI13", "PI14", "PI15", 173 "PI16"; 174 function = "emac0"; 175 drive-strength = <40>; 176 }; 177 178 i2c0_pins: i2c0-pins { 179 pins = "PI6", "PI7"; 180 function = "i2c0"; 181 }; 182 183 i2c3_ph_pins: i2c3-ph-pins { 184 pins = "PH4", "PH5"; 185 function = "i2c3"; 186 }; 187 188 ir_rx_pin: ir-rx-pin { 189 pins = "PH10"; 190 function = "ir_rx"; 191 }; 192 193 mmc0_pins: mmc0-pins { 194 pins = "PF0", "PF1", "PF2", "PF3", 195 "PF4", "PF5"; 196 function = "mmc0"; 197 drive-strength = <30>; 198 bias-pull-up; 199 }; 200 201 /omit-if-no-ref/ 202 mmc1_pins: mmc1-pins { 203 pins = "PG0", "PG1", "PG2", "PG3", 204 "PG4", "PG5"; 205 function = "mmc1"; 206 drive-strength = <30>; 207 bias-pull-up; 208 }; 209 210 mmc2_pins: mmc2-pins { 211 pins = "PC0", "PC1", "PC5", "PC6", 212 "PC8", "PC9", "PC10", "PC11", 213 "PC13", "PC14", "PC15", "PC16"; 214 function = "mmc2"; 215 drive-strength = <30>; 216 bias-pull-up; 217 }; 218 219 /omit-if-no-ref/ 220 spi0_pins: spi0-pins { 221 pins = "PC0", "PC2", "PC4"; 222 function = "spi0"; 223 }; 224 225 /omit-if-no-ref/ 226 spi0_cs0_pin: spi0-cs0-pin { 227 pins = "PC3"; 228 function = "spi0"; 229 }; 230 231 /omit-if-no-ref/ 232 spi1_pins: spi1-pins { 233 pins = "PH6", "PH7", "PH8"; 234 function = "spi1"; 235 }; 236 237 /omit-if-no-ref/ 238 spi1_cs0_pin: spi1-cs0-pin { 239 pins = "PH5"; 240 function = "spi1"; 241 }; 242 243 uart0_ph_pins: uart0-ph-pins { 244 pins = "PH0", "PH1"; 245 function = "uart0"; 246 }; 247 248 /omit-if-no-ref/ 249 uart1_pins: uart1-pins { 250 pins = "PG6", "PG7"; 251 function = "uart1"; 252 }; 253 254 /omit-if-no-ref/ 255 uart1_rts_cts_pins: uart1-rts-cts-pins { 256 pins = "PG8", "PG9"; 257 function = "uart1"; 258 }; 259 }; 260 261 gic: interrupt-controller@3021000 { 262 compatible = "arm,gic-400"; 263 reg = <0x03021000 0x1000>, 264 <0x03022000 0x2000>, 265 <0x03024000 0x2000>, 266 <0x03026000 0x2000>; 267 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 268 interrupt-controller; 269 #interrupt-cells = <3>; 270 }; 271 272 mmc0: mmc@4020000 { 273 compatible = "allwinner,sun50i-h616-mmc", 274 "allwinner,sun50i-a100-mmc"; 275 reg = <0x04020000 0x1000>; 276 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 277 clock-names = "ahb", "mmc"; 278 resets = <&ccu RST_BUS_MMC0>; 279 reset-names = "ahb"; 280 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&mmc0_pins>; 283 status = "disabled"; 284 max-frequency = <150000000>; 285 cap-sd-highspeed; 286 cap-mmc-highspeed; 287 mmc-ddr-3_3v; 288 cap-sdio-irq; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 }; 292 293 mmc1: mmc@4021000 { 294 compatible = "allwinner,sun50i-h616-mmc", 295 "allwinner,sun50i-a100-mmc"; 296 reg = <0x04021000 0x1000>; 297 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 298 clock-names = "ahb", "mmc"; 299 resets = <&ccu RST_BUS_MMC1>; 300 reset-names = "ahb"; 301 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&mmc1_pins>; 304 status = "disabled"; 305 max-frequency = <150000000>; 306 cap-sd-highspeed; 307 cap-mmc-highspeed; 308 mmc-ddr-3_3v; 309 cap-sdio-irq; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 }; 313 314 mmc2: mmc@4022000 { 315 compatible = "allwinner,sun50i-h616-emmc", 316 "allwinner,sun50i-a100-emmc"; 317 reg = <0x04022000 0x1000>; 318 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 319 clock-names = "ahb", "mmc"; 320 resets = <&ccu RST_BUS_MMC2>; 321 reset-names = "ahb"; 322 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&mmc2_pins>; 325 status = "disabled"; 326 max-frequency = <150000000>; 327 cap-sd-highspeed; 328 cap-mmc-highspeed; 329 mmc-ddr-3_3v; 330 cap-sdio-irq; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 }; 334 335 uart0: serial@5000000 { 336 compatible = "snps,dw-apb-uart"; 337 reg = <0x05000000 0x400>; 338 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 339 reg-shift = <2>; 340 reg-io-width = <4>; 341 clocks = <&ccu CLK_BUS_UART0>; 342 resets = <&ccu RST_BUS_UART0>; 343 status = "disabled"; 344 }; 345 346 uart1: serial@5000400 { 347 compatible = "snps,dw-apb-uart"; 348 reg = <0x05000400 0x400>; 349 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 350 reg-shift = <2>; 351 reg-io-width = <4>; 352 clocks = <&ccu CLK_BUS_UART1>; 353 resets = <&ccu RST_BUS_UART1>; 354 status = "disabled"; 355 }; 356 357 uart2: serial@5000800 { 358 compatible = "snps,dw-apb-uart"; 359 reg = <0x05000800 0x400>; 360 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 361 reg-shift = <2>; 362 reg-io-width = <4>; 363 clocks = <&ccu CLK_BUS_UART2>; 364 resets = <&ccu RST_BUS_UART2>; 365 status = "disabled"; 366 }; 367 368 uart3: serial@5000c00 { 369 compatible = "snps,dw-apb-uart"; 370 reg = <0x05000c00 0x400>; 371 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 372 reg-shift = <2>; 373 reg-io-width = <4>; 374 clocks = <&ccu CLK_BUS_UART3>; 375 resets = <&ccu RST_BUS_UART3>; 376 status = "disabled"; 377 }; 378 379 uart4: serial@5001000 { 380 compatible = "snps,dw-apb-uart"; 381 reg = <0x05001000 0x400>; 382 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 383 reg-shift = <2>; 384 reg-io-width = <4>; 385 clocks = <&ccu CLK_BUS_UART4>; 386 resets = <&ccu RST_BUS_UART4>; 387 status = "disabled"; 388 }; 389 390 uart5: serial@5001400 { 391 compatible = "snps,dw-apb-uart"; 392 reg = <0x05001400 0x400>; 393 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 394 reg-shift = <2>; 395 reg-io-width = <4>; 396 clocks = <&ccu CLK_BUS_UART5>; 397 resets = <&ccu RST_BUS_UART5>; 398 status = "disabled"; 399 }; 400 401 i2c0: i2c@5002000 { 402 compatible = "allwinner,sun50i-h616-i2c", 403 "allwinner,sun8i-v536-i2c", 404 "allwinner,sun6i-a31-i2c"; 405 reg = <0x05002000 0x400>; 406 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&ccu CLK_BUS_I2C0>; 408 resets = <&ccu RST_BUS_I2C0>; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&i2c0_pins>; 411 status = "disabled"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 }; 415 416 i2c1: i2c@5002400 { 417 compatible = "allwinner,sun50i-h616-i2c", 418 "allwinner,sun8i-v536-i2c", 419 "allwinner,sun6i-a31-i2c"; 420 reg = <0x05002400 0x400>; 421 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&ccu CLK_BUS_I2C1>; 423 resets = <&ccu RST_BUS_I2C1>; 424 status = "disabled"; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 }; 428 429 i2c2: i2c@5002800 { 430 compatible = "allwinner,sun50i-h616-i2c", 431 "allwinner,sun8i-v536-i2c", 432 "allwinner,sun6i-a31-i2c"; 433 reg = <0x05002800 0x400>; 434 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&ccu CLK_BUS_I2C2>; 436 resets = <&ccu RST_BUS_I2C2>; 437 status = "disabled"; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 }; 441 442 i2c3: i2c@5002c00 { 443 compatible = "allwinner,sun50i-h616-i2c", 444 "allwinner,sun8i-v536-i2c", 445 "allwinner,sun6i-a31-i2c"; 446 reg = <0x05002c00 0x400>; 447 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&ccu CLK_BUS_I2C3>; 449 resets = <&ccu RST_BUS_I2C3>; 450 status = "disabled"; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 }; 454 455 i2c4: i2c@5003000 { 456 compatible = "allwinner,sun50i-h616-i2c", 457 "allwinner,sun8i-v536-i2c", 458 "allwinner,sun6i-a31-i2c"; 459 reg = <0x05003000 0x400>; 460 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&ccu CLK_BUS_I2C4>; 462 resets = <&ccu RST_BUS_I2C4>; 463 status = "disabled"; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 }; 467 468 spi0: spi@5010000 { 469 compatible = "allwinner,sun50i-h616-spi", 470 "allwinner,sun8i-h3-spi"; 471 reg = <0x05010000 0x1000>; 472 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 474 clock-names = "ahb", "mod"; 475 resets = <&ccu RST_BUS_SPI0>; 476 status = "disabled"; 477 #address-cells = <1>; 478 #size-cells = <0>; 479 }; 480 481 spi1: spi@5011000 { 482 compatible = "allwinner,sun50i-h616-spi", 483 "allwinner,sun8i-h3-spi"; 484 reg = <0x05011000 0x1000>; 485 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 487 clock-names = "ahb", "mod"; 488 resets = <&ccu RST_BUS_SPI1>; 489 status = "disabled"; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 }; 493 494 emac0: ethernet@5020000 { 495 compatible = "allwinner,sun50i-h616-emac0", 496 "allwinner,sun50i-a64-emac"; 497 reg = <0x05020000 0x10000>; 498 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 499 interrupt-names = "macirq"; 500 clocks = <&ccu CLK_BUS_EMAC0>; 501 clock-names = "stmmaceth"; 502 resets = <&ccu RST_BUS_EMAC0>; 503 reset-names = "stmmaceth"; 504 syscon = <&syscon>; 505 status = "disabled"; 506 507 mdio0: mdio { 508 compatible = "snps,dwmac-mdio"; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 }; 512 }; 513 514 usbotg: usb@5100000 { 515 compatible = "allwinner,sun50i-h616-musb", 516 "allwinner,sun8i-h3-musb"; 517 reg = <0x05100000 0x0400>; 518 clocks = <&ccu CLK_BUS_OTG>; 519 resets = <&ccu RST_BUS_OTG>; 520 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 521 interrupt-names = "mc"; 522 phys = <&usbphy 0>; 523 phy-names = "usb"; 524 extcon = <&usbphy 0>; 525 status = "disabled"; 526 }; 527 528 usbphy: phy@5100400 { 529 compatible = "allwinner,sun50i-h616-usb-phy"; 530 reg = <0x05100400 0x24>, 531 <0x05101800 0x14>, 532 <0x05200800 0x14>, 533 <0x05310800 0x14>, 534 <0x05311800 0x14>; 535 reg-names = "phy_ctrl", 536 "pmu0", 537 "pmu1", 538 "pmu2", 539 "pmu3"; 540 clocks = <&ccu CLK_USB_PHY0>, 541 <&ccu CLK_USB_PHY1>, 542 <&ccu CLK_USB_PHY2>, 543 <&ccu CLK_USB_PHY3>, 544 <&ccu CLK_BUS_EHCI2>; 545 clock-names = "usb0_phy", 546 "usb1_phy", 547 "usb2_phy", 548 "usb3_phy", 549 "pmu2_clk"; 550 resets = <&ccu RST_USB_PHY0>, 551 <&ccu RST_USB_PHY1>, 552 <&ccu RST_USB_PHY2>, 553 <&ccu RST_USB_PHY3>; 554 reset-names = "usb0_reset", 555 "usb1_reset", 556 "usb2_reset", 557 "usb3_reset"; 558 status = "disabled"; 559 #phy-cells = <1>; 560 }; 561 562 ehci0: usb@5101000 { 563 compatible = "allwinner,sun50i-h616-ehci", 564 "generic-ehci"; 565 reg = <0x05101000 0x100>; 566 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&ccu CLK_BUS_OHCI0>, 568 <&ccu CLK_BUS_EHCI0>, 569 <&ccu CLK_USB_OHCI0>; 570 resets = <&ccu RST_BUS_OHCI0>, 571 <&ccu RST_BUS_EHCI0>; 572 phys = <&usbphy 0>; 573 phy-names = "usb"; 574 status = "disabled"; 575 }; 576 577 ohci0: usb@5101400 { 578 compatible = "allwinner,sun50i-h616-ohci", 579 "generic-ohci"; 580 reg = <0x05101400 0x100>; 581 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&ccu CLK_BUS_OHCI0>, 583 <&ccu CLK_USB_OHCI0>; 584 resets = <&ccu RST_BUS_OHCI0>; 585 phys = <&usbphy 0>; 586 phy-names = "usb"; 587 status = "disabled"; 588 }; 589 590 ehci1: usb@5200000 { 591 compatible = "allwinner,sun50i-h616-ehci", 592 "generic-ehci"; 593 reg = <0x05200000 0x100>; 594 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&ccu CLK_BUS_OHCI1>, 596 <&ccu CLK_BUS_EHCI1>, 597 <&ccu CLK_USB_OHCI1>; 598 resets = <&ccu RST_BUS_OHCI1>, 599 <&ccu RST_BUS_EHCI1>; 600 phys = <&usbphy 1>; 601 phy-names = "usb"; 602 status = "disabled"; 603 }; 604 605 ohci1: usb@5200400 { 606 compatible = "allwinner,sun50i-h616-ohci", 607 "generic-ohci"; 608 reg = <0x05200400 0x100>; 609 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&ccu CLK_BUS_OHCI1>, 611 <&ccu CLK_USB_OHCI1>; 612 resets = <&ccu RST_BUS_OHCI1>; 613 phys = <&usbphy 1>; 614 phy-names = "usb"; 615 status = "disabled"; 616 }; 617 618 ehci2: usb@5310000 { 619 compatible = "allwinner,sun50i-h616-ehci", 620 "generic-ehci"; 621 reg = <0x05310000 0x100>; 622 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&ccu CLK_BUS_OHCI2>, 624 <&ccu CLK_BUS_EHCI2>, 625 <&ccu CLK_USB_OHCI2>; 626 resets = <&ccu RST_BUS_OHCI2>, 627 <&ccu RST_BUS_EHCI2>; 628 phys = <&usbphy 2>; 629 phy-names = "usb"; 630 status = "disabled"; 631 }; 632 633 ohci2: usb@5310400 { 634 compatible = "allwinner,sun50i-h616-ohci", 635 "generic-ohci"; 636 reg = <0x05310400 0x100>; 637 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&ccu CLK_BUS_OHCI2>, 639 <&ccu CLK_USB_OHCI2>; 640 resets = <&ccu RST_BUS_OHCI2>; 641 phys = <&usbphy 2>; 642 phy-names = "usb"; 643 status = "disabled"; 644 }; 645 646 ehci3: usb@5311000 { 647 compatible = "allwinner,sun50i-h616-ehci", 648 "generic-ehci"; 649 reg = <0x05311000 0x100>; 650 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&ccu CLK_BUS_OHCI3>, 652 <&ccu CLK_BUS_EHCI3>, 653 <&ccu CLK_USB_OHCI3>; 654 resets = <&ccu RST_BUS_OHCI3>, 655 <&ccu RST_BUS_EHCI3>; 656 phys = <&usbphy 3>; 657 phy-names = "usb"; 658 status = "disabled"; 659 }; 660 661 ohci3: usb@5311400 { 662 compatible = "allwinner,sun50i-h616-ohci", 663 "generic-ohci"; 664 reg = <0x05311400 0x100>; 665 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&ccu CLK_BUS_OHCI3>, 667 <&ccu CLK_USB_OHCI3>; 668 resets = <&ccu RST_BUS_OHCI3>; 669 phys = <&usbphy 3>; 670 phy-names = "usb"; 671 status = "disabled"; 672 }; 673 674 rtc: rtc@7000000 { 675 compatible = "allwinner,sun50i-h616-rtc"; 676 reg = <0x07000000 0x400>; 677 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, 679 <&ccu CLK_PLL_SYSTEM_32K>; 680 clock-names = "bus", "hosc", 681 "pll-32k"; 682 #clock-cells = <1>; 683 }; 684 685 r_ccu: clock@7010000 { 686 compatible = "allwinner,sun50i-h616-r-ccu"; 687 reg = <0x07010000 0x210>; 688 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 689 <&ccu CLK_PLL_PERIPH0>; 690 clock-names = "hosc", "losc", "iosc", "pll-periph"; 691 #clock-cells = <1>; 692 #reset-cells = <1>; 693 }; 694 695 r_pio: pinctrl@7022000 { 696 compatible = "allwinner,sun50i-h616-r-pinctrl"; 697 reg = <0x07022000 0x400>; 698 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, 699 <&rtc CLK_OSC32K>; 700 clock-names = "apb", "hosc", "losc"; 701 gpio-controller; 702 #gpio-cells = <3>; 703 704 /omit-if-no-ref/ 705 r_i2c_pins: r-i2c-pins { 706 pins = "PL0", "PL1"; 707 function = "s_i2c"; 708 }; 709 710 r_rsb_pins: r-rsb-pins { 711 pins = "PL0", "PL1"; 712 function = "s_rsb"; 713 }; 714 }; 715 716 ir: ir@7040000 { 717 compatible = "allwinner,sun50i-h616-ir", 718 "allwinner,sun6i-a31-ir"; 719 reg = <0x07040000 0x400>; 720 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&r_ccu CLK_R_APB1_IR>, 722 <&r_ccu CLK_IR>; 723 clock-names = "apb", "ir"; 724 resets = <&r_ccu RST_R_APB1_IR>; 725 pinctrl-names = "default"; 726 pinctrl-0 = <&ir_rx_pin>; 727 status = "disabled"; 728 }; 729 730 r_i2c: i2c@7081400 { 731 compatible = "allwinner,sun50i-h616-i2c", 732 "allwinner,sun8i-v536-i2c", 733 "allwinner,sun6i-a31-i2c"; 734 reg = <0x07081400 0x400>; 735 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&r_ccu CLK_R_APB2_I2C>; 737 resets = <&r_ccu RST_R_APB2_I2C>; 738 status = "disabled"; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 }; 742 743 r_rsb: rsb@7083000 { 744 compatible = "allwinner,sun50i-h616-rsb", 745 "allwinner,sun8i-a23-rsb"; 746 reg = <0x07083000 0x400>; 747 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&r_ccu CLK_R_APB2_RSB>; 749 clock-frequency = <3000000>; 750 resets = <&r_ccu RST_R_APB2_RSB>; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&r_rsb_pins>; 753 status = "disabled"; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 }; 757 }; 758}; 759