1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun50i-h6-ccu.h> 6#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 7#include <dt-bindings/clock/sun6i-rtc.h> 8#include <dt-bindings/clock/sun8i-de2.h> 9#include <dt-bindings/clock/sun8i-tcon-top.h> 10#include <dt-bindings/reset/sun50i-h6-ccu.h> 11#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 12#include <dt-bindings/reset/sun8i-de2.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "arm,cortex-a53"; 26 device_type = "cpu"; 27 reg = <0>; 28 enable-method = "psci"; 29 clocks = <&ccu CLK_CPUX>; 30 clock-latency-ns = <244144>; /* 8 32k periods */ 31 #cooling-cells = <2>; 32 }; 33 34 cpu1: cpu@1 { 35 compatible = "arm,cortex-a53"; 36 device_type = "cpu"; 37 reg = <1>; 38 enable-method = "psci"; 39 clocks = <&ccu CLK_CPUX>; 40 clock-latency-ns = <244144>; /* 8 32k periods */ 41 #cooling-cells = <2>; 42 }; 43 44 cpu2: cpu@2 { 45 compatible = "arm,cortex-a53"; 46 device_type = "cpu"; 47 reg = <2>; 48 enable-method = "psci"; 49 clocks = <&ccu CLK_CPUX>; 50 clock-latency-ns = <244144>; /* 8 32k periods */ 51 #cooling-cells = <2>; 52 }; 53 54 cpu3: cpu@3 { 55 compatible = "arm,cortex-a53"; 56 device_type = "cpu"; 57 reg = <3>; 58 enable-method = "psci"; 59 clocks = <&ccu CLK_CPUX>; 60 clock-latency-ns = <244144>; /* 8 32k periods */ 61 #cooling-cells = <2>; 62 }; 63 }; 64 65 de: display-engine { 66 compatible = "allwinner,sun50i-h6-display-engine"; 67 allwinner,pipelines = <&mixer0>; 68 status = "disabled"; 69 }; 70 71 osc24M: osc24M_clk { 72 #clock-cells = <0>; 73 compatible = "fixed-clock"; 74 clock-frequency = <24000000>; 75 clock-output-names = "osc24M"; 76 }; 77 78 pmu { 79 compatible = "arm,cortex-a53-pmu"; 80 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 85 }; 86 87 psci { 88 compatible = "arm,psci-0.2"; 89 method = "smc"; 90 }; 91 92 timer { 93 compatible = "arm,armv8-timer"; 94 arm,no-tick-in-suspend; 95 interrupts = <GIC_PPI 13 96 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 97 <GIC_PPI 14 98 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 99 <GIC_PPI 11 100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 101 <GIC_PPI 10 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 103 }; 104 105 soc { 106 compatible = "simple-bus"; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges; 110 111 bus@1000000 { 112 compatible = "allwinner,sun50i-h6-de3", 113 "allwinner,sun50i-a64-de2"; 114 reg = <0x1000000 0x400000>; 115 allwinner,sram = <&de2_sram 1>; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges = <0 0x1000000 0x400000>; 119 120 display_clocks: clock@0 { 121 compatible = "allwinner,sun50i-h6-de3-clk"; 122 reg = <0x0 0x10000>; 123 clocks = <&ccu CLK_BUS_DE>, 124 <&ccu CLK_DE>; 125 clock-names = "bus", 126 "mod"; 127 resets = <&ccu RST_BUS_DE>; 128 #clock-cells = <1>; 129 #reset-cells = <1>; 130 }; 131 132 mixer0: mixer@100000 { 133 compatible = "allwinner,sun50i-h6-de3-mixer-0"; 134 reg = <0x100000 0x100000>; 135 clocks = <&display_clocks CLK_BUS_MIXER0>, 136 <&display_clocks CLK_MIXER0>; 137 clock-names = "bus", 138 "mod"; 139 resets = <&display_clocks RST_MIXER0>; 140 iommus = <&iommu 0>; 141 142 ports { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 146 mixer0_out: port@1 { 147 reg = <1>; 148 149 mixer0_out_tcon_top_mixer0: endpoint { 150 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 151 }; 152 }; 153 }; 154 }; 155 }; 156 157 video-codec-g2@1c00000 { 158 compatible = "allwinner,sun50i-h6-vpu-g2"; 159 reg = <0x01c00000 0x1000>; 160 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 161 clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>; 162 clock-names = "bus", "mod"; 163 resets = <&ccu RST_BUS_VP9>; 164 }; 165 166 video-codec@1c0e000 { 167 compatible = "allwinner,sun50i-h6-video-engine"; 168 reg = <0x01c0e000 0x2000>; 169 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 170 <&ccu CLK_MBUS_VE>; 171 clock-names = "ahb", "mod", "ram"; 172 resets = <&ccu RST_BUS_VE>; 173 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 174 allwinner,sram = <&ve_sram 1>; 175 iommus = <&iommu 3>; 176 }; 177 178 gpu: gpu@1800000 { 179 compatible = "allwinner,sun50i-h6-mali", 180 "arm,mali-t720"; 181 reg = <0x01800000 0x4000>; 182 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-names = "job", "mmu", "gpu"; 186 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 187 clock-names = "core", "bus"; 188 resets = <&ccu RST_BUS_GPU>; 189 status = "disabled"; 190 }; 191 192 crypto: crypto@1904000 { 193 compatible = "allwinner,sun50i-h6-crypto"; 194 reg = <0x01904000 0x1000>; 195 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; 197 clock-names = "bus", "mod", "ram"; 198 resets = <&ccu RST_BUS_CE>; 199 }; 200 201 syscon: syscon@3000000 { 202 compatible = "allwinner,sun50i-h6-system-control", 203 "allwinner,sun50i-a64-system-control"; 204 reg = <0x03000000 0x1000>; 205 #address-cells = <1>; 206 #size-cells = <1>; 207 ranges; 208 209 sram_c: sram@28000 { 210 compatible = "mmio-sram"; 211 reg = <0x00028000 0x1e000>; 212 #address-cells = <1>; 213 #size-cells = <1>; 214 ranges = <0 0x00028000 0x1e000>; 215 216 de2_sram: sram-section@0 { 217 compatible = "allwinner,sun50i-h6-sram-c", 218 "allwinner,sun50i-a64-sram-c"; 219 reg = <0x0000 0x1e000>; 220 }; 221 }; 222 223 sram_c1: sram@1a00000 { 224 compatible = "mmio-sram"; 225 reg = <0x01a00000 0x200000>; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 ranges = <0 0x01a00000 0x200000>; 229 230 ve_sram: sram-section@0 { 231 compatible = "allwinner,sun50i-h6-sram-c1", 232 "allwinner,sun4i-a10-sram-c1"; 233 reg = <0x000000 0x200000>; 234 }; 235 }; 236 }; 237 238 ccu: clock@3001000 { 239 compatible = "allwinner,sun50i-h6-ccu"; 240 reg = <0x03001000 0x1000>; 241 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; 242 clock-names = "hosc", "losc", "iosc"; 243 #clock-cells = <1>; 244 #reset-cells = <1>; 245 }; 246 247 dma: dma-controller@3002000 { 248 compatible = "allwinner,sun50i-h6-dma"; 249 reg = <0x03002000 0x1000>; 250 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 252 clock-names = "bus", "mbus"; 253 dma-channels = <16>; 254 dma-requests = <46>; 255 resets = <&ccu RST_BUS_DMA>; 256 #dma-cells = <1>; 257 }; 258 259 msgbox: mailbox@3003000 { 260 compatible = "allwinner,sun50i-h6-msgbox", 261 "allwinner,sun6i-a31-msgbox"; 262 reg = <0x03003000 0x1000>; 263 clocks = <&ccu CLK_BUS_MSGBOX>; 264 resets = <&ccu RST_BUS_MSGBOX>; 265 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 266 #mbox-cells = <1>; 267 }; 268 269 sid: efuse@3006000 { 270 compatible = "allwinner,sun50i-h6-sid"; 271 reg = <0x03006000 0x400>; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 275 ths_calibration: thermal-sensor-calibration@14 { 276 reg = <0x14 0x8>; 277 }; 278 279 cpu_speed_grade: cpu-speed-grade@1c { 280 reg = <0x1c 0x4>; 281 }; 282 }; 283 284 timer@3009000 { 285 compatible = "allwinner,sun50i-h6-timer", 286 "allwinner,sun8i-a23-timer"; 287 reg = <0x03009000 0xa0>; 288 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&osc24M>; 291 }; 292 293 watchdog: watchdog@30090a0 { 294 compatible = "allwinner,sun50i-h6-wdt", 295 "allwinner,sun6i-a31-wdt"; 296 reg = <0x030090a0 0x20>; 297 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&osc24M>; 299 /* Broken on some H6 boards */ 300 status = "disabled"; 301 }; 302 303 pwm: pwm@300a000 { 304 compatible = "allwinner,sun50i-h6-pwm"; 305 reg = <0x0300a000 0x400>; 306 clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; 307 clock-names = "mod", "bus"; 308 resets = <&ccu RST_BUS_PWM>; 309 #pwm-cells = <3>; 310 status = "disabled"; 311 }; 312 313 pio: pinctrl@300b000 { 314 compatible = "allwinner,sun50i-h6-pinctrl"; 315 reg = <0x0300b000 0x400>; 316 interrupt-parent = <&r_intc>; 317 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 322 clock-names = "apb", "hosc", "losc"; 323 gpio-controller; 324 #gpio-cells = <3>; 325 interrupt-controller; 326 #interrupt-cells = <3>; 327 328 ext_rgmii_pins: rgmii-pins { 329 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 330 "PD5", "PD7", "PD8", "PD9", "PD10", 331 "PD11", "PD12", "PD13", "PD19", "PD20"; 332 function = "emac"; 333 drive-strength = <40>; 334 }; 335 336 hdmi_pins: hdmi-pins { 337 pins = "PH8", "PH9", "PH10"; 338 function = "hdmi"; 339 }; 340 341 i2c0_pins: i2c0-pins { 342 pins = "PD25", "PD26"; 343 function = "i2c0"; 344 }; 345 346 i2c1_pins: i2c1-pins { 347 pins = "PH5", "PH6"; 348 function = "i2c1"; 349 }; 350 351 i2c2_pins: i2c2-pins { 352 pins = "PD23", "PD24"; 353 function = "i2c2"; 354 }; 355 356 mmc0_pins: mmc0-pins { 357 pins = "PF0", "PF1", "PF2", "PF3", 358 "PF4", "PF5"; 359 function = "mmc0"; 360 drive-strength = <30>; 361 bias-pull-up; 362 }; 363 364 /omit-if-no-ref/ 365 mmc1_pins: mmc1-pins { 366 pins = "PG0", "PG1", "PG2", "PG3", 367 "PG4", "PG5"; 368 function = "mmc1"; 369 drive-strength = <30>; 370 bias-pull-up; 371 }; 372 373 mmc2_pins: mmc2-pins { 374 pins = "PC1", "PC4", "PC5", "PC6", 375 "PC7", "PC8", "PC9", "PC10", 376 "PC11", "PC12", "PC13", "PC14"; 377 function = "mmc2"; 378 drive-strength = <30>; 379 bias-pull-up; 380 }; 381 382 /omit-if-no-ref/ 383 spi0_pins: spi0-pins { 384 pins = "PC0", "PC2", "PC3"; 385 function = "spi0"; 386 }; 387 388 /* pin shared with MMC2-CMD (eMMC) */ 389 /omit-if-no-ref/ 390 spi0_cs_pin: spi0-cs-pin { 391 pins = "PC5"; 392 function = "spi0"; 393 }; 394 395 /omit-if-no-ref/ 396 spi1_pins: spi1-pins { 397 pins = "PH4", "PH5", "PH6"; 398 function = "spi1"; 399 }; 400 401 /omit-if-no-ref/ 402 spi1_cs_pin: spi1-cs-pin { 403 pins = "PH3"; 404 function = "spi1"; 405 }; 406 407 spdif_tx_pin: spdif-tx-pin { 408 pins = "PH7"; 409 function = "spdif"; 410 }; 411 412 uart0_ph_pins: uart0-ph-pins { 413 pins = "PH0", "PH1"; 414 function = "uart0"; 415 }; 416 417 uart1_pins: uart1-pins { 418 pins = "PG6", "PG7"; 419 function = "uart1"; 420 }; 421 422 uart1_rts_cts_pins: uart1-rts-cts-pins { 423 pins = "PG8", "PG9"; 424 function = "uart1"; 425 }; 426 }; 427 428 gic: interrupt-controller@3021000 { 429 compatible = "arm,gic-400"; 430 reg = <0x03021000 0x1000>, 431 <0x03022000 0x2000>, 432 <0x03024000 0x2000>, 433 <0x03026000 0x2000>; 434 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 435 interrupt-controller; 436 #interrupt-cells = <3>; 437 }; 438 439 iommu: iommu@30f0000 { 440 compatible = "allwinner,sun50i-h6-iommu"; 441 reg = <0x030f0000 0x10000>; 442 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&ccu CLK_BUS_IOMMU>; 444 resets = <&ccu RST_BUS_IOMMU>; 445 #iommu-cells = <1>; 446 }; 447 448 mmc0: mmc@4020000 { 449 compatible = "allwinner,sun50i-h6-mmc", 450 "allwinner,sun50i-a64-mmc"; 451 reg = <0x04020000 0x1000>; 452 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 453 clock-names = "ahb", "mmc"; 454 resets = <&ccu RST_BUS_MMC0>; 455 reset-names = "ahb"; 456 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&mmc0_pins>; 459 max-frequency = <150000000>; 460 status = "disabled"; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 }; 464 465 mmc1: mmc@4021000 { 466 compatible = "allwinner,sun50i-h6-mmc", 467 "allwinner,sun50i-a64-mmc"; 468 reg = <0x04021000 0x1000>; 469 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 470 clock-names = "ahb", "mmc"; 471 resets = <&ccu RST_BUS_MMC1>; 472 reset-names = "ahb"; 473 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&mmc1_pins>; 476 max-frequency = <150000000>; 477 status = "disabled"; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 }; 481 482 mmc2: mmc@4022000 { 483 compatible = "allwinner,sun50i-h6-emmc", 484 "allwinner,sun50i-a64-emmc"; 485 reg = <0x04022000 0x1000>; 486 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 487 clock-names = "ahb", "mmc"; 488 resets = <&ccu RST_BUS_MMC2>; 489 reset-names = "ahb"; 490 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 491 pinctrl-names = "default"; 492 pinctrl-0 = <&mmc2_pins>; 493 max-frequency = <150000000>; 494 status = "disabled"; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 }; 498 499 uart0: serial@5000000 { 500 compatible = "snps,dw-apb-uart"; 501 reg = <0x05000000 0x400>; 502 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 503 reg-shift = <2>; 504 reg-io-width = <4>; 505 clocks = <&ccu CLK_BUS_UART0>; 506 resets = <&ccu RST_BUS_UART0>; 507 status = "disabled"; 508 }; 509 510 uart1: serial@5000400 { 511 compatible = "snps,dw-apb-uart"; 512 reg = <0x05000400 0x400>; 513 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 514 reg-shift = <2>; 515 reg-io-width = <4>; 516 clocks = <&ccu CLK_BUS_UART1>; 517 resets = <&ccu RST_BUS_UART1>; 518 status = "disabled"; 519 }; 520 521 uart2: serial@5000800 { 522 compatible = "snps,dw-apb-uart"; 523 reg = <0x05000800 0x400>; 524 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 525 reg-shift = <2>; 526 reg-io-width = <4>; 527 clocks = <&ccu CLK_BUS_UART2>; 528 resets = <&ccu RST_BUS_UART2>; 529 status = "disabled"; 530 }; 531 532 uart3: serial@5000c00 { 533 compatible = "snps,dw-apb-uart"; 534 reg = <0x05000c00 0x400>; 535 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 536 reg-shift = <2>; 537 reg-io-width = <4>; 538 clocks = <&ccu CLK_BUS_UART3>; 539 resets = <&ccu RST_BUS_UART3>; 540 status = "disabled"; 541 }; 542 543 i2c0: i2c@5002000 { 544 compatible = "allwinner,sun50i-h6-i2c", 545 "allwinner,sun6i-a31-i2c"; 546 reg = <0x05002000 0x400>; 547 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&ccu CLK_BUS_I2C0>; 549 resets = <&ccu RST_BUS_I2C0>; 550 pinctrl-names = "default"; 551 pinctrl-0 = <&i2c0_pins>; 552 status = "disabled"; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 }; 556 557 i2c1: i2c@5002400 { 558 compatible = "allwinner,sun50i-h6-i2c", 559 "allwinner,sun6i-a31-i2c"; 560 reg = <0x05002400 0x400>; 561 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&ccu CLK_BUS_I2C1>; 563 resets = <&ccu RST_BUS_I2C1>; 564 pinctrl-names = "default"; 565 pinctrl-0 = <&i2c1_pins>; 566 status = "disabled"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 }; 570 571 i2c2: i2c@5002800 { 572 compatible = "allwinner,sun50i-h6-i2c", 573 "allwinner,sun6i-a31-i2c"; 574 reg = <0x05002800 0x400>; 575 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&ccu CLK_BUS_I2C2>; 577 resets = <&ccu RST_BUS_I2C2>; 578 pinctrl-names = "default"; 579 pinctrl-0 = <&i2c2_pins>; 580 status = "disabled"; 581 #address-cells = <1>; 582 #size-cells = <0>; 583 }; 584 585 spi0: spi@5010000 { 586 compatible = "allwinner,sun50i-h6-spi", 587 "allwinner,sun8i-h3-spi"; 588 reg = <0x05010000 0x1000>; 589 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 591 clock-names = "ahb", "mod"; 592 dmas = <&dma 22>, <&dma 22>; 593 dma-names = "rx", "tx"; 594 resets = <&ccu RST_BUS_SPI0>; 595 status = "disabled"; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 }; 599 600 spi1: spi@5011000 { 601 compatible = "allwinner,sun50i-h6-spi", 602 "allwinner,sun8i-h3-spi"; 603 reg = <0x05011000 0x1000>; 604 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 605 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 606 clock-names = "ahb", "mod"; 607 dmas = <&dma 23>, <&dma 23>; 608 dma-names = "rx", "tx"; 609 resets = <&ccu RST_BUS_SPI1>; 610 status = "disabled"; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 }; 614 615 emac: ethernet@5020000 { 616 compatible = "allwinner,sun50i-h6-emac", 617 "allwinner,sun50i-a64-emac"; 618 syscon = <&syscon>; 619 reg = <0x05020000 0x10000>; 620 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 621 interrupt-names = "macirq"; 622 resets = <&ccu RST_BUS_EMAC>; 623 reset-names = "stmmaceth"; 624 clocks = <&ccu CLK_BUS_EMAC>; 625 clock-names = "stmmaceth"; 626 status = "disabled"; 627 628 mdio: mdio { 629 compatible = "snps,dwmac-mdio"; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 }; 633 }; 634 635 i2s1: i2s@5091000 { 636 #sound-dai-cells = <0>; 637 compatible = "allwinner,sun50i-h6-i2s"; 638 reg = <0x05091000 0x1000>; 639 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 641 clock-names = "apb", "mod"; 642 dmas = <&dma 4>, <&dma 4>; 643 resets = <&ccu RST_BUS_I2S1>; 644 dma-names = "rx", "tx"; 645 status = "disabled"; 646 }; 647 648 spdif: spdif@5093000 { 649 #sound-dai-cells = <0>; 650 compatible = "allwinner,sun50i-h6-spdif"; 651 reg = <0x05093000 0x400>; 652 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 654 clock-names = "apb", "spdif"; 655 resets = <&ccu RST_BUS_SPDIF>; 656 dmas = <&dma 2>; 657 dma-names = "tx"; 658 pinctrl-names = "default"; 659 pinctrl-0 = <&spdif_tx_pin>; 660 status = "disabled"; 661 }; 662 663 usb2otg: usb@5100000 { 664 compatible = "allwinner,sun50i-h6-musb", 665 "allwinner,sun8i-a33-musb"; 666 reg = <0x05100000 0x0400>; 667 clocks = <&ccu CLK_BUS_OTG>; 668 resets = <&ccu RST_BUS_OTG>; 669 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 670 interrupt-names = "mc"; 671 phys = <&usb2phy 0>; 672 phy-names = "usb"; 673 extcon = <&usb2phy 0>; 674 status = "disabled"; 675 }; 676 677 usb2phy: phy@5100400 { 678 compatible = "allwinner,sun50i-h6-usb-phy"; 679 reg = <0x05100400 0x24>, 680 <0x05101800 0x4>, 681 <0x05311800 0x4>; 682 reg-names = "phy_ctrl", 683 "pmu0", 684 "pmu3"; 685 clocks = <&ccu CLK_USB_PHY0>, 686 <&ccu CLK_USB_PHY3>; 687 clock-names = "usb0_phy", 688 "usb3_phy"; 689 resets = <&ccu RST_USB_PHY0>, 690 <&ccu RST_USB_PHY3>; 691 reset-names = "usb0_reset", 692 "usb3_reset"; 693 status = "disabled"; 694 #phy-cells = <1>; 695 }; 696 697 ehci0: usb@5101000 { 698 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 699 reg = <0x05101000 0x100>; 700 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&ccu CLK_BUS_OHCI0>, 702 <&ccu CLK_BUS_EHCI0>, 703 <&ccu CLK_USB_OHCI0>; 704 resets = <&ccu RST_BUS_OHCI0>, 705 <&ccu RST_BUS_EHCI0>; 706 phys = <&usb2phy 0>; 707 phy-names = "usb"; 708 status = "disabled"; 709 }; 710 711 ohci0: usb@5101400 { 712 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 713 reg = <0x05101400 0x100>; 714 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&ccu CLK_BUS_OHCI0>, 716 <&ccu CLK_USB_OHCI0>; 717 resets = <&ccu RST_BUS_OHCI0>; 718 phys = <&usb2phy 0>; 719 phy-names = "usb"; 720 status = "disabled"; 721 }; 722 723 dwc3: usb@5200000 { 724 compatible = "snps,dwc3"; 725 reg = <0x05200000 0x10000>; 726 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&ccu CLK_BUS_XHCI>, 728 <&ccu CLK_BUS_XHCI>, 729 <&rtc CLK_OSC32K>; 730 clock-names = "ref", "bus_early", "suspend"; 731 resets = <&ccu RST_BUS_XHCI>; 732 /* 733 * The datasheet of the chip doesn't declare the 734 * peripheral function, and there's no boards known 735 * to have a USB Type-B port routed to the port. 736 * In addition, no one has tested the peripheral 737 * function yet. 738 * So set the dr_mode to "host" in the DTSI file. 739 */ 740 dr_mode = "host"; 741 phys = <&usb3phy>; 742 phy-names = "usb3-phy"; 743 status = "disabled"; 744 }; 745 746 usb3phy: phy@5210000 { 747 compatible = "allwinner,sun50i-h6-usb3-phy"; 748 reg = <0x5210000 0x10000>; 749 clocks = <&ccu CLK_USB_PHY1>; 750 resets = <&ccu RST_USB_PHY1>; 751 #phy-cells = <0>; 752 status = "disabled"; 753 }; 754 755 ehci3: usb@5311000 { 756 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 757 reg = <0x05311000 0x100>; 758 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&ccu CLK_BUS_OHCI3>, 760 <&ccu CLK_BUS_EHCI3>, 761 <&ccu CLK_USB_OHCI3>; 762 resets = <&ccu RST_BUS_OHCI3>, 763 <&ccu RST_BUS_EHCI3>; 764 phys = <&usb2phy 3>; 765 phy-names = "usb"; 766 status = "disabled"; 767 }; 768 769 ohci3: usb@5311400 { 770 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 771 reg = <0x05311400 0x100>; 772 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&ccu CLK_BUS_OHCI3>, 774 <&ccu CLK_USB_OHCI3>; 775 resets = <&ccu RST_BUS_OHCI3>; 776 phys = <&usb2phy 3>; 777 phy-names = "usb"; 778 status = "disabled"; 779 }; 780 781 hdmi: hdmi@6000000 { 782 compatible = "allwinner,sun50i-h6-dw-hdmi"; 783 reg = <0x06000000 0x10000>; 784 reg-io-width = <1>; 785 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 787 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 788 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 789 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 790 "hdcp-bus"; 791 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 792 reset-names = "ctrl", "hdcp"; 793 phys = <&hdmi_phy>; 794 phy-names = "phy"; 795 pinctrl-names = "default"; 796 pinctrl-0 = <&hdmi_pins>; 797 status = "disabled"; 798 799 ports { 800 #address-cells = <1>; 801 #size-cells = <0>; 802 803 hdmi_in: port@0 { 804 reg = <0>; 805 806 hdmi_in_tcon_top: endpoint { 807 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 808 }; 809 }; 810 811 hdmi_out: port@1 { 812 reg = <1>; 813 }; 814 }; 815 }; 816 817 hdmi_phy: hdmi-phy@6010000 { 818 compatible = "allwinner,sun50i-h6-hdmi-phy"; 819 reg = <0x06010000 0x10000>; 820 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 821 clock-names = "bus", "mod"; 822 resets = <&ccu RST_BUS_HDMI>; 823 reset-names = "phy"; 824 #phy-cells = <0>; 825 }; 826 827 tcon_top: tcon-top@6510000 { 828 compatible = "allwinner,sun50i-h6-tcon-top"; 829 reg = <0x06510000 0x1000>; 830 clocks = <&ccu CLK_BUS_TCON_TOP>, 831 <&ccu CLK_TCON_TV0>; 832 clock-names = "bus", 833 "tcon-tv0"; 834 clock-output-names = "tcon-top-tv0"; 835 resets = <&ccu RST_BUS_TCON_TOP>; 836 #clock-cells = <1>; 837 838 ports { 839 #address-cells = <1>; 840 #size-cells = <0>; 841 842 tcon_top_mixer0_in: port@0 { 843 #address-cells = <1>; 844 #size-cells = <0>; 845 reg = <0>; 846 847 tcon_top_mixer0_in_mixer0: endpoint@0 { 848 reg = <0>; 849 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 850 }; 851 }; 852 853 tcon_top_mixer0_out: port@1 { 854 #address-cells = <1>; 855 #size-cells = <0>; 856 reg = <1>; 857 858 tcon_top_mixer0_out_tcon_tv: endpoint@2 { 859 reg = <2>; 860 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; 861 }; 862 }; 863 864 tcon_top_hdmi_in: port@4 { 865 #address-cells = <1>; 866 #size-cells = <0>; 867 reg = <4>; 868 869 tcon_top_hdmi_in_tcon_tv: endpoint@0 { 870 reg = <0>; 871 remote-endpoint = <&tcon_tv_out_tcon_top>; 872 }; 873 }; 874 875 tcon_top_hdmi_out: port@5 { 876 reg = <5>; 877 878 tcon_top_hdmi_out_hdmi: endpoint { 879 remote-endpoint = <&hdmi_in_tcon_top>; 880 }; 881 }; 882 }; 883 }; 884 885 tcon_tv: lcd-controller@6515000 { 886 compatible = "allwinner,sun50i-h6-tcon-tv", 887 "allwinner,sun8i-r40-tcon-tv"; 888 reg = <0x06515000 0x1000>; 889 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&ccu CLK_BUS_TCON_TV0>, 891 <&tcon_top CLK_TCON_TOP_TV0>; 892 clock-names = "ahb", 893 "tcon-ch1"; 894 resets = <&ccu RST_BUS_TCON_TV0>; 895 reset-names = "lcd"; 896 897 ports { 898 #address-cells = <1>; 899 #size-cells = <0>; 900 901 tcon_tv_in: port@0 { 902 reg = <0>; 903 904 tcon_tv_in_tcon_top_mixer0: endpoint { 905 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; 906 }; 907 }; 908 909 tcon_tv_out: port@1 { 910 #address-cells = <1>; 911 #size-cells = <0>; 912 reg = <1>; 913 914 tcon_tv_out_tcon_top: endpoint@1 { 915 reg = <1>; 916 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; 917 }; 918 }; 919 }; 920 }; 921 922 rtc: rtc@7000000 { 923 compatible = "allwinner,sun50i-h6-rtc"; 924 reg = <0x07000000 0x400>; 925 interrupt-parent = <&r_intc>; 926 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 928 clock-output-names = "osc32k", "osc32k-out", "iosc"; 929 #clock-cells = <1>; 930 }; 931 932 r_ccu: clock@7010000 { 933 compatible = "allwinner,sun50i-h6-r-ccu"; 934 reg = <0x07010000 0x400>; 935 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 936 <&ccu CLK_PLL_PERIPH0>; 937 clock-names = "hosc", "losc", "iosc", "pll-periph"; 938 #clock-cells = <1>; 939 #reset-cells = <1>; 940 }; 941 942 r_watchdog: watchdog@7020400 { 943 compatible = "allwinner,sun50i-h6-wdt", 944 "allwinner,sun6i-a31-wdt"; 945 reg = <0x07020400 0x20>; 946 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&osc24M>; 948 }; 949 950 r_intc: interrupt-controller@7021000 { 951 compatible = "allwinner,sun50i-h6-r-intc"; 952 interrupt-controller; 953 #interrupt-cells = <3>; 954 reg = <0x07021000 0x400>; 955 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 956 }; 957 958 r_pio: pinctrl@7022000 { 959 compatible = "allwinner,sun50i-h6-r-pinctrl"; 960 reg = <0x07022000 0x400>; 961 interrupt-parent = <&r_intc>; 962 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, 965 <&rtc CLK_OSC32K>; 966 clock-names = "apb", "hosc", "losc"; 967 gpio-controller; 968 #gpio-cells = <3>; 969 interrupt-controller; 970 #interrupt-cells = <3>; 971 972 r_i2c_pins: r-i2c-pins { 973 pins = "PL0", "PL1"; 974 function = "s_i2c"; 975 }; 976 977 r_ir_rx_pin: r-ir-rx-pin { 978 pins = "PL9"; 979 function = "s_cir_rx"; 980 }; 981 982 r_rsb_pins: r-rsb-pins { 983 pins = "PL0", "PL1"; 984 function = "s_rsb"; 985 }; 986 }; 987 988 r_ir: ir@7040000 { 989 compatible = "allwinner,sun50i-h6-ir", 990 "allwinner,sun6i-a31-ir"; 991 reg = <0x07040000 0x400>; 992 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 993 clocks = <&r_ccu CLK_R_APB1_IR>, 994 <&r_ccu CLK_IR>; 995 clock-names = "apb", "ir"; 996 resets = <&r_ccu RST_R_APB1_IR>; 997 pinctrl-names = "default"; 998 pinctrl-0 = <&r_ir_rx_pin>; 999 status = "disabled"; 1000 }; 1001 1002 r_i2c: i2c@7081400 { 1003 compatible = "allwinner,sun50i-h6-i2c", 1004 "allwinner,sun6i-a31-i2c"; 1005 reg = <0x07081400 0x400>; 1006 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&r_ccu CLK_R_APB2_I2C>; 1008 resets = <&r_ccu RST_R_APB2_I2C>; 1009 pinctrl-names = "default"; 1010 pinctrl-0 = <&r_i2c_pins>; 1011 status = "disabled"; 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 }; 1015 1016 r_rsb: rsb@7083000 { 1017 compatible = "allwinner,sun8i-a23-rsb"; 1018 reg = <0x07083000 0x400>; 1019 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&r_ccu CLK_R_APB2_RSB>; 1021 clock-frequency = <3000000>; 1022 resets = <&r_ccu RST_R_APB2_RSB>; 1023 pinctrl-names = "default"; 1024 pinctrl-0 = <&r_rsb_pins>; 1025 status = "disabled"; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 }; 1029 1030 ths: thermal-sensor@5070400 { 1031 compatible = "allwinner,sun50i-h6-ths"; 1032 reg = <0x05070400 0x100>; 1033 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&ccu CLK_BUS_THS>; 1035 clock-names = "bus"; 1036 resets = <&ccu RST_BUS_THS>; 1037 nvmem-cells = <&ths_calibration>; 1038 nvmem-cell-names = "calibration"; 1039 #thermal-sensor-cells = <1>; 1040 }; 1041 }; 1042 1043 thermal-zones { 1044 cpu-thermal { 1045 polling-delay-passive = <0>; 1046 polling-delay = <0>; 1047 thermal-sensors = <&ths 0>; 1048 1049 trips { 1050 cpu_alert: cpu-alert { 1051 temperature = <85000>; 1052 hysteresis = <2000>; 1053 type = "passive"; 1054 }; 1055 1056 cpu-crit { 1057 temperature = <100000>; 1058 hysteresis = <0>; 1059 type = "critical"; 1060 }; 1061 }; 1062 1063 cooling-maps { 1064 map0 { 1065 trip = <&cpu_alert>; 1066 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1067 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1068 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1069 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1070 }; 1071 }; 1072 }; 1073 1074 gpu-thermal { 1075 polling-delay-passive = <0>; 1076 polling-delay = <0>; 1077 thermal-sensors = <&ths 1>; 1078 }; 1079 }; 1080}; 1081